Roll SwiftShader from bbe6452b420c to 9aec4b969291 (10 revisions)
https://swiftshader.googlesource.com/SwiftShader.git/+log/bbe6452b420c..9aec4b969291
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https://autoroll.skia.org/r/swiftshader-android
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is aware of the problem.
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https://issues.skia.org/issues/new?component=1389291&template=1850622
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Change-Id: I28bf3be8f9fdbb91f18d7c077f9a7571c3429243
diff --git a/CMakeLists.txt b/CMakeLists.txt
index fc252f8..434fbb7 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -84,6 +84,17 @@
endif()
endif()
+# Cross compiling with `cmake -A <arch>`.
+if(CMAKE_GENERATOR_PLATFORM)
+ if(CMAKE_GENERATOR_PLATFORM MATCHES "^(Win32|win32|X86|x86)$")
+ set(ARCH "x86")
+ elseif(CMAKE_GENERATOR_PLATFORM MATCHES "^(Win64|win64|X64|x64)$")
+ set(ARCH "x86_64")
+ elseif(CMAKE_GENERATOR_PLATFORM MATCHES "^(ARM64|Arm64|arm64)$")
+ set(ARCH "aarch64")
+ endif()
+endif()
+
set(CMAKE_MACOSX_RPATH TRUE)
if ((CMAKE_GENERATOR MATCHES "Visual Studio") AND (CMAKE_GENERATOR_TOOLSET STREQUAL ""))
diff --git a/src/Device/Context.cpp b/src/Device/Context.cpp
index 1cecc19..71c6811 100644
--- a/src/Device/Context.cpp
+++ b/src/Device/Context.cpp
@@ -315,12 +315,6 @@
void Inputs::initialize(const VkPipelineVertexInputStateCreateInfo *vertexInputState, const VkPipelineDynamicStateCreateInfo *dynamicStateCreateInfo)
{
- if(vertexInputState->flags != 0)
- {
- // Vulkan 1.2: "flags is reserved for future use." "flags must be 0"
- UNSUPPORTED("vertexInputState->flags");
- }
-
dynamicStateFlags = ParseInputsDynamicStateFlags(dynamicStateCreateInfo);
if(dynamicStateFlags.dynamicVertexInput)
@@ -328,6 +322,12 @@
return;
}
+ if(vertexInputState->flags != 0)
+ {
+ // Vulkan 1.2: "flags is reserved for future use." "flags must be 0"
+ UNSUPPORTED("vertexInputState->flags");
+ }
+
// Temporary in-binding-order representation of buffer strides, to be consumed below
// when considering attributes. TODO: unfuse buffers from attributes in backend, is old GL model.
uint32_t vertexStrides[MAX_VERTEX_INPUT_BINDINGS];
@@ -513,7 +513,7 @@
{
dynamicStateFlags = allDynamicStateFlags.vertexInputInterface;
- if(vertexInputState->flags != 0)
+ if(vertexInputState && vertexInputState->flags != 0)
{
// Vulkan 1.2: "flags is reserved for future use." "flags must be 0"
UNSUPPORTED("vertexInputState->flags");
diff --git a/src/Reactor/Debug.cpp b/src/Reactor/Debug.cpp
index 031524d..cdb1afc 100644
--- a/src/Reactor/Debug.cpp
+++ b/src/Reactor/Debug.cpp
@@ -106,7 +106,7 @@
};
#ifdef __ANDROID__
-void logv_android(Level level, const char *msg)
+[[maybe_unused]] void logv_android(Level level, const char *msg)
{
switch(level)
{
@@ -128,7 +128,7 @@
}
}
#else
-void logv_std(Level level, const char *msg)
+[[maybe_unused]] void logv_std(Level level, const char *msg)
{
switch(level)
{
diff --git a/src/Reactor/LLVMJIT.cpp b/src/Reactor/LLVMJIT.cpp
index 0f61e07..262c69e 100644
--- a/src/Reactor/LLVMJIT.cpp
+++ b/src/Reactor/LLVMJIT.cpp
@@ -28,8 +28,8 @@
// See https://groups.google.com/g/llvm-dev/c/CAE7Va57h2c/m/74ITeXFEAQAJ
// for information about `RTDyldObjectLinkingLayer` vs `ObjectLinkingLayer`.
-// On RISC-V, only `ObjectLinkingLayer` is supported.
-#if defined(__riscv)
+// On RISC-V and LoongArch, only `ObjectLinkingLayer` is supported.
+#if defined(__riscv) || defined(__loongarch__)
#define USE_LEGACY_OBJECT_LINKING_LAYER 0
#else
#define USE_LEGACY_OBJECT_LINKING_LAYER 1
@@ -250,6 +250,11 @@
// On RISC-V, using the default code model results in an
// "Unsupported riscv relocation" error.
jitTargetMachineBuilder.setCodeModel(llvm::CodeModel::Medium);
+#elif defined(__loongarch__)
+ // jitTargetMachineBuilder.getFeatures() on LoongArch does
+ // not return the LoongArch CPU extensions, so they are
+ // manually added.
+ jitTargetMachineBuilder.getFeatures().AddFeature("+d");
#endif
jitTargetMachineBuilder.setCPU(std::string(llvm::sys::getHostCPUName()));
diff --git a/src/Reactor/reactor.gni b/src/Reactor/reactor.gni
index 04fad6f..51cb8fb 100644
--- a/src/Reactor/reactor.gni
+++ b/src/Reactor/reactor.gni
@@ -9,8 +9,8 @@
import("//build_overrides/build.gni")
declare_args() {
- # Subzero doesn't support ARM64, MIPS64, PPC64, and RISCV64 (only x86 and ARMv7a).
- supports_subzero = current_cpu != "arm64" && current_cpu != "mips64el" && current_cpu != "ppc64" && current_cpu != "riscv64"
+ # Subzero doesn't support ARM64, LOONGARCH64, MIPS64, PPC64, and RISCV64 (only x86 and ARMv7a).
+ supports_subzero = current_cpu != "arm64" && current_cpu != "mips64el" && current_cpu != "ppc64" && current_cpu != "riscv64" && current_cpu != "loong64"
}
declare_args() {
diff --git a/src/System/Debug.cpp b/src/System/Debug.cpp
index ce86d1c..2b5eb63 100644
--- a/src/System/Debug.cpp
+++ b/src/System/Debug.cpp
@@ -56,7 +56,7 @@
};
#ifdef __ANDROID__
-void logv_android(Level level, const char *msg)
+[[maybe_unused]] void logv_android(Level level, const char *msg)
{
switch(level)
{
@@ -80,7 +80,7 @@
}
}
#else
-void logv_std(Level level, const char *msg)
+[[maybe_unused]] void logv_std(Level level, const char *msg)
{
switch(level)
{
@@ -127,8 +127,8 @@
vfprintf(file, format, args);
fclose(file);
}
- }
#endif // SWIFTSHADER_DISABLE_TRACE
+ }
}
} // anonymous namespace
diff --git a/src/Vulkan/VkRenderPass.cpp b/src/Vulkan/VkRenderPass.cpp
index 135fbde..e0feb2a 100644
--- a/src/Vulkan/VkRenderPass.cpp
+++ b/src/Vulkan/VkRenderPass.cpp
@@ -164,6 +164,12 @@
{
if(subpassDepthStencilResolves == nullptr)
{
+ // Align host memory to 8-bytes
+ const intptr_t memoryAsInt = reinterpret_cast<intptr_t>(hostMemory);
+ const intptr_t alignment = alignof(VkSubpassDescriptionDepthStencilResolve);
+ const intptr_t padding = (alignment - memoryAsInt % alignment) % alignment;
+ hostMemory += padding;
+
subpassDepthStencilResolves = reinterpret_cast<VkSubpassDescriptionDepthStencilResolve *>(hostMemory);
hostMemory += subpassCount * sizeof(VkSubpassDescriptionDepthStencilResolve);
for(uint32_t subpass = 0; subpass < subpassCount; subpass++)
@@ -401,7 +407,9 @@
{
// If any subpass uses DSR, then allocate a VkSubpassDescriptionDepthStencilResolve
// for all subpasses. This allows us to index into our DSR structs using the subpass index.
- requiredMemory += sizeof(VkSubpassDescriptionDepthStencilResolve) * pCreateInfo->subpassCount;
+ //
+ // Add a few bytes for alignment if necessary
+ requiredMemory += sizeof(VkSubpassDescriptionDepthStencilResolve) * pCreateInfo->subpassCount + alignof(VkSubpassDescriptionDepthStencilResolve);
usesDSR = true;
}
// For each subpass that actually uses DSR, allocate a VkAttachmentReference2.
diff --git a/third_party/llvm-10.0/configs/windows/include/llvm/Config/llvm-config.h b/third_party/llvm-10.0/configs/windows/include/llvm/Config/llvm-config.h
index 098a22c..34f8823 100644
--- a/third_party/llvm-10.0/configs/windows/include/llvm/Config/llvm-config.h
+++ b/third_party/llvm-10.0/configs/windows/include/llvm/Config/llvm-config.h
@@ -22,6 +22,10 @@
#define __x86_64__ 1
#endif
+#if !defined(__aarch64__) && (defined(_M_ARM64) || defined (_M_ARM64EC))
+#define __aarch64__ 1
+#endif
+
#define LLVM_CONFIG_H
/* Define if LLVM_ENABLE_DUMP is enabled */
diff --git a/third_party/llvm-16.0/Android.bp b/third_party/llvm-16.0/Android.bp
index b2832f8..02c015c 100644
--- a/third_party/llvm-16.0/Android.bp
+++ b/third_party/llvm-16.0/Android.bp
@@ -1533,5 +1533,6 @@
srcs: [
"llvm/lib/Analysis/RegionPrinter.cpp",
+ "llvm/lib/MC/MCDisassembler/MCDisassembler.cpp",
],
}
diff --git a/third_party/llvm-16.0/BUILD.gn b/third_party/llvm-16.0/BUILD.gn
index 13f5cc3..891a790 100644
--- a/third_party/llvm-16.0/BUILD.gn
+++ b/third_party/llvm-16.0/BUILD.gn
@@ -97,6 +97,7 @@
"llvm/include/",
"llvm/lib/Target/AArch64/",
"llvm/lib/Target/ARM/",
+ "llvm/lib/Target/LoongArch/",
"llvm/lib/Target/Mips/",
"llvm/lib/Target/PowerPC/",
"llvm/lib/Target/RISCV/",
@@ -106,6 +107,7 @@
"configs/common/lib/IR/",
"configs/common/lib/Target/AArch64/",
"configs/common/lib/Target/ARM/",
+ "configs/common/lib/Target/LoongArch/",
"configs/common/lib/Target/Mips/",
"configs/common/lib/Target/PowerPC/",
"configs/common/lib/Target/RISCV/",
@@ -158,10 +160,16 @@
]
+ if (is_debug) {
+ deps += [ ":swiftshader_llvm_debug" ]
+ }
+
if (current_cpu == "arm64") {
deps += [ ":swiftshader_llvm_aarch64" ]
} else if (current_cpu == "arm") {
deps += [ ":swiftshader_llvm_arm" ]
+ } else if (current_cpu == "loong64") {
+ deps += [ ":swiftshader_llvm_loongarch64" ]
} else if (current_cpu == "mipsel" || current_cpu == "mips64el") {
deps += [ ":swiftshader_llvm_mips" ]
} else if (current_cpu == "ppc64") {
@@ -613,7 +621,6 @@
"llvm/lib/DebugInfo/DWARF/DWARFAbbreviationDeclaration.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFAddressRange.cpp",
- "llvm/lib/DebugInfo/DWARF/DWARFCompileUnit.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFContext.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFDataExtractor.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFDebugAbbrev.cpp",
@@ -629,13 +636,11 @@
"llvm/lib/DebugInfo/DWARF/DWARFDebugRangeList.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFDebugRnglists.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFDie.cpp",
- "llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFFormValue.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFGdbIndex.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFListTable.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFTypePrinter.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFTypeUnit.cpp",
- "llvm/lib/DebugInfo/DWARF/DWARFUnit.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFUnitIndex.cpp",
"llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp",
"llvm/lib/Demangle/DLangDemangle.cpp",
@@ -1256,6 +1261,9 @@
}
swiftshader_llvm_source_set("swiftshader_llvm_source_set_1") {
sources = [
+ "llvm/lib/DebugInfo/DWARF/DWARFCompileUnit.cpp",
+ "llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp",
+ "llvm/lib/DebugInfo/DWARF/DWARFUnit.cpp",
"llvm/lib/ExecutionEngine/JITLink/COFF.cpp",
"llvm/lib/ExecutionEngine/JITLink/MachO.cpp",
"llvm/lib/IRPrinter/IRPrintingPasses.cpp",
@@ -1270,6 +1278,13 @@
}
+swiftshader_llvm_source_set("swiftshader_llvm_debug") {
+ sources = [
+ "llvm/lib/Analysis/RegionPrinter.cpp",
+ "llvm/lib/MC/MCDisassembler/MCDisassembler.cpp",
+ ]
+}
+
swiftshader_llvm_source_set("swiftshader_llvm_aarch64") {
sources = [
"llvm/lib/CodeGen/MultiHazardRecognizer.cpp",
@@ -1432,6 +1447,38 @@
}
}
+swiftshader_llvm_source_set("swiftshader_llvm_loongarch64") {
+ sources = [
+ "llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp",
+ "llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp",
+ "llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp",
+ "llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp",
+ "llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp",
+ "llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp",
+ "llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp",
+ "llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp",
+ "llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp",
+ "llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp",
+ "llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp",
+ "llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp",
+ "llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp",
+ "llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp",
+ "llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.cpp",
+ "llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp",
+ "llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFStreamer.cpp",
+ "llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp",
+ "llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCAsmInfo.cpp",
+ "llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp",
+ "llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp",
+ "llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp",
+ "llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.cpp",
+ "llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchTargetStreamer.cpp",
+ "llvm/lib/Target/LoongArch/TargetInfo/LoongArchTargetInfo.cpp",
+ "llvm/lib/TargetParser/LoongArchTargetParser.cpp",
+ "llvm/lib/Transforms/IPO/BarrierNoopPass.cpp",
+ ]
+}
+
swiftshader_llvm_source_set("swiftshader_llvm_mips") {
sources = [
"llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp",
diff --git a/third_party/llvm-16.0/CMakeLists.txt b/third_party/llvm-16.0/CMakeLists.txt
index 62d0cda..3a0bf52 100644
--- a/third_party/llvm-16.0/CMakeLists.txt
+++ b/third_party/llvm-16.0/CMakeLists.txt
@@ -1394,6 +1394,36 @@
${LLVM_DIR}/lib/Target/ARM/Utils/ARMBaseInfo.cpp
${LLVM_DIR}/lib/Transforms/IPO/BarrierNoopPass.cpp
)
+elseif(ARCH STREQUAL "loongarch64")
+ list(APPEND LLVM_LIST
+ ${LLVM_DIR}/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/LoongArchFrameLowering.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/LoongArchISelLowering.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/LoongArchInstrInfo.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/LoongArchMCInstLower.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/LoongArchSubtarget.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/MCTargetDesc/LoongArchELFStreamer.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/MCTargetDesc/LoongArchMCAsmInfo.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/MCTargetDesc/LoongArchMatInt.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/MCTargetDesc/LoongArchTargetStreamer.cpp
+ ${LLVM_DIR}/lib/Target/LoongArch/TargetInfo/LoongArchTargetInfo.cpp
+ ${LLVM_DIR}/lib/TargetParser/LoongArchTargetParser.cpp
+ ${LLVM_DIR}/lib/Transforms/IPO/BarrierNoopPass.cpp
+ )
elseif(ARCH STREQUAL "ppc64le")
list(APPEND LLVM_LIST
${LLVM_DIR}/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -1529,6 +1559,7 @@
${LLVM_DIR}/include
${LLVM_DIR}/lib/Target/AArch64
${LLVM_DIR}/lib/Target/ARM
+ ${LLVM_DIR}/lib/Target/LoongArch
${LLVM_DIR}/lib/Target/Mips
${LLVM_DIR}/lib/Target/PowerPC
${LLVM_DIR}/lib/Target/RISCV
@@ -1537,6 +1568,7 @@
${LLVM_CONFIG_DIR}/common/lib/IR
${LLVM_CONFIG_DIR}/common/lib/Target/AArch64
${LLVM_CONFIG_DIR}/common/lib/Target/ARM
+ ${LLVM_CONFIG_DIR}/common/lib/Target/LoongArch
${LLVM_CONFIG_DIR}/common/lib/Target/Mips
${LLVM_CONFIG_DIR}/common/lib/Target/PowerPC
${LLVM_CONFIG_DIR}/common/lib/Target/RISCV
diff --git a/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenAsmMatcher.inc b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenAsmMatcher.inc
new file mode 100644
index 0000000..eeed0be
--- /dev/null
+++ b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenAsmMatcher.inc
@@ -0,0 +1,2353 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Assembly Matcher Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_ASSEMBLER_HEADER
+#undef GET_ASSEMBLER_HEADER
+ // This should be included into the middle of the declaration of
+ // your subclasses implementation of MCTargetAsmParser.
+ FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
+ void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
+ const OperandVector &Operands);
+ void convertToMapAndConstraints(unsigned Kind,
+ const OperandVector &Operands) override;
+ unsigned MatchInstructionImpl(const OperandVector &Operands,
+ MCInst &Inst,
+ uint64_t &ErrorInfo,
+ FeatureBitset &MissingFeatures,
+ bool matchingInlineAsm,
+ unsigned VariantID = 0);
+ unsigned MatchInstructionImpl(const OperandVector &Operands,
+ MCInst &Inst,
+ uint64_t &ErrorInfo,
+ bool matchingInlineAsm,
+ unsigned VariantID = 0) {
+ FeatureBitset MissingFeatures;
+ return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
+ matchingInlineAsm, VariantID);
+ }
+
+ OperandMatchResultTy MatchOperandParserImpl(
+ OperandVector &Operands,
+ StringRef Mnemonic,
+ bool ParseForAllFeatures = false);
+ OperandMatchResultTy tryCustomParseOperand(
+ OperandVector &Operands,
+ unsigned MCK);
+
+#endif // GET_ASSEMBLER_HEADER_INFO
+
+
+#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
+#undef GET_OPERAND_DIAGNOSTIC_TYPES
+
+ Match_InvalidBareSymbol,
+ Match_InvalidImm32,
+ Match_InvalidSImm12,
+ Match_InvalidSImm12addlike,
+ Match_InvalidSImm12lu52id,
+ Match_InvalidSImm14lsl2,
+ Match_InvalidSImm16,
+ Match_InvalidSImm16lsl2,
+ Match_InvalidSImm20,
+ Match_InvalidSImm20lu12iw,
+ Match_InvalidSImm20lu32id,
+ Match_InvalidSImm20pcalau12i,
+ Match_InvalidSImm21lsl2,
+ Match_InvalidSImm26Operand,
+ Match_InvalidUImm12,
+ Match_InvalidUImm12ori,
+ Match_InvalidUImm14,
+ Match_InvalidUImm15,
+ Match_InvalidUImm2,
+ Match_InvalidUImm2plus1,
+ Match_InvalidUImm3,
+ Match_InvalidUImm5,
+ Match_InvalidUImm6,
+ Match_InvalidUImm8,
+ END_OPERAND_DIAGNOSTIC_TYPES
+#endif // GET_OPERAND_DIAGNOSTIC_TYPES
+
+
+#ifdef GET_REGISTER_MATCHER
+#undef GET_REGISTER_MATCHER
+
+// Bits for subtarget features that participate in instruction matching.
+enum SubtargetFeatureBits : uint8_t {
+ Feature_IsLA64Bit = 10,
+ Feature_IsLA32Bit = 9,
+ Feature_HasBasicFBit = 1,
+ Feature_HasBasicDBit = 0,
+ Feature_HasExtLSXBit = 4,
+ Feature_HasExtLASXBit = 2,
+ Feature_HasExtLVZBit = 5,
+ Feature_HasExtLBTBit = 3,
+ Feature_HasLaGlobalWithPcrelBit = 7,
+ Feature_HasLaGlobalWithAbsBit = 6,
+ Feature_HasLaLocalWithAbsBit = 8,
+};
+
+static unsigned MatchRegisterName(StringRef Name) {
+ switch (Name.size()) {
+ default: break;
+ case 2: // 30 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'f': // 20 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 1; // "f0"
+ case '1': // 2 strings to match.
+ return 2; // "f1"
+ case '2': // 2 strings to match.
+ return 3; // "f2"
+ case '3': // 2 strings to match.
+ return 4; // "f3"
+ case '4': // 2 strings to match.
+ return 5; // "f4"
+ case '5': // 2 strings to match.
+ return 6; // "f5"
+ case '6': // 2 strings to match.
+ return 7; // "f6"
+ case '7': // 2 strings to match.
+ return 8; // "f7"
+ case '8': // 2 strings to match.
+ return 9; // "f8"
+ case '9': // 2 strings to match.
+ return 10; // "f9"
+ }
+ break;
+ case 'r': // 10 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 45; // "r0"
+ case '1': // 1 string to match.
+ return 46; // "r1"
+ case '2': // 1 string to match.
+ return 47; // "r2"
+ case '3': // 1 string to match.
+ return 48; // "r3"
+ case '4': // 1 string to match.
+ return 49; // "r4"
+ case '5': // 1 string to match.
+ return 50; // "r5"
+ case '6': // 1 string to match.
+ return 51; // "r6"
+ case '7': // 1 string to match.
+ return 52; // "r7"
+ case '8': // 1 string to match.
+ return 53; // "r8"
+ case '9': // 1 string to match.
+ return 54; // "r9"
+ }
+ break;
+ }
+ break;
+ case 3: // 66 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'f': // 44 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '1': // 20 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 11; // "f10"
+ case '1': // 2 strings to match.
+ return 12; // "f11"
+ case '2': // 2 strings to match.
+ return 13; // "f12"
+ case '3': // 2 strings to match.
+ return 14; // "f13"
+ case '4': // 2 strings to match.
+ return 15; // "f14"
+ case '5': // 2 strings to match.
+ return 16; // "f15"
+ case '6': // 2 strings to match.
+ return 17; // "f16"
+ case '7': // 2 strings to match.
+ return 18; // "f17"
+ case '8': // 2 strings to match.
+ return 19; // "f18"
+ case '9': // 2 strings to match.
+ return 20; // "f19"
+ }
+ break;
+ case '2': // 20 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 21; // "f20"
+ case '1': // 2 strings to match.
+ return 22; // "f21"
+ case '2': // 2 strings to match.
+ return 23; // "f22"
+ case '3': // 2 strings to match.
+ return 24; // "f23"
+ case '4': // 2 strings to match.
+ return 25; // "f24"
+ case '5': // 2 strings to match.
+ return 26; // "f25"
+ case '6': // 2 strings to match.
+ return 27; // "f26"
+ case '7': // 2 strings to match.
+ return 28; // "f27"
+ case '8': // 2 strings to match.
+ return 29; // "f28"
+ case '9': // 2 strings to match.
+ return 30; // "f29"
+ }
+ break;
+ case '3': // 4 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 31; // "f30"
+ case '1': // 2 strings to match.
+ return 32; // "f31"
+ }
+ break;
+ }
+ break;
+ case 'r': // 22 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '1': // 10 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 55; // "r10"
+ case '1': // 1 string to match.
+ return 56; // "r11"
+ case '2': // 1 string to match.
+ return 57; // "r12"
+ case '3': // 1 string to match.
+ return 58; // "r13"
+ case '4': // 1 string to match.
+ return 59; // "r14"
+ case '5': // 1 string to match.
+ return 60; // "r15"
+ case '6': // 1 string to match.
+ return 61; // "r16"
+ case '7': // 1 string to match.
+ return 62; // "r17"
+ case '8': // 1 string to match.
+ return 63; // "r18"
+ case '9': // 1 string to match.
+ return 64; // "r19"
+ }
+ break;
+ case '2': // 10 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 65; // "r20"
+ case '1': // 1 string to match.
+ return 66; // "r21"
+ case '2': // 1 string to match.
+ return 67; // "r22"
+ case '3': // 1 string to match.
+ return 68; // "r23"
+ case '4': // 1 string to match.
+ return 69; // "r24"
+ case '5': // 1 string to match.
+ return 70; // "r25"
+ case '6': // 1 string to match.
+ return 71; // "r26"
+ case '7': // 1 string to match.
+ return 72; // "r27"
+ case '8': // 1 string to match.
+ return 73; // "r28"
+ case '9': // 1 string to match.
+ return 74; // "r29"
+ }
+ break;
+ case '3': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 75; // "r30"
+ case '1': // 1 string to match.
+ return 76; // "r31"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ case 4: // 8 strings to match.
+ if (memcmp(Name.data()+0, "fcc", 3) != 0)
+ break;
+ switch (Name[3]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 33; // "fcc0"
+ case '1': // 1 string to match.
+ return 34; // "fcc1"
+ case '2': // 1 string to match.
+ return 35; // "fcc2"
+ case '3': // 1 string to match.
+ return 36; // "fcc3"
+ case '4': // 1 string to match.
+ return 37; // "fcc4"
+ case '5': // 1 string to match.
+ return 38; // "fcc5"
+ case '6': // 1 string to match.
+ return 39; // "fcc6"
+ case '7': // 1 string to match.
+ return 40; // "fcc7"
+ }
+ break;
+ case 5: // 4 strings to match.
+ if (memcmp(Name.data()+0, "fcsr", 4) != 0)
+ break;
+ switch (Name[4]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 41; // "fcsr0"
+ case '1': // 1 string to match.
+ return 42; // "fcsr1"
+ case '2': // 1 string to match.
+ return 43; // "fcsr2"
+ case '3': // 1 string to match.
+ return 44; // "fcsr3"
+ }
+ break;
+ }
+ return 0;
+}
+
+static unsigned MatchRegisterAltName(StringRef Name) {
+ switch (Name.size()) {
+ default: break;
+ case 2: // 31 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'a': // 8 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 49; // "a0"
+ case '1': // 1 string to match.
+ return 50; // "a1"
+ case '2': // 1 string to match.
+ return 51; // "a2"
+ case '3': // 1 string to match.
+ return 52; // "a3"
+ case '4': // 1 string to match.
+ return 53; // "a4"
+ case '5': // 1 string to match.
+ return 54; // "a5"
+ case '6': // 1 string to match.
+ return 55; // "a6"
+ case '7': // 1 string to match.
+ return 56; // "a7"
+ }
+ break;
+ case 'f': // 1 string to match.
+ if (Name[1] != 'p')
+ break;
+ return 67; // "fp"
+ case 'r': // 1 string to match.
+ if (Name[1] != 'a')
+ break;
+ return 46; // "ra"
+ case 's': // 11 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 68; // "s0"
+ case '1': // 1 string to match.
+ return 69; // "s1"
+ case '2': // 1 string to match.
+ return 70; // "s2"
+ case '3': // 1 string to match.
+ return 71; // "s3"
+ case '4': // 1 string to match.
+ return 72; // "s4"
+ case '5': // 1 string to match.
+ return 73; // "s5"
+ case '6': // 1 string to match.
+ return 74; // "s6"
+ case '7': // 1 string to match.
+ return 75; // "s7"
+ case '8': // 1 string to match.
+ return 76; // "s8"
+ case '9': // 1 string to match.
+ return 67; // "s9"
+ case 'p': // 1 string to match.
+ return 48; // "sp"
+ }
+ break;
+ case 't': // 10 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 57; // "t0"
+ case '1': // 1 string to match.
+ return 58; // "t1"
+ case '2': // 1 string to match.
+ return 59; // "t2"
+ case '3': // 1 string to match.
+ return 60; // "t3"
+ case '4': // 1 string to match.
+ return 61; // "t4"
+ case '5': // 1 string to match.
+ return 62; // "t5"
+ case '6': // 1 string to match.
+ return 63; // "t6"
+ case '7': // 1 string to match.
+ return 64; // "t7"
+ case '8': // 1 string to match.
+ return 65; // "t8"
+ case 'p': // 1 string to match.
+ return 47; // "tp"
+ }
+ break;
+ }
+ break;
+ case 3: // 52 strings to match.
+ if (Name[0] != 'f')
+ break;
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 16 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 1; // "fa0"
+ case '1': // 2 strings to match.
+ return 2; // "fa1"
+ case '2': // 2 strings to match.
+ return 3; // "fa2"
+ case '3': // 2 strings to match.
+ return 4; // "fa3"
+ case '4': // 2 strings to match.
+ return 5; // "fa4"
+ case '5': // 2 strings to match.
+ return 6; // "fa5"
+ case '6': // 2 strings to match.
+ return 7; // "fa6"
+ case '7': // 2 strings to match.
+ return 8; // "fa7"
+ }
+ break;
+ case 's': // 16 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 25; // "fs0"
+ case '1': // 2 strings to match.
+ return 26; // "fs1"
+ case '2': // 2 strings to match.
+ return 27; // "fs2"
+ case '3': // 2 strings to match.
+ return 28; // "fs3"
+ case '4': // 2 strings to match.
+ return 29; // "fs4"
+ case '5': // 2 strings to match.
+ return 30; // "fs5"
+ case '6': // 2 strings to match.
+ return 31; // "fs6"
+ case '7': // 2 strings to match.
+ return 32; // "fs7"
+ }
+ break;
+ case 't': // 20 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 9; // "ft0"
+ case '1': // 2 strings to match.
+ return 10; // "ft1"
+ case '2': // 2 strings to match.
+ return 11; // "ft2"
+ case '3': // 2 strings to match.
+ return 12; // "ft3"
+ case '4': // 2 strings to match.
+ return 13; // "ft4"
+ case '5': // 2 strings to match.
+ return 14; // "ft5"
+ case '6': // 2 strings to match.
+ return 15; // "ft6"
+ case '7': // 2 strings to match.
+ return 16; // "ft7"
+ case '8': // 2 strings to match.
+ return 17; // "ft8"
+ case '9': // 2 strings to match.
+ return 18; // "ft9"
+ }
+ break;
+ }
+ break;
+ case 4: // 13 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'f': // 12 strings to match.
+ if (memcmp(Name.data()+1, "t1", 2) != 0)
+ break;
+ switch (Name[3]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 19; // "ft10"
+ case '1': // 2 strings to match.
+ return 20; // "ft11"
+ case '2': // 2 strings to match.
+ return 21; // "ft12"
+ case '3': // 2 strings to match.
+ return 22; // "ft13"
+ case '4': // 2 strings to match.
+ return 23; // "ft14"
+ case '5': // 2 strings to match.
+ return 24; // "ft15"
+ }
+ break;
+ case 'z': // 1 string to match.
+ if (memcmp(Name.data()+1, "ero", 3) != 0)
+ break;
+ return 45; // "zero"
+ }
+ break;
+ }
+ return 0;
+}
+
+#endif // GET_REGISTER_MATCHER
+
+
+#ifdef GET_SUBTARGET_FEATURE_NAME
+#undef GET_SUBTARGET_FEATURE_NAME
+
+// User-level names for subtarget features that participate in
+// instruction matching.
+static const char *getSubtargetFeatureName(uint64_t Val) {
+ switch(Val) {
+ case Feature_IsLA64Bit: return "LA64 Basic Integer and Privilege Instruction Set";
+ case Feature_IsLA32Bit: return "LA32 Basic Integer and Privilege Instruction Set";
+ case Feature_HasBasicFBit: return "'F' (Single-Precision Floating-Point)";
+ case Feature_HasBasicDBit: return "'D' (Double-Precision Floating-Point)";
+ case Feature_HasExtLSXBit: return "'LSX' (Loongson SIMD Extension)";
+ case Feature_HasExtLASXBit: return "'LASX' (Loongson Advanced SIMD Extension)";
+ case Feature_HasExtLVZBit: return "'LVZ' (Loongson Virtualization Extension)";
+ case Feature_HasExtLBTBit: return "'LBT' (Loongson Binary Translation Extension)";
+ case Feature_HasLaGlobalWithPcrelBit: return "Expand la.global as la.pcrel";
+ case Feature_HasLaGlobalWithAbsBit: return "Expand la.global as la.abs";
+ case Feature_HasLaLocalWithAbsBit: return "Expand la.local as la.abs";
+ default: return "(unknown)";
+ }
+}
+
+#endif // GET_SUBTARGET_FEATURE_NAME
+
+
+#ifdef GET_MATCHER_IMPLEMENTATION
+#undef GET_MATCHER_IMPLEMENTATION
+
+enum {
+ Tie0_1_1,
+};
+
+static const uint8_t TiedAsmOperandTable[][3] = {
+ /* Tie0_1_1 */ { 0, 1, 1 },
+};
+
+namespace {
+enum OperatorConversionKind {
+ CVT_Done,
+ CVT_Reg,
+ CVT_Tied,
+ CVT_95_Reg,
+ CVT_95_addImmOperands,
+ CVT_95_addRegOperands,
+ CVT_regR0,
+ CVT_imm_95_0,
+ CVT_regR1,
+ CVT_NUM_CONVERTERS
+};
+
+enum InstructionConversionKind {
+ Convert__Reg1_0__Reg1_1__Reg1_2,
+ Convert__Reg1_0__Reg1_1__SImm12addlike1_2,
+ Convert__Reg1_0__Reg1_1__SImm161_2,
+ Convert__Reg1_0__Reg1_1__Reg1_2__UImm2plus11_3,
+ Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2,
+ Convert__Reg1_0__Reg1_1__UImm121_2,
+ Convert__Reg1_0__Reg1_1,
+ Convert__SImm26OperandB1_0,
+ Convert__Reg1_0__SImm21lsl21_1,
+ Convert__Reg1_0__Reg1_1__SImm16lsl21_2,
+ Convert__Reg1_0__regR0__SImm16lsl21_1,
+ Convert__Reg1_1__Reg1_0__SImm16lsl21_2,
+ Convert__regR0__Reg1_0__SImm16lsl21_1,
+ Convert__SImm26OperandBL1_0,
+ Convert__UImm151_0,
+ Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2__UImm61_3,
+ Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3,
+ Convert__Reg1_0__Reg1_1__UImm61_2__UImm61_3,
+ Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3,
+ Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3,
+ Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3,
+ Convert__UImm51_0__Reg1_1__SImm121_2,
+ Convert__Reg1_0__UImm141_1,
+ Convert__Reg1_0__Tie0_1_1__UImm141_1,
+ Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm141_2,
+ Convert_NoOperands,
+ Convert__Reg1_0__Reg1_1__SImm121_2,
+ Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3,
+ Convert__Reg1_2__Reg1_1__UImm51_0,
+ Convert__regR0__Reg1_0__imm_95_0,
+ Convert__Reg1_0__BareSymbol1_1,
+ Convert__Reg1_0__imm_95_0__BareSymbol1_1,
+ Convert__Reg1_0__Reg1_1__BareSymbol1_2,
+ Convert__Reg1_0__Reg1_1__UImm81_2,
+ Convert__Reg1_0__UImm81_1,
+ Convert__Reg1_0__Reg1_1__SImm14lsl21_2,
+ Convert__Reg1_0__Imm1_1,
+ Convert__Reg1_0__Imm321_1,
+ Convert__Reg1_0__SImm20lu12iw1_1,
+ Convert__Reg1_0__Tie0_1_1__SImm20lu32id1_1,
+ Convert__Reg1_0__Reg1_1__SImm12lu52id1_2,
+ Convert__Reg1_0__Reg1_1__regR0,
+ Convert__Reg1_0__Tie0_1_1__Reg1_1,
+ Convert__regR0__regR0__imm_95_0,
+ Convert__Reg1_0__Reg1_1__UImm12ori1_2,
+ Convert__Reg1_0__SImm201_1,
+ Convert__Reg1_0__SImm20pcalau12i1_1,
+ Convert__UImm51_0__Reg1_1__Reg1_2,
+ Convert__regR0__regR1__imm_95_0,
+ Convert__Reg1_0__Reg1_1__UImm61_2,
+ Convert__Reg1_0__Reg1_1__UImm51_2,
+ Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm14lsl21_2,
+ CVT_NUM_SIGNATURES
+};
+
+} // end anonymous namespace
+
+static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
+ // Convert__Reg1_0__Reg1_1__Reg1_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__SImm12addlike1_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__SImm161_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__Reg1_2__UImm2plus11_3
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__UImm121_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
+ // Convert__SImm26OperandB1_0
+ { CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__Reg1_0__SImm21lsl21_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__SImm16lsl21_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__regR0__SImm16lsl21_1
+ { CVT_95_Reg, 1, CVT_regR0, 0, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_1__Reg1_0__SImm16lsl21_2
+ { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__regR0__Reg1_0__SImm16lsl21_1
+ { CVT_regR0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__SImm26OperandBL1_0
+ { CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__UImm151_0
+ { CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2__UImm61_3
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__UImm61_2__UImm61_3
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
+ // Convert__UImm51_0__Reg1_1__SImm121_2
+ { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__UImm141_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__UImm141_1
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm141_2
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert_NoOperands
+ { CVT_Done },
+ // Convert__Reg1_0__Reg1_1__SImm121_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
+ // Convert__Reg1_2__Reg1_1__UImm51_0
+ { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__regR0__Reg1_0__imm_95_0
+ { CVT_regR0, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__Reg1_0__BareSymbol1_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__imm_95_0__BareSymbol1_1
+ { CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__BareSymbol1_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__UImm81_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__UImm81_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__SImm14lsl21_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Imm1_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Imm321_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__SImm20lu12iw1_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__SImm20lu32id1_1
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__SImm12lu52id1_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__regR0
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regR0, 0, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__Reg1_1
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
+ // Convert__regR0__regR0__imm_95_0
+ { CVT_regR0, 0, CVT_regR0, 0, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__UImm12ori1_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__SImm201_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__SImm20pcalau12i1_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__UImm51_0__Reg1_1__Reg1_2
+ { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
+ // Convert__regR0__regR1__imm_95_0
+ { CVT_regR0, 0, CVT_regR1, 0, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__UImm61_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__UImm51_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm14lsl21_2
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+};
+
+void LoongArchAsmParser::
+convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
+ const OperandVector &Operands) {
+ assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
+ const uint8_t *Converter = ConversionTable[Kind];
+ unsigned OpIdx;
+ Inst.setOpcode(Opcode);
+ for (const uint8_t *p = Converter; *p; p += 2) {
+ OpIdx = *(p + 1);
+ switch (*p) {
+ default: llvm_unreachable("invalid conversion entry!");
+ case CVT_Reg:
+ static_cast<LoongArchOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
+ break;
+ case CVT_Tied: {
+ assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
+ std::begin(TiedAsmOperandTable)) &&
+ "Tied operand not found");
+ unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
+ if (TiedResOpnd != (uint8_t)-1)
+ Inst.addOperand(Inst.getOperand(TiedResOpnd));
+ break;
+ }
+ case CVT_95_Reg:
+ static_cast<LoongArchOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
+ break;
+ case CVT_95_addImmOperands:
+ static_cast<LoongArchOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
+ break;
+ case CVT_95_addRegOperands:
+ static_cast<LoongArchOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
+ break;
+ case CVT_regR0:
+ Inst.addOperand(MCOperand::createReg(LoongArch::R0));
+ break;
+ case CVT_imm_95_0:
+ Inst.addOperand(MCOperand::createImm(0));
+ break;
+ case CVT_regR1:
+ Inst.addOperand(MCOperand::createReg(LoongArch::R1));
+ break;
+ }
+ }
+}
+
+void LoongArchAsmParser::
+convertToMapAndConstraints(unsigned Kind,
+ const OperandVector &Operands) {
+ assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
+ unsigned NumMCOperands = 0;
+ const uint8_t *Converter = ConversionTable[Kind];
+ for (const uint8_t *p = Converter; *p; p += 2) {
+ switch (*p) {
+ default: llvm_unreachable("invalid conversion entry!");
+ case CVT_Reg:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("r");
+ ++NumMCOperands;
+ break;
+ case CVT_Tied:
+ ++NumMCOperands;
+ break;
+ case CVT_95_Reg:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("r");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addImmOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_regR0:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_0:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_regR1:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ ++NumMCOperands;
+ break;
+ }
+ }
+}
+
+namespace {
+
+/// MatchClassKind - The kinds of classes which participate in
+/// instruction matching.
+enum MatchClassKind {
+ InvalidMatchClass = 0,
+ OptionalMatchClass = 1,
+ MCK_LAST_TOKEN = OptionalMatchClass,
+ MCK_FCSR, // register class 'FCSR'
+ MCK_CFR, // register class 'CFR'
+ MCK_GPRT, // register class 'GPRT'
+ MCK_FPR32, // register class 'FPR32'
+ MCK_FPR64, // register class 'FPR64'
+ MCK_GPR, // register class 'GPR'
+ MCK_LAST_REGISTER = MCK_GPR,
+ MCK_AtomicMemAsmOperand, // user defined class 'AtomicMemAsmOperand'
+ MCK_BareSymbol, // user defined class 'BareSymbol'
+ MCK_Imm, // user defined class 'ImmAsmOperand'
+ MCK_SImm26OperandB, // user defined class 'SImm26OperandB'
+ MCK_SImm26OperandBL, // user defined class 'SImm26OperandBL'
+ MCK_Imm32, // user defined class 'anonymous_3918'
+ MCK_UImm2, // user defined class 'anonymous_3919'
+ MCK_UImm2plus1, // user defined class 'anonymous_3920'
+ MCK_UImm3, // user defined class 'anonymous_3921'
+ MCK_UImm5, // user defined class 'anonymous_3922'
+ MCK_UImm6, // user defined class 'anonymous_3923'
+ MCK_UImm8, // user defined class 'anonymous_3924'
+ MCK_UImm12, // user defined class 'anonymous_3925'
+ MCK_UImm12ori, // user defined class 'anonymous_3926'
+ MCK_UImm14, // user defined class 'anonymous_3927'
+ MCK_UImm15, // user defined class 'anonymous_3928'
+ MCK_SImm12, // user defined class 'anonymous_3929'
+ MCK_SImm12addlike, // user defined class 'anonymous_3930'
+ MCK_SImm12lu52id, // user defined class 'anonymous_3931'
+ MCK_SImm14lsl2, // user defined class 'anonymous_3932'
+ MCK_SImm16, // user defined class 'anonymous_3933'
+ MCK_SImm16lsl2, // user defined class 'anonymous_3934'
+ MCK_SImm20, // user defined class 'anonymous_3935'
+ MCK_SImm20pcalau12i, // user defined class 'anonymous_3936'
+ MCK_SImm20lu12iw, // user defined class 'anonymous_3937'
+ MCK_SImm20lu32id, // user defined class 'anonymous_3938'
+ MCK_SImm21lsl2, // user defined class 'anonymous_3939'
+ NumMatchClassKinds
+};
+
+} // end anonymous namespace
+
+static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
+ return MCTargetAsmParser::Match_InvalidOperand;
+}
+
+static MatchClassKind matchTokenString(StringRef Name) {
+ return InvalidMatchClass;
+}
+
+/// isSubclass - Compute whether \p A is a subclass of \p B.
+static bool isSubclass(MatchClassKind A, MatchClassKind B) {
+ if (A == B)
+ return true;
+
+ switch (A) {
+ default:
+ return false;
+
+ case MCK_GPRT:
+ return B == MCK_GPR;
+ }
+}
+
+static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
+ LoongArchOperand &Operand = (LoongArchOperand &)GOp;
+ if (Kind == InvalidMatchClass)
+ return MCTargetAsmParser::Match_InvalidOperand;
+
+ if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
+ return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
+ MCTargetAsmParser::Match_Success :
+ MCTargetAsmParser::Match_InvalidOperand;
+
+ switch (Kind) {
+ default: break;
+ // 'AtomicMemAsmOperand' class
+ case MCK_AtomicMemAsmOperand: {
+ DiagnosticPredicate DP(Operand.isGPR());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'BareSymbol' class
+ case MCK_BareSymbol: {
+ DiagnosticPredicate DP(Operand.isBareSymbol());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidBareSymbol;
+ break;
+ }
+ // 'Imm' class
+ case MCK_Imm: {
+ DiagnosticPredicate DP(Operand.isImm());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'SImm26OperandB' class
+ case MCK_SImm26OperandB: {
+ DiagnosticPredicate DP(Operand.isSImm26Operand());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidSImm26Operand;
+ break;
+ }
+ // 'SImm26OperandBL' class
+ case MCK_SImm26OperandBL: {
+ DiagnosticPredicate DP(Operand.isSImm26Operand());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidSImm26Operand;
+ break;
+ }
+ // 'Imm32' class
+ case MCK_Imm32: {
+ DiagnosticPredicate DP(Operand.isImm32());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidImm32;
+ break;
+ }
+ // 'UImm2' class
+ case MCK_UImm2: {
+ DiagnosticPredicate DP(Operand.isUImm2());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidUImm2;
+ break;
+ }
+ // 'UImm2plus1' class
+ case MCK_UImm2plus1: {
+ DiagnosticPredicate DP(Operand.isUImm2plus1());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidUImm2plus1;
+ break;
+ }
+ // 'UImm3' class
+ case MCK_UImm3: {
+ DiagnosticPredicate DP(Operand.isUImm3());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidUImm3;
+ break;
+ }
+ // 'UImm5' class
+ case MCK_UImm5: {
+ DiagnosticPredicate DP(Operand.isUImm5());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidUImm5;
+ break;
+ }
+ // 'UImm6' class
+ case MCK_UImm6: {
+ DiagnosticPredicate DP(Operand.isUImm6());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidUImm6;
+ break;
+ }
+ // 'UImm8' class
+ case MCK_UImm8: {
+ DiagnosticPredicate DP(Operand.isUImm8());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidUImm8;
+ break;
+ }
+ // 'UImm12' class
+ case MCK_UImm12: {
+ DiagnosticPredicate DP(Operand.isUImm12());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidUImm12;
+ break;
+ }
+ // 'UImm12ori' class
+ case MCK_UImm12ori: {
+ DiagnosticPredicate DP(Operand.isUImm12ori());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidUImm12ori;
+ break;
+ }
+ // 'UImm14' class
+ case MCK_UImm14: {
+ DiagnosticPredicate DP(Operand.isUImm14());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidUImm14;
+ break;
+ }
+ // 'UImm15' class
+ case MCK_UImm15: {
+ DiagnosticPredicate DP(Operand.isUImm15());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidUImm15;
+ break;
+ }
+ // 'SImm12' class
+ case MCK_SImm12: {
+ DiagnosticPredicate DP(Operand.isSImm12());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidSImm12;
+ break;
+ }
+ // 'SImm12addlike' class
+ case MCK_SImm12addlike: {
+ DiagnosticPredicate DP(Operand.isSImm12addlike());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidSImm12addlike;
+ break;
+ }
+ // 'SImm12lu52id' class
+ case MCK_SImm12lu52id: {
+ DiagnosticPredicate DP(Operand.isSImm12lu52id());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidSImm12lu52id;
+ break;
+ }
+ // 'SImm14lsl2' class
+ case MCK_SImm14lsl2: {
+ DiagnosticPredicate DP(Operand.isSImm14lsl2());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidSImm14lsl2;
+ break;
+ }
+ // 'SImm16' class
+ case MCK_SImm16: {
+ DiagnosticPredicate DP(Operand.isSImm16());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidSImm16;
+ break;
+ }
+ // 'SImm16lsl2' class
+ case MCK_SImm16lsl2: {
+ DiagnosticPredicate DP(Operand.isSImm16lsl2());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidSImm16lsl2;
+ break;
+ }
+ // 'SImm20' class
+ case MCK_SImm20: {
+ DiagnosticPredicate DP(Operand.isSImm20());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidSImm20;
+ break;
+ }
+ // 'SImm20pcalau12i' class
+ case MCK_SImm20pcalau12i: {
+ DiagnosticPredicate DP(Operand.isSImm20pcalau12i());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidSImm20pcalau12i;
+ break;
+ }
+ // 'SImm20lu12iw' class
+ case MCK_SImm20lu12iw: {
+ DiagnosticPredicate DP(Operand.isSImm20lu12iw());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidSImm20lu12iw;
+ break;
+ }
+ // 'SImm20lu32id' class
+ case MCK_SImm20lu32id: {
+ DiagnosticPredicate DP(Operand.isSImm20lu32id());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidSImm20lu32id;
+ break;
+ }
+ // 'SImm21lsl2' class
+ case MCK_SImm21lsl2: {
+ DiagnosticPredicate DP(Operand.isSImm21lsl2());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return LoongArchAsmParser::Match_InvalidSImm21lsl2;
+ break;
+ }
+ } // end switch (Kind)
+
+ if (Operand.isReg()) {
+ MatchClassKind OpKind;
+ switch (Operand.getReg()) {
+ default: OpKind = InvalidMatchClass; break;
+ case LoongArch::R0: OpKind = MCK_GPR; break;
+ case LoongArch::R1: OpKind = MCK_GPR; break;
+ case LoongArch::R2: OpKind = MCK_GPR; break;
+ case LoongArch::R3: OpKind = MCK_GPR; break;
+ case LoongArch::R4: OpKind = MCK_GPRT; break;
+ case LoongArch::R5: OpKind = MCK_GPRT; break;
+ case LoongArch::R6: OpKind = MCK_GPRT; break;
+ case LoongArch::R7: OpKind = MCK_GPRT; break;
+ case LoongArch::R8: OpKind = MCK_GPRT; break;
+ case LoongArch::R9: OpKind = MCK_GPRT; break;
+ case LoongArch::R10: OpKind = MCK_GPRT; break;
+ case LoongArch::R11: OpKind = MCK_GPRT; break;
+ case LoongArch::R12: OpKind = MCK_GPRT; break;
+ case LoongArch::R13: OpKind = MCK_GPRT; break;
+ case LoongArch::R14: OpKind = MCK_GPRT; break;
+ case LoongArch::R15: OpKind = MCK_GPRT; break;
+ case LoongArch::R16: OpKind = MCK_GPRT; break;
+ case LoongArch::R17: OpKind = MCK_GPRT; break;
+ case LoongArch::R18: OpKind = MCK_GPRT; break;
+ case LoongArch::R19: OpKind = MCK_GPRT; break;
+ case LoongArch::R20: OpKind = MCK_GPRT; break;
+ case LoongArch::R21: OpKind = MCK_GPR; break;
+ case LoongArch::R22: OpKind = MCK_GPR; break;
+ case LoongArch::R23: OpKind = MCK_GPR; break;
+ case LoongArch::R24: OpKind = MCK_GPR; break;
+ case LoongArch::R25: OpKind = MCK_GPR; break;
+ case LoongArch::R26: OpKind = MCK_GPR; break;
+ case LoongArch::R27: OpKind = MCK_GPR; break;
+ case LoongArch::R28: OpKind = MCK_GPR; break;
+ case LoongArch::R29: OpKind = MCK_GPR; break;
+ case LoongArch::R30: OpKind = MCK_GPR; break;
+ case LoongArch::R31: OpKind = MCK_GPR; break;
+ case LoongArch::F0: OpKind = MCK_FPR32; break;
+ case LoongArch::F1: OpKind = MCK_FPR32; break;
+ case LoongArch::F2: OpKind = MCK_FPR32; break;
+ case LoongArch::F3: OpKind = MCK_FPR32; break;
+ case LoongArch::F4: OpKind = MCK_FPR32; break;
+ case LoongArch::F5: OpKind = MCK_FPR32; break;
+ case LoongArch::F6: OpKind = MCK_FPR32; break;
+ case LoongArch::F7: OpKind = MCK_FPR32; break;
+ case LoongArch::F8: OpKind = MCK_FPR32; break;
+ case LoongArch::F9: OpKind = MCK_FPR32; break;
+ case LoongArch::F10: OpKind = MCK_FPR32; break;
+ case LoongArch::F11: OpKind = MCK_FPR32; break;
+ case LoongArch::F12: OpKind = MCK_FPR32; break;
+ case LoongArch::F13: OpKind = MCK_FPR32; break;
+ case LoongArch::F14: OpKind = MCK_FPR32; break;
+ case LoongArch::F15: OpKind = MCK_FPR32; break;
+ case LoongArch::F16: OpKind = MCK_FPR32; break;
+ case LoongArch::F17: OpKind = MCK_FPR32; break;
+ case LoongArch::F18: OpKind = MCK_FPR32; break;
+ case LoongArch::F19: OpKind = MCK_FPR32; break;
+ case LoongArch::F20: OpKind = MCK_FPR32; break;
+ case LoongArch::F21: OpKind = MCK_FPR32; break;
+ case LoongArch::F22: OpKind = MCK_FPR32; break;
+ case LoongArch::F23: OpKind = MCK_FPR32; break;
+ case LoongArch::F24: OpKind = MCK_FPR32; break;
+ case LoongArch::F25: OpKind = MCK_FPR32; break;
+ case LoongArch::F26: OpKind = MCK_FPR32; break;
+ case LoongArch::F27: OpKind = MCK_FPR32; break;
+ case LoongArch::F28: OpKind = MCK_FPR32; break;
+ case LoongArch::F29: OpKind = MCK_FPR32; break;
+ case LoongArch::F30: OpKind = MCK_FPR32; break;
+ case LoongArch::F31: OpKind = MCK_FPR32; break;
+ case LoongArch::F0_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F1_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F2_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F3_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F4_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F5_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F6_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F7_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F8_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F9_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F10_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F11_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F12_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F13_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F14_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F15_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F16_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F17_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F18_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F19_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F20_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F21_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F22_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F23_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F24_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F25_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F26_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F27_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F28_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F29_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F30_64: OpKind = MCK_FPR64; break;
+ case LoongArch::F31_64: OpKind = MCK_FPR64; break;
+ case LoongArch::FCC0: OpKind = MCK_CFR; break;
+ case LoongArch::FCC1: OpKind = MCK_CFR; break;
+ case LoongArch::FCC2: OpKind = MCK_CFR; break;
+ case LoongArch::FCC3: OpKind = MCK_CFR; break;
+ case LoongArch::FCC4: OpKind = MCK_CFR; break;
+ case LoongArch::FCC5: OpKind = MCK_CFR; break;
+ case LoongArch::FCC6: OpKind = MCK_CFR; break;
+ case LoongArch::FCC7: OpKind = MCK_CFR; break;
+ case LoongArch::FCSR0: OpKind = MCK_FCSR; break;
+ case LoongArch::FCSR1: OpKind = MCK_FCSR; break;
+ case LoongArch::FCSR2: OpKind = MCK_FCSR; break;
+ case LoongArch::FCSR3: OpKind = MCK_FCSR; break;
+ }
+ return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
+ getDiagKindFromRegisterClass(Kind);
+ }
+
+ if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
+ return getDiagKindFromRegisterClass(Kind);
+
+ return MCTargetAsmParser::Match_InvalidOperand;
+}
+
+#ifndef NDEBUG
+const char *getMatchClassName(MatchClassKind Kind) {
+ switch (Kind) {
+ case InvalidMatchClass: return "InvalidMatchClass";
+ case OptionalMatchClass: return "OptionalMatchClass";
+ case MCK_FCSR: return "MCK_FCSR";
+ case MCK_CFR: return "MCK_CFR";
+ case MCK_GPRT: return "MCK_GPRT";
+ case MCK_FPR32: return "MCK_FPR32";
+ case MCK_FPR64: return "MCK_FPR64";
+ case MCK_GPR: return "MCK_GPR";
+ case MCK_AtomicMemAsmOperand: return "MCK_AtomicMemAsmOperand";
+ case MCK_BareSymbol: return "MCK_BareSymbol";
+ case MCK_Imm: return "MCK_Imm";
+ case MCK_SImm26OperandB: return "MCK_SImm26OperandB";
+ case MCK_SImm26OperandBL: return "MCK_SImm26OperandBL";
+ case MCK_Imm32: return "MCK_Imm32";
+ case MCK_UImm2: return "MCK_UImm2";
+ case MCK_UImm2plus1: return "MCK_UImm2plus1";
+ case MCK_UImm3: return "MCK_UImm3";
+ case MCK_UImm5: return "MCK_UImm5";
+ case MCK_UImm6: return "MCK_UImm6";
+ case MCK_UImm8: return "MCK_UImm8";
+ case MCK_UImm12: return "MCK_UImm12";
+ case MCK_UImm12ori: return "MCK_UImm12ori";
+ case MCK_UImm14: return "MCK_UImm14";
+ case MCK_UImm15: return "MCK_UImm15";
+ case MCK_SImm12: return "MCK_SImm12";
+ case MCK_SImm12addlike: return "MCK_SImm12addlike";
+ case MCK_SImm12lu52id: return "MCK_SImm12lu52id";
+ case MCK_SImm14lsl2: return "MCK_SImm14lsl2";
+ case MCK_SImm16: return "MCK_SImm16";
+ case MCK_SImm16lsl2: return "MCK_SImm16lsl2";
+ case MCK_SImm20: return "MCK_SImm20";
+ case MCK_SImm20pcalau12i: return "MCK_SImm20pcalau12i";
+ case MCK_SImm20lu12iw: return "MCK_SImm20lu12iw";
+ case MCK_SImm20lu32id: return "MCK_SImm20lu32id";
+ case MCK_SImm21lsl2: return "MCK_SImm21lsl2";
+ case NumMatchClassKinds: return "NumMatchClassKinds";
+ }
+ llvm_unreachable("unhandled MatchClassKind!");
+}
+
+#endif // NDEBUG
+FeatureBitset LoongArchAsmParser::
+ComputeAvailableFeatures(const FeatureBitset &FB) const {
+ FeatureBitset Features;
+ if (FB[LoongArch::Feature64Bit])
+ Features.set(Feature_IsLA64Bit);
+ if (!FB[LoongArch::Feature64Bit])
+ Features.set(Feature_IsLA32Bit);
+ if (FB[LoongArch::FeatureBasicF])
+ Features.set(Feature_HasBasicFBit);
+ if (FB[LoongArch::FeatureBasicD])
+ Features.set(Feature_HasBasicDBit);
+ if (FB[LoongArch::FeatureExtLSX])
+ Features.set(Feature_HasExtLSXBit);
+ if (FB[LoongArch::FeatureExtLASX])
+ Features.set(Feature_HasExtLASXBit);
+ if (FB[LoongArch::FeatureExtLVZ])
+ Features.set(Feature_HasExtLVZBit);
+ if (FB[LoongArch::FeatureExtLBT])
+ Features.set(Feature_HasExtLBTBit);
+ if (FB[LoongArch::LaGlobalWithPcrel])
+ Features.set(Feature_HasLaGlobalWithPcrelBit);
+ if (FB[LoongArch::LaGlobalWithAbs])
+ Features.set(Feature_HasLaGlobalWithAbsBit);
+ if (FB[LoongArch::LaLocalWithAbs])
+ Features.set(Feature_HasLaLocalWithAbsBit);
+ return Features;
+}
+
+static bool checkAsmTiedOperandConstraints(const LoongArchAsmParser&AsmParser,
+ unsigned Kind,
+ const OperandVector &Operands,
+ uint64_t &ErrorInfo) {
+ assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
+ const uint8_t *Converter = ConversionTable[Kind];
+ for (const uint8_t *p = Converter; *p; p += 2) {
+ switch (*p) {
+ case CVT_Tied: {
+ unsigned OpIdx = *(p + 1);
+ assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
+ std::begin(TiedAsmOperandTable)) &&
+ "Tied operand not found");
+ unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
+ unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
+ if (OpndNum1 != OpndNum2) {
+ auto &SrcOp1 = Operands[OpndNum1];
+ auto &SrcOp2 = Operands[OpndNum2];
+ if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
+ ErrorInfo = OpndNum2;
+ return false;
+ }
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ return true;
+}
+
+static const char MnemonicTable[] =
+ "\005add.d\005add.w\006addi.d\006addi.w\taddu16i.d\006alsl.d\006alsl.w\007"
+ "alsl.wu\007amadd.d\007amadd.w\namadd_db.d\namadd_db.w\007amand.d\007ama"
+ "nd.w\namand_db.d\namand_db.w\007ammax.d\010ammax.du\007ammax.w\010ammax"
+ ".wu\nammax_db.d\013ammax_db.du\nammax_db.w\013ammax_db.wu\007ammin.d\010"
+ "ammin.du\007ammin.w\010ammin.wu\nammin_db.d\013ammin_db.du\nammin_db.w\013"
+ "ammin_db.wu\006amor.d\006amor.w\tamor_db.d\tamor_db.w\010amswap.d\010am"
+ "swap.w\013amswap_db.d\013amswap_db.w\007amxor.d\007amxor.w\namxor_db.d\n"
+ "amxor_db.w\003and\004andi\004andn\010asrtgt.d\010asrtle.d\001b\005bceqz"
+ "\005bcnez\003beq\004beqz\003bge\004bgeu\004bgez\003bgt\004bgtu\004bgtz\t"
+ "bitrev.4b\tbitrev.8b\010bitrev.d\010bitrev.w\002bl\003ble\004bleu\004bl"
+ "ez\003blt\004bltu\004bltz\003bne\004bnez\005break\tbstrins.d\tbstrins.w"
+ "\nbstrpick.d\nbstrpick.w\nbytepick.d\nbytepick.w\005cacop\005clo.d\005c"
+ "lo.w\005clz.d\005clz.w\006cpucfg\tcrc.w.b.w\tcrc.w.d.w\tcrc.w.h.w\tcrc."
+ "w.w.w\ncrcc.w.b.w\ncrcc.w.d.w\ncrcc.w.h.w\ncrcc.w.w.w\005csrrd\005csrwr"
+ "\007csrxchg\005cto.d\005cto.w\005ctz.d\005ctz.w\004dbar\004dbcl\005div."
+ "d\006div.du\005div.w\006div.wu\004ertn\007ext.w.b\007ext.w.h\006fabs.d\006"
+ "fabs.s\006fadd.d\006fadd.s\010fclass.d\010fclass.s\nfcmp.caf.d\nfcmp.ca"
+ "f.s\nfcmp.ceq.d\nfcmp.ceq.s\nfcmp.cle.d\nfcmp.cle.s\nfcmp.clt.d\nfcmp.c"
+ "lt.s\nfcmp.cne.d\nfcmp.cne.s\nfcmp.cor.d\nfcmp.cor.s\013fcmp.cueq.d\013"
+ "fcmp.cueq.s\013fcmp.cule.d\013fcmp.cule.s\013fcmp.cult.d\013fcmp.cult.s"
+ "\nfcmp.cun.d\nfcmp.cun.s\013fcmp.cune.d\013fcmp.cune.s\nfcmp.saf.d\nfcm"
+ "p.saf.s\nfcmp.seq.d\nfcmp.seq.s\nfcmp.sle.d\nfcmp.sle.s\nfcmp.slt.d\nfc"
+ "mp.slt.s\nfcmp.sne.d\nfcmp.sne.s\nfcmp.sor.d\nfcmp.sor.s\013fcmp.sueq.d"
+ "\013fcmp.sueq.s\013fcmp.sule.d\013fcmp.sule.s\013fcmp.sult.d\013fcmp.su"
+ "lt.s\nfcmp.sun.d\nfcmp.sun.s\013fcmp.sune.d\013fcmp.sune.s\013fcopysign"
+ ".d\013fcopysign.s\010fcvt.d.s\010fcvt.s.d\006fdiv.d\006fdiv.s\tffint.d."
+ "l\tffint.d.w\tffint.s.l\tffint.s.w\005fld.d\005fld.s\007fldgt.d\007fldg"
+ "t.s\007fldle.d\007fldle.s\006fldx.d\006fldx.s\007flogb.d\007flogb.s\007"
+ "fmadd.d\007fmadd.s\006fmax.d\006fmax.s\007fmaxa.d\007fmaxa.s\006fmin.d\006"
+ "fmin.s\007fmina.d\007fmina.s\006fmov.d\006fmov.s\007fmsub.d\007fmsub.s\006"
+ "fmul.d\006fmul.s\006fneg.d\006fneg.s\010fnmadd.d\010fnmadd.s\010fnmsub."
+ "d\010fnmsub.s\010frecip.d\010frecip.s\007frint.d\007frint.s\010frsqrt.d"
+ "\010frsqrt.s\tfscaleb.d\tfscaleb.s\004fsel\007fsqrt.d\007fsqrt.s\005fst"
+ ".d\005fst.s\007fstgt.d\007fstgt.s\007fstle.d\007fstle.s\006fstx.d\006fs"
+ "tx.s\006fsub.d\006fsub.s\tftint.l.d\tftint.l.s\tftint.w.d\tftint.w.s\013"
+ "ftintrm.l.d\013ftintrm.l.s\013ftintrm.w.d\013ftintrm.w.s\014ftintrne.l."
+ "d\014ftintrne.l.s\014ftintrne.w.d\014ftintrne.w.s\013ftintrp.l.d\013fti"
+ "ntrp.l.s\013ftintrp.w.d\013ftintrp.w.s\013ftintrz.l.d\013ftintrz.l.s\013"
+ "ftintrz.w.d\013ftintrz.w.s\004ibar\004idle\006invtlb\tiocsrrd.b\tiocsrr"
+ "d.d\tiocsrrd.h\tiocsrrd.w\tiocsrwr.b\tiocsrwr.d\tiocsrwr.h\tiocsrwr.w\004"
+ "jirl\002jr\002la\006la.abs\tla.global\006la.got\010la.local\010la.pcrel"
+ "\tla.tls.gd\tla.tls.ie\tla.tls.ld\tla.tls.le\004ld.b\005ld.bu\004ld.d\004"
+ "ld.h\005ld.hu\004ld.w\005ld.wu\005lddir\006ldgt.b\006ldgt.d\006ldgt.h\006"
+ "ldgt.w\006ldle.b\006ldle.d\006ldle.h\006ldle.w\005ldpte\007ldptr.d\007l"
+ "dptr.w\005ldx.b\006ldx.bu\005ldx.d\005ldx.h\006ldx.hu\005ldx.w\006ldx.w"
+ "u\004li.d\004li.w\004ll.d\004ll.w\007lu12i.w\007lu32i.d\007lu52i.d\007m"
+ "askeqz\007masknez\005mod.d\006mod.du\005mod.w\006mod.wu\010movcf2fr\010"
+ "movcf2gr\004move\nmovfcsr2gr\010movfr2cf\nmovfr2gr.d\nmovfr2gr.s\013mov"
+ "frh2gr.s\010movgr2cf\nmovgr2fcsr\nmovgr2fr.d\nmovgr2fr.w\013movgr2frh.w"
+ "\005mul.d\005mul.w\006mulh.d\007mulh.du\006mulh.w\007mulh.wu\010mulw.d."
+ "w\tmulw.d.wu\003nop\003nor\002or\003ori\003orn\006pcaddi\tpcaddu12i\tpc"
+ "addu18i\tpcalau12i\005preld\006preldx\010rdtime.d\trdtimeh.w\trdtimel.w"
+ "\003ret\007revb.2h\007revb.2w\007revb.4h\006revb.d\007revh.2w\006revh.d"
+ "\006rotr.d\006rotr.w\007rotri.d\007rotri.w\004sc.d\004sc.w\005sll.d\005"
+ "sll.w\006slli.d\006slli.w\003slt\004slti\004sltu\005sltui\005sra.d\005s"
+ "ra.w\006srai.d\006srai.w\005srl.d\005srl.w\006srli.d\006srli.w\004st.b\004"
+ "st.d\004st.h\004st.w\006stgt.b\006stgt.d\006stgt.h\006stgt.w\006stle.b\006"
+ "stle.d\006stle.h\006stle.w\007stptr.d\007stptr.w\005stx.b\005stx.d\005s"
+ "tx.h\005stx.w\005sub.d\005sub.w\007syscall\006tlbclr\007tlbfill\010tlbf"
+ "lush\005tlbrd\007tlbsrch\005tlbwr\003xor\004xori";
+
+// Feature bitsets.
+enum : uint8_t {
+ AMFBS_None,
+ AMFBS_HasBasicD,
+ AMFBS_HasBasicF,
+ AMFBS_HasLaGlobalWithAbs,
+ AMFBS_HasLaGlobalWithPcrel,
+ AMFBS_HasLaLocalWithAbs,
+ AMFBS_IsLA64,
+ AMFBS_HasBasicD_IsLA64,
+};
+
+static constexpr FeatureBitset FeatureBitsets[] = {
+ {}, // AMFBS_None
+ {Feature_HasBasicDBit, },
+ {Feature_HasBasicFBit, },
+ {Feature_HasLaGlobalWithAbsBit, },
+ {Feature_HasLaGlobalWithPcrelBit, },
+ {Feature_HasLaLocalWithAbsBit, },
+ {Feature_IsLA64Bit, },
+ {Feature_HasBasicDBit, Feature_IsLA64Bit, },
+};
+
+namespace {
+ struct MatchEntry {
+ uint16_t Mnemonic;
+ uint16_t Opcode;
+ uint8_t ConvertFn;
+ uint8_t RequiredFeaturesIdx;
+ uint8_t Classes[4];
+ StringRef getMnemonic() const {
+ return StringRef(MnemonicTable + Mnemonic + 1,
+ MnemonicTable[Mnemonic]);
+ }
+ };
+
+ // Predicate for searching for an opcode.
+ struct LessOpcode {
+ bool operator()(const MatchEntry &LHS, StringRef RHS) {
+ return LHS.getMnemonic() < RHS;
+ }
+ bool operator()(StringRef LHS, const MatchEntry &RHS) {
+ return LHS < RHS.getMnemonic();
+ }
+ bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
+ return LHS.getMnemonic() < RHS.getMnemonic();
+ }
+ };
+} // end anonymous namespace
+
+static const MatchEntry MatchTable0[] = {
+ { 0 /* add.d */, LoongArch::ADD_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 6 /* add.w */, LoongArch::ADD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 12 /* addi.d */, LoongArch::ADDI_D, Convert__Reg1_0__Reg1_1__SImm12addlike1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_SImm12addlike }, },
+ { 19 /* addi.w */, LoongArch::ADDI_W, Convert__Reg1_0__Reg1_1__SImm12addlike1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12addlike }, },
+ { 26 /* addu16i.d */, LoongArch::ADDU16I_D, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_SImm16 }, },
+ { 36 /* alsl.d */, LoongArch::ALSL_D, Convert__Reg1_0__Reg1_1__Reg1_2__UImm2plus11_3, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2plus1 }, },
+ { 43 /* alsl.w */, LoongArch::ALSL_W, Convert__Reg1_0__Reg1_1__Reg1_2__UImm2plus11_3, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2plus1 }, },
+ { 50 /* alsl.wu */, LoongArch::ALSL_WU, Convert__Reg1_0__Reg1_1__Reg1_2__UImm2plus11_3, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2plus1 }, },
+ { 58 /* amadd.d */, LoongArch::AMADD_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 66 /* amadd.w */, LoongArch::AMADD_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 74 /* amadd_db.d */, LoongArch::AMADD_DB_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 85 /* amadd_db.w */, LoongArch::AMADD_DB_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 96 /* amand.d */, LoongArch::AMAND_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 104 /* amand.w */, LoongArch::AMAND_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 112 /* amand_db.d */, LoongArch::AMAND_DB_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 123 /* amand_db.w */, LoongArch::AMAND_DB_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 134 /* ammax.d */, LoongArch::AMMAX_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 142 /* ammax.du */, LoongArch::AMMAX_DU, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 151 /* ammax.w */, LoongArch::AMMAX_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 159 /* ammax.wu */, LoongArch::AMMAX_WU, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 168 /* ammax_db.d */, LoongArch::AMMAX_DB_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 179 /* ammax_db.du */, LoongArch::AMMAX_DB_DU, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 191 /* ammax_db.w */, LoongArch::AMMAX_DB_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 202 /* ammax_db.wu */, LoongArch::AMMAX_DB_WU, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 214 /* ammin.d */, LoongArch::AMMIN_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 222 /* ammin.du */, LoongArch::AMMIN_DU, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 231 /* ammin.w */, LoongArch::AMMIN_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 239 /* ammin.wu */, LoongArch::AMMIN_WU, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 248 /* ammin_db.d */, LoongArch::AMMIN_DB_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 259 /* ammin_db.du */, LoongArch::AMMIN_DB_DU, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 271 /* ammin_db.w */, LoongArch::AMMIN_DB_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 282 /* ammin_db.wu */, LoongArch::AMMIN_DB_WU, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 294 /* amor.d */, LoongArch::AMOR_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 301 /* amor.w */, LoongArch::AMOR_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 308 /* amor_db.d */, LoongArch::AMOR_DB_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 318 /* amor_db.w */, LoongArch::AMOR_DB_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 328 /* amswap.d */, LoongArch::AMSWAP_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 337 /* amswap.w */, LoongArch::AMSWAP_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 346 /* amswap_db.d */, LoongArch::AMSWAP_DB_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 358 /* amswap_db.w */, LoongArch::AMSWAP_DB_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 370 /* amxor.d */, LoongArch::AMXOR_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 378 /* amxor.w */, LoongArch::AMXOR_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 386 /* amxor_db.d */, LoongArch::AMXOR_DB_D, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 397 /* amxor_db.w */, LoongArch::AMXOR_DB_W, Convert__Reg1_0__Reg1_1__AtomicMemAsmOperand1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_AtomicMemAsmOperand }, },
+ { 408 /* and */, LoongArch::AND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 412 /* andi */, LoongArch::ANDI, Convert__Reg1_0__Reg1_1__UImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImm12 }, },
+ { 417 /* andn */, LoongArch::ANDN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 422 /* asrtgt.d */, LoongArch::ASRTGT_D, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 431 /* asrtle.d */, LoongArch::ASRTLE_D, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 440 /* b */, LoongArch::B, Convert__SImm26OperandB1_0, AMFBS_None, { MCK_SImm26OperandB }, },
+ { 442 /* bceqz */, LoongArch::BCEQZ, Convert__Reg1_0__SImm21lsl21_1, AMFBS_HasBasicF, { MCK_CFR, MCK_SImm21lsl2 }, },
+ { 448 /* bcnez */, LoongArch::BCNEZ, Convert__Reg1_0__SImm21lsl21_1, AMFBS_HasBasicF, { MCK_CFR, MCK_SImm21lsl2 }, },
+ { 454 /* beq */, LoongArch::BEQ, Convert__Reg1_0__Reg1_1__SImm16lsl21_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm16lsl2 }, },
+ { 458 /* beqz */, LoongArch::BEQZ, Convert__Reg1_0__SImm21lsl21_1, AMFBS_None, { MCK_GPR, MCK_SImm21lsl2 }, },
+ { 463 /* bge */, LoongArch::BGE, Convert__Reg1_0__Reg1_1__SImm16lsl21_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm16lsl2 }, },
+ { 467 /* bgeu */, LoongArch::BGEU, Convert__Reg1_0__Reg1_1__SImm16lsl21_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm16lsl2 }, },
+ { 472 /* bgez */, LoongArch::BGE, Convert__Reg1_0__regR0__SImm16lsl21_1, AMFBS_None, { MCK_GPR, MCK_SImm16lsl2 }, },
+ { 477 /* bgt */, LoongArch::BLT, Convert__Reg1_1__Reg1_0__SImm16lsl21_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm16lsl2 }, },
+ { 481 /* bgtu */, LoongArch::BLTU, Convert__Reg1_1__Reg1_0__SImm16lsl21_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm16lsl2 }, },
+ { 486 /* bgtz */, LoongArch::BLT, Convert__regR0__Reg1_0__SImm16lsl21_1, AMFBS_None, { MCK_GPR, MCK_SImm16lsl2 }, },
+ { 491 /* bitrev.4b */, LoongArch::BITREV_4B, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 501 /* bitrev.8b */, LoongArch::BITREV_8B, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 511 /* bitrev.d */, LoongArch::BITREV_D, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 520 /* bitrev.w */, LoongArch::BITREV_W, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 529 /* bl */, LoongArch::BL, Convert__SImm26OperandBL1_0, AMFBS_None, { MCK_SImm26OperandBL }, },
+ { 532 /* ble */, LoongArch::BGE, Convert__Reg1_1__Reg1_0__SImm16lsl21_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm16lsl2 }, },
+ { 536 /* bleu */, LoongArch::BGEU, Convert__Reg1_1__Reg1_0__SImm16lsl21_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm16lsl2 }, },
+ { 541 /* blez */, LoongArch::BGE, Convert__regR0__Reg1_0__SImm16lsl21_1, AMFBS_None, { MCK_GPR, MCK_SImm16lsl2 }, },
+ { 546 /* blt */, LoongArch::BLT, Convert__Reg1_0__Reg1_1__SImm16lsl21_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm16lsl2 }, },
+ { 550 /* bltu */, LoongArch::BLTU, Convert__Reg1_0__Reg1_1__SImm16lsl21_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm16lsl2 }, },
+ { 555 /* bltz */, LoongArch::BLT, Convert__Reg1_0__regR0__SImm16lsl21_1, AMFBS_None, { MCK_GPR, MCK_SImm16lsl2 }, },
+ { 560 /* bne */, LoongArch::BNE, Convert__Reg1_0__Reg1_1__SImm16lsl21_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm16lsl2 }, },
+ { 564 /* bnez */, LoongArch::BNEZ, Convert__Reg1_0__SImm21lsl21_1, AMFBS_None, { MCK_GPR, MCK_SImm21lsl2 }, },
+ { 569 /* break */, LoongArch::BREAK, Convert__UImm151_0, AMFBS_None, { MCK_UImm15 }, },
+ { 575 /* bstrins.d */, LoongArch::BSTRINS_D, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm61_2__UImm61_3, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_UImm6, MCK_UImm6 }, },
+ { 585 /* bstrins.w */, LoongArch::BSTRINS_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm51_2__UImm51_3, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
+ { 595 /* bstrpick.d */, LoongArch::BSTRPICK_D, Convert__Reg1_0__Reg1_1__UImm61_2__UImm61_3, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_UImm6, MCK_UImm6 }, },
+ { 606 /* bstrpick.w */, LoongArch::BSTRPICK_W, Convert__Reg1_0__Reg1_1__UImm51_2__UImm51_3, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImm5, MCK_UImm5 }, },
+ { 617 /* bytepick.d */, LoongArch::BYTEPICK_D, Convert__Reg1_0__Reg1_1__Reg1_2__UImm31_3, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm3 }, },
+ { 628 /* bytepick.w */, LoongArch::BYTEPICK_W, Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_UImm2 }, },
+ { 639 /* cacop */, LoongArch::CACOP, Convert__UImm51_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_UImm5, MCK_GPR, MCK_SImm12 }, },
+ { 645 /* clo.d */, LoongArch::CLO_D, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 651 /* clo.w */, LoongArch::CLO_W, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 657 /* clz.d */, LoongArch::CLZ_D, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 663 /* clz.w */, LoongArch::CLZ_W, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 669 /* cpucfg */, LoongArch::CPUCFG, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 676 /* crc.w.b.w */, LoongArch::CRC_W_B_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 686 /* crc.w.d.w */, LoongArch::CRC_W_D_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 696 /* crc.w.h.w */, LoongArch::CRC_W_H_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 706 /* crc.w.w.w */, LoongArch::CRC_W_W_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 716 /* crcc.w.b.w */, LoongArch::CRCC_W_B_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 727 /* crcc.w.d.w */, LoongArch::CRCC_W_D_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 738 /* crcc.w.h.w */, LoongArch::CRCC_W_H_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 749 /* crcc.w.w.w */, LoongArch::CRCC_W_W_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 760 /* csrrd */, LoongArch::CSRRD, Convert__Reg1_0__UImm141_1, AMFBS_None, { MCK_GPR, MCK_UImm14 }, },
+ { 766 /* csrwr */, LoongArch::CSRWR, Convert__Reg1_0__Tie0_1_1__UImm141_1, AMFBS_None, { MCK_GPR, MCK_UImm14 }, },
+ { 772 /* csrxchg */, LoongArch::CSRXCHG, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm141_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImm14 }, },
+ { 780 /* cto.d */, LoongArch::CTO_D, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 786 /* cto.w */, LoongArch::CTO_W, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 792 /* ctz.d */, LoongArch::CTZ_D, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 798 /* ctz.w */, LoongArch::CTZ_W, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 804 /* dbar */, LoongArch::DBAR, Convert__UImm151_0, AMFBS_None, { MCK_UImm15 }, },
+ { 809 /* dbcl */, LoongArch::DBCL, Convert__UImm151_0, AMFBS_None, { MCK_UImm15 }, },
+ { 814 /* div.d */, LoongArch::DIV_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 820 /* div.du */, LoongArch::DIV_DU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 827 /* div.w */, LoongArch::DIV_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 833 /* div.wu */, LoongArch::DIV_WU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 840 /* ertn */, LoongArch::ERTN, Convert_NoOperands, AMFBS_None, { }, },
+ { 845 /* ext.w.b */, LoongArch::EXT_W_B, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 853 /* ext.w.h */, LoongArch::EXT_W_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 861 /* fabs.d */, LoongArch::FABS_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 868 /* fabs.s */, LoongArch::FABS_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 875 /* fadd.d */, LoongArch::FADD_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 882 /* fadd.s */, LoongArch::FADD_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 889 /* fclass.d */, LoongArch::FCLASS_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 898 /* fclass.s */, LoongArch::FCLASS_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 907 /* fcmp.caf.d */, LoongArch::FCMP_CAF_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 918 /* fcmp.caf.s */, LoongArch::FCMP_CAF_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 929 /* fcmp.ceq.d */, LoongArch::FCMP_CEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 940 /* fcmp.ceq.s */, LoongArch::FCMP_CEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 951 /* fcmp.cle.d */, LoongArch::FCMP_CLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 962 /* fcmp.cle.s */, LoongArch::FCMP_CLE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 973 /* fcmp.clt.d */, LoongArch::FCMP_CLT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 984 /* fcmp.clt.s */, LoongArch::FCMP_CLT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 995 /* fcmp.cne.d */, LoongArch::FCMP_CNE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1006 /* fcmp.cne.s */, LoongArch::FCMP_CNE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1017 /* fcmp.cor.d */, LoongArch::FCMP_COR_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1028 /* fcmp.cor.s */, LoongArch::FCMP_COR_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1039 /* fcmp.cueq.d */, LoongArch::FCMP_CUEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1051 /* fcmp.cueq.s */, LoongArch::FCMP_CUEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1063 /* fcmp.cule.d */, LoongArch::FCMP_CULE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1075 /* fcmp.cule.s */, LoongArch::FCMP_CULE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1087 /* fcmp.cult.d */, LoongArch::FCMP_CULT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1099 /* fcmp.cult.s */, LoongArch::FCMP_CULT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1111 /* fcmp.cun.d */, LoongArch::FCMP_CUN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1122 /* fcmp.cun.s */, LoongArch::FCMP_CUN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1133 /* fcmp.cune.d */, LoongArch::FCMP_CUNE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1145 /* fcmp.cune.s */, LoongArch::FCMP_CUNE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1157 /* fcmp.saf.d */, LoongArch::FCMP_SAF_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1168 /* fcmp.saf.s */, LoongArch::FCMP_SAF_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1179 /* fcmp.seq.d */, LoongArch::FCMP_SEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1190 /* fcmp.seq.s */, LoongArch::FCMP_SEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1201 /* fcmp.sle.d */, LoongArch::FCMP_SLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1212 /* fcmp.sle.s */, LoongArch::FCMP_SLE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1223 /* fcmp.slt.d */, LoongArch::FCMP_SLT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1234 /* fcmp.slt.s */, LoongArch::FCMP_SLT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1245 /* fcmp.sne.d */, LoongArch::FCMP_SNE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1256 /* fcmp.sne.s */, LoongArch::FCMP_SNE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1267 /* fcmp.sor.d */, LoongArch::FCMP_SOR_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1278 /* fcmp.sor.s */, LoongArch::FCMP_SOR_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1289 /* fcmp.sueq.d */, LoongArch::FCMP_SUEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1301 /* fcmp.sueq.s */, LoongArch::FCMP_SUEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1313 /* fcmp.sule.d */, LoongArch::FCMP_SULE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1325 /* fcmp.sule.s */, LoongArch::FCMP_SULE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1337 /* fcmp.sult.d */, LoongArch::FCMP_SULT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1349 /* fcmp.sult.s */, LoongArch::FCMP_SULT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1361 /* fcmp.sun.d */, LoongArch::FCMP_SUN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1372 /* fcmp.sun.s */, LoongArch::FCMP_SUN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1383 /* fcmp.sune.d */, LoongArch::FCMP_SUNE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_CFR, MCK_FPR64, MCK_FPR64 }, },
+ { 1395 /* fcmp.sune.s */, LoongArch::FCMP_SUNE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32, MCK_FPR32 }, },
+ { 1407 /* fcopysign.d */, LoongArch::FCOPYSIGN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1419 /* fcopysign.s */, LoongArch::FCOPYSIGN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1431 /* fcvt.d.s */, LoongArch::FCVT_D_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR32 }, },
+ { 1440 /* fcvt.s.d */, LoongArch::FCVT_S_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR32, MCK_FPR64 }, },
+ { 1449 /* fdiv.d */, LoongArch::FDIV_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1456 /* fdiv.s */, LoongArch::FDIV_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1463 /* ffint.d.l */, LoongArch::FFINT_D_L, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1473 /* ffint.d.w */, LoongArch::FFINT_D_W, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR32 }, },
+ { 1483 /* ffint.s.l */, LoongArch::FFINT_S_L, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR32, MCK_FPR64 }, },
+ { 1493 /* ffint.s.w */, LoongArch::FFINT_S_W, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 1503 /* fld.d */, LoongArch::FLD_D, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_GPR, MCK_SImm12 }, },
+ { 1509 /* fld.s */, LoongArch::FLD_S, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_GPR, MCK_SImm12 }, },
+ { 1515 /* fldgt.d */, LoongArch::FLDGT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_GPR, MCK_GPR }, },
+ { 1523 /* fldgt.s */, LoongArch::FLDGT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_GPR, MCK_GPR }, },
+ { 1531 /* fldle.d */, LoongArch::FLDLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_GPR, MCK_GPR }, },
+ { 1539 /* fldle.s */, LoongArch::FLDLE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_GPR, MCK_GPR }, },
+ { 1547 /* fldx.d */, LoongArch::FLDX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_GPR, MCK_GPR }, },
+ { 1554 /* fldx.s */, LoongArch::FLDX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_GPR, MCK_GPR }, },
+ { 1561 /* flogb.d */, LoongArch::FLOGB_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1569 /* flogb.s */, LoongArch::FLOGB_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 1577 /* fmadd.d */, LoongArch::FMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1585 /* fmadd.s */, LoongArch::FMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1593 /* fmax.d */, LoongArch::FMAX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1600 /* fmax.s */, LoongArch::FMAX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1607 /* fmaxa.d */, LoongArch::FMAXA_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1615 /* fmaxa.s */, LoongArch::FMAXA_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1623 /* fmin.d */, LoongArch::FMIN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1630 /* fmin.s */, LoongArch::FMIN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1637 /* fmina.d */, LoongArch::FMINA_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1645 /* fmina.s */, LoongArch::FMINA_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1653 /* fmov.d */, LoongArch::FMOV_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1660 /* fmov.s */, LoongArch::FMOV_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 1667 /* fmsub.d */, LoongArch::FMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1675 /* fmsub.s */, LoongArch::FMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1683 /* fmul.d */, LoongArch::FMUL_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1690 /* fmul.s */, LoongArch::FMUL_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1697 /* fneg.d */, LoongArch::FNEG_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1704 /* fneg.s */, LoongArch::FNEG_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 1711 /* fnmadd.d */, LoongArch::FNMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1720 /* fnmadd.s */, LoongArch::FNMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1729 /* fnmsub.d */, LoongArch::FNMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1738 /* fnmsub.s */, LoongArch::FNMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1747 /* frecip.d */, LoongArch::FRECIP_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1756 /* frecip.s */, LoongArch::FRECIP_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 1765 /* frint.d */, LoongArch::FRINT_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1773 /* frint.s */, LoongArch::FRINT_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 1781 /* frsqrt.d */, LoongArch::FRSQRT_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1790 /* frsqrt.s */, LoongArch::FRSQRT_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 1799 /* fscaleb.d */, LoongArch::FSCALEB_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1809 /* fscaleb.s */, LoongArch::FSCALEB_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1819 /* fsel */, LoongArch::FSEL_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_CFR }, },
+ { 1824 /* fsqrt.d */, LoongArch::FSQRT_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1832 /* fsqrt.s */, LoongArch::FSQRT_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 1840 /* fst.d */, LoongArch::FST_D, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_GPR, MCK_SImm12 }, },
+ { 1846 /* fst.s */, LoongArch::FST_S, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_GPR, MCK_SImm12 }, },
+ { 1852 /* fstgt.d */, LoongArch::FSTGT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_GPR, MCK_GPR }, },
+ { 1860 /* fstgt.s */, LoongArch::FSTGT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_GPR, MCK_GPR }, },
+ { 1868 /* fstle.d */, LoongArch::FSTLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_GPR, MCK_GPR }, },
+ { 1876 /* fstle.s */, LoongArch::FSTLE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_GPR, MCK_GPR }, },
+ { 1884 /* fstx.d */, LoongArch::FSTX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_GPR, MCK_GPR }, },
+ { 1891 /* fstx.s */, LoongArch::FSTX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_GPR, MCK_GPR }, },
+ { 1898 /* fsub.d */, LoongArch::FSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1905 /* fsub.s */, LoongArch::FSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1912 /* ftint.l.d */, LoongArch::FTINT_L_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1922 /* ftint.l.s */, LoongArch::FTINT_L_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR32 }, },
+ { 1932 /* ftint.w.d */, LoongArch::FTINT_W_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR32, MCK_FPR64 }, },
+ { 1942 /* ftint.w.s */, LoongArch::FTINT_W_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 1952 /* ftintrm.l.d */, LoongArch::FTINTRM_L_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1964 /* ftintrm.l.s */, LoongArch::FTINTRM_L_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR32 }, },
+ { 1976 /* ftintrm.w.d */, LoongArch::FTINTRM_W_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR32, MCK_FPR64 }, },
+ { 1988 /* ftintrm.w.s */, LoongArch::FTINTRM_W_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 2000 /* ftintrne.l.d */, LoongArch::FTINTRNE_L_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 2013 /* ftintrne.l.s */, LoongArch::FTINTRNE_L_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR32 }, },
+ { 2026 /* ftintrne.w.d */, LoongArch::FTINTRNE_W_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR32, MCK_FPR64 }, },
+ { 2039 /* ftintrne.w.s */, LoongArch::FTINTRNE_W_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 2052 /* ftintrp.l.d */, LoongArch::FTINTRP_L_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 2064 /* ftintrp.l.s */, LoongArch::FTINTRP_L_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR32 }, },
+ { 2076 /* ftintrp.w.d */, LoongArch::FTINTRP_W_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR32, MCK_FPR64 }, },
+ { 2088 /* ftintrp.w.s */, LoongArch::FTINTRP_W_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 2100 /* ftintrz.l.d */, LoongArch::FTINTRZ_L_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR64 }, },
+ { 2112 /* ftintrz.l.s */, LoongArch::FTINTRZ_L_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_FPR32 }, },
+ { 2124 /* ftintrz.w.d */, LoongArch::FTINTRZ_W_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_FPR32, MCK_FPR64 }, },
+ { 2136 /* ftintrz.w.s */, LoongArch::FTINTRZ_W_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_FPR32 }, },
+ { 2148 /* ibar */, LoongArch::IBAR, Convert__UImm151_0, AMFBS_None, { MCK_UImm15 }, },
+ { 2153 /* idle */, LoongArch::IDLE, Convert__UImm151_0, AMFBS_None, { MCK_UImm15 }, },
+ { 2158 /* invtlb */, LoongArch::INVTLB, Convert__Reg1_2__Reg1_1__UImm51_0, AMFBS_None, { MCK_UImm5, MCK_GPR, MCK_GPR }, },
+ { 2165 /* iocsrrd.b */, LoongArch::IOCSRRD_B, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2175 /* iocsrrd.d */, LoongArch::IOCSRRD_D, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 2185 /* iocsrrd.h */, LoongArch::IOCSRRD_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2195 /* iocsrrd.w */, LoongArch::IOCSRRD_W, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2205 /* iocsrwr.b */, LoongArch::IOCSRWR_B, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2215 /* iocsrwr.d */, LoongArch::IOCSRWR_D, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 2225 /* iocsrwr.h */, LoongArch::IOCSRWR_H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2235 /* iocsrwr.w */, LoongArch::IOCSRWR_W, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2245 /* jirl */, LoongArch::JIRL, Convert__Reg1_0__Reg1_1__SImm16lsl21_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm16lsl2 }, },
+ { 2250 /* jr */, LoongArch::JIRL, Convert__regR0__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
+ { 2253 /* la */, LoongArch::PseudoLA_PCREL, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasLaGlobalWithPcrel, { MCK_GPR, MCK_BareSymbol }, },
+ { 2253 /* la */, LoongArch::PseudoLA_ABS, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasLaGlobalWithAbs, { MCK_GPR, MCK_BareSymbol }, },
+ { 2253 /* la */, LoongArch::PseudoLA_GOT, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2256 /* la.abs */, LoongArch::PseudoLA_ABS, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2256 /* la.abs */, LoongArch::PseudoLA_ABS_LARGE, Convert__Reg1_0__imm_95_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2263 /* la.global */, LoongArch::PseudoLA_PCREL, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasLaGlobalWithPcrel, { MCK_GPR, MCK_BareSymbol }, },
+ { 2263 /* la.global */, LoongArch::PseudoLA_ABS, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasLaGlobalWithAbs, { MCK_GPR, MCK_BareSymbol }, },
+ { 2263 /* la.global */, LoongArch::PseudoLA_GOT, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2263 /* la.global */, LoongArch::PseudoLA_PCREL_LARGE, Convert__Reg1_0__Reg1_1__BareSymbol1_2, AMFBS_HasLaGlobalWithPcrel, { MCK_GPR, MCK_GPR, MCK_BareSymbol }, },
+ { 2263 /* la.global */, LoongArch::PseudoLA_ABS_LARGE, Convert__Reg1_0__Reg1_1__BareSymbol1_2, AMFBS_HasLaGlobalWithAbs, { MCK_GPR, MCK_GPR, MCK_BareSymbol }, },
+ { 2263 /* la.global */, LoongArch::PseudoLA_GOT_LARGE, Convert__Reg1_0__Reg1_1__BareSymbol1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSymbol }, },
+ { 2273 /* la.got */, LoongArch::PseudoLA_GOT, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2273 /* la.got */, LoongArch::PseudoLA_GOT_LARGE, Convert__Reg1_0__Reg1_1__BareSymbol1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_BareSymbol }, },
+ { 2280 /* la.local */, LoongArch::PseudoLA_ABS, Convert__Reg1_0__BareSymbol1_1, AMFBS_HasLaLocalWithAbs, { MCK_GPR, MCK_BareSymbol }, },
+ { 2280 /* la.local */, LoongArch::PseudoLA_PCREL, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2280 /* la.local */, LoongArch::PseudoLA_ABS_LARGE, Convert__Reg1_0__Reg1_1__BareSymbol1_2, AMFBS_HasLaLocalWithAbs, { MCK_GPR, MCK_GPR, MCK_BareSymbol }, },
+ { 2280 /* la.local */, LoongArch::PseudoLA_PCREL_LARGE, Convert__Reg1_0__Reg1_1__BareSymbol1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_BareSymbol }, },
+ { 2289 /* la.pcrel */, LoongArch::PseudoLA_PCREL, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2289 /* la.pcrel */, LoongArch::PseudoLA_PCREL_LARGE, Convert__Reg1_0__Reg1_1__BareSymbol1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_BareSymbol }, },
+ { 2298 /* la.tls.gd */, LoongArch::PseudoLA_TLS_GD, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2298 /* la.tls.gd */, LoongArch::PseudoLA_TLS_GD_LARGE, Convert__Reg1_0__Reg1_1__BareSymbol1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_BareSymbol }, },
+ { 2308 /* la.tls.ie */, LoongArch::PseudoLA_TLS_IE, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2308 /* la.tls.ie */, LoongArch::PseudoLA_TLS_IE_LARGE, Convert__Reg1_0__Reg1_1__BareSymbol1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_BareSymbol }, },
+ { 2318 /* la.tls.ld */, LoongArch::PseudoLA_TLS_LD, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2318 /* la.tls.ld */, LoongArch::PseudoLA_TLS_LD_LARGE, Convert__Reg1_0__Reg1_1__BareSymbol1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_BareSymbol }, },
+ { 2328 /* la.tls.le */, LoongArch::PseudoLA_TLS_LE, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2338 /* ld.b */, LoongArch::LD_B, Convert__Reg1_0__Reg1_1__SImm12addlike1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12addlike }, },
+ { 2343 /* ld.bu */, LoongArch::LD_BU, Convert__Reg1_0__Reg1_1__SImm12addlike1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12addlike }, },
+ { 2349 /* ld.d */, LoongArch::LD_D, Convert__Reg1_0__Reg1_1__SImm12addlike1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_SImm12addlike }, },
+ { 2354 /* ld.h */, LoongArch::LD_H, Convert__Reg1_0__Reg1_1__SImm12addlike1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12addlike }, },
+ { 2359 /* ld.hu */, LoongArch::LD_HU, Convert__Reg1_0__Reg1_1__SImm12addlike1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12addlike }, },
+ { 2365 /* ld.w */, LoongArch::LD_W, Convert__Reg1_0__Reg1_1__SImm12addlike1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12addlike }, },
+ { 2370 /* ld.wu */, LoongArch::LD_WU, Convert__Reg1_0__Reg1_1__SImm12addlike1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_SImm12addlike }, },
+ { 2376 /* lddir */, LoongArch::LDDIR, Convert__Reg1_0__Reg1_1__UImm81_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImm8 }, },
+ { 2382 /* ldgt.b */, LoongArch::LDGT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2389 /* ldgt.d */, LoongArch::LDGT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2396 /* ldgt.h */, LoongArch::LDGT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2403 /* ldgt.w */, LoongArch::LDGT_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2410 /* ldle.b */, LoongArch::LDLE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2417 /* ldle.d */, LoongArch::LDLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2424 /* ldle.h */, LoongArch::LDLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2431 /* ldle.w */, LoongArch::LDLE_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2438 /* ldpte */, LoongArch::LDPTE, Convert__Reg1_0__UImm81_1, AMFBS_None, { MCK_GPR, MCK_UImm8 }, },
+ { 2444 /* ldptr.d */, LoongArch::LDPTR_D, Convert__Reg1_0__Reg1_1__SImm14lsl21_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_SImm14lsl2 }, },
+ { 2452 /* ldptr.w */, LoongArch::LDPTR_W, Convert__Reg1_0__Reg1_1__SImm14lsl21_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_SImm14lsl2 }, },
+ { 2460 /* ldx.b */, LoongArch::LDX_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2466 /* ldx.bu */, LoongArch::LDX_BU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2473 /* ldx.d */, LoongArch::LDX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2479 /* ldx.h */, LoongArch::LDX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2485 /* ldx.hu */, LoongArch::LDX_HU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2492 /* ldx.w */, LoongArch::LDX_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2498 /* ldx.wu */, LoongArch::LDX_WU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2505 /* li.d */, LoongArch::PseudoLI_D, Convert__Reg1_0__Imm1_1, AMFBS_IsLA64, { MCK_GPR, MCK_Imm }, },
+ { 2510 /* li.w */, LoongArch::PseudoLI_W, Convert__Reg1_0__Imm321_1, AMFBS_None, { MCK_GPR, MCK_Imm32 }, },
+ { 2515 /* ll.d */, LoongArch::LL_D, Convert__Reg1_0__Reg1_1__SImm14lsl21_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_SImm14lsl2 }, },
+ { 2520 /* ll.w */, LoongArch::LL_W, Convert__Reg1_0__Reg1_1__SImm14lsl21_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm14lsl2 }, },
+ { 2525 /* lu12i.w */, LoongArch::LU12I_W, Convert__Reg1_0__SImm20lu12iw1_1, AMFBS_None, { MCK_GPR, MCK_SImm20lu12iw }, },
+ { 2533 /* lu32i.d */, LoongArch::LU32I_D, Convert__Reg1_0__Tie0_1_1__SImm20lu32id1_1, AMFBS_IsLA64, { MCK_GPR, MCK_SImm20lu32id }, },
+ { 2541 /* lu52i.d */, LoongArch::LU52I_D, Convert__Reg1_0__Reg1_1__SImm12lu52id1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_SImm12lu52id }, },
+ { 2549 /* maskeqz */, LoongArch::MASKEQZ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2557 /* masknez */, LoongArch::MASKNEZ, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2565 /* mod.d */, LoongArch::MOD_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2571 /* mod.du */, LoongArch::MOD_DU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2578 /* mod.w */, LoongArch::MOD_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2584 /* mod.wu */, LoongArch::MOD_WU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2591 /* movcf2fr */, LoongArch::MOVCF2FR_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_CFR }, },
+ { 2600 /* movcf2gr */, LoongArch::MOVCF2GR, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_GPR, MCK_CFR }, },
+ { 2609 /* move */, LoongArch::OR, Convert__Reg1_0__Reg1_1__regR0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2614 /* movfcsr2gr */, LoongArch::MOVFCSR2GR, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_GPR, MCK_FCSR }, },
+ { 2625 /* movfr2cf */, LoongArch::MOVFR2CF_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_CFR, MCK_FPR32 }, },
+ { 2634 /* movfr2gr.d */, LoongArch::MOVFR2GR_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD_IsLA64, { MCK_GPR, MCK_FPR64 }, },
+ { 2645 /* movfr2gr.s */, LoongArch::MOVFR2GR_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_GPR, MCK_FPR32 }, },
+ { 2656 /* movfrh2gr.s */, LoongArch::MOVFRH2GR_S, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD, { MCK_GPR, MCK_FPR64 }, },
+ { 2668 /* movgr2cf */, LoongArch::MOVGR2CF, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_CFR, MCK_GPR }, },
+ { 2677 /* movgr2fcsr */, LoongArch::MOVGR2FCSR, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FCSR, MCK_GPR }, },
+ { 2688 /* movgr2fr.d */, LoongArch::MOVGR2FR_D, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicD_IsLA64, { MCK_FPR64, MCK_GPR }, },
+ { 2699 /* movgr2fr.w */, LoongArch::MOVGR2FR_W, Convert__Reg1_0__Reg1_1, AMFBS_HasBasicF, { MCK_FPR32, MCK_GPR }, },
+ { 2710 /* movgr2frh.w */, LoongArch::MOVGR2FRH_W, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasBasicD, { MCK_FPR64, MCK_GPR }, },
+ { 2722 /* mul.d */, LoongArch::MUL_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2728 /* mul.w */, LoongArch::MUL_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2734 /* mulh.d */, LoongArch::MULH_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2741 /* mulh.du */, LoongArch::MULH_DU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2749 /* mulh.w */, LoongArch::MULH_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2756 /* mulh.wu */, LoongArch::MULH_WU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2764 /* mulw.d.w */, LoongArch::MULW_D_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2773 /* mulw.d.wu */, LoongArch::MULW_D_WU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2783 /* nop */, LoongArch::ANDI, Convert__regR0__regR0__imm_95_0, AMFBS_None, { }, },
+ { 2787 /* nor */, LoongArch::NOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2791 /* or */, LoongArch::OR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2794 /* ori */, LoongArch::ORI, Convert__Reg1_0__Reg1_1__UImm12ori1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImm12ori }, },
+ { 2798 /* orn */, LoongArch::ORN, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2802 /* pcaddi */, LoongArch::PCADDI, Convert__Reg1_0__SImm201_1, AMFBS_None, { MCK_GPR, MCK_SImm20 }, },
+ { 2809 /* pcaddu12i */, LoongArch::PCADDU12I, Convert__Reg1_0__SImm201_1, AMFBS_None, { MCK_GPR, MCK_SImm20 }, },
+ { 2819 /* pcaddu18i */, LoongArch::PCADDU18I, Convert__Reg1_0__SImm201_1, AMFBS_IsLA64, { MCK_GPR, MCK_SImm20 }, },
+ { 2829 /* pcalau12i */, LoongArch::PCALAU12I, Convert__Reg1_0__SImm20pcalau12i1_1, AMFBS_None, { MCK_GPR, MCK_SImm20pcalau12i }, },
+ { 2839 /* preld */, LoongArch::PRELD, Convert__UImm51_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_UImm5, MCK_GPR, MCK_SImm12 }, },
+ { 2845 /* preldx */, LoongArch::PRELDX, Convert__UImm51_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_UImm5, MCK_GPR, MCK_GPR }, },
+ { 2852 /* rdtime.d */, LoongArch::RDTIME_D, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 2861 /* rdtimeh.w */, LoongArch::RDTIMEH_W, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2871 /* rdtimel.w */, LoongArch::RDTIMEL_W, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2881 /* ret */, LoongArch::JIRL, Convert__regR0__regR1__imm_95_0, AMFBS_None, { }, },
+ { 2885 /* revb.2h */, LoongArch::REVB_2H, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2893 /* revb.2w */, LoongArch::REVB_2W, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 2901 /* revb.4h */, LoongArch::REVB_4H, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 2909 /* revb.d */, LoongArch::REVB_D, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 2916 /* revh.2w */, LoongArch::REVH_2W, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 2924 /* revh.d */, LoongArch::REVH_D, Convert__Reg1_0__Reg1_1, AMFBS_IsLA64, { MCK_GPR, MCK_GPR }, },
+ { 2931 /* rotr.d */, LoongArch::ROTR_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2938 /* rotr.w */, LoongArch::ROTR_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2945 /* rotri.d */, LoongArch::ROTRI_D, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
+ { 2953 /* rotri.w */, LoongArch::ROTRI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
+ { 2961 /* sc.d */, LoongArch::SC_D, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm14lsl21_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_SImm14lsl2 }, },
+ { 2966 /* sc.w */, LoongArch::SC_W, Convert__Reg1_0__Tie0_1_1__Reg1_1__SImm14lsl21_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm14lsl2 }, },
+ { 2971 /* sll.d */, LoongArch::SLL_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2977 /* sll.w */, LoongArch::SLL_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2983 /* slli.d */, LoongArch::SLLI_D, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
+ { 2990 /* slli.w */, LoongArch::SLLI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
+ { 2997 /* slt */, LoongArch::SLT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3001 /* slti */, LoongArch::SLTI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 3006 /* sltu */, LoongArch::SLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3011 /* sltui */, LoongArch::SLTUI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 3017 /* sra.d */, LoongArch::SRA_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3023 /* sra.w */, LoongArch::SRA_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3029 /* srai.d */, LoongArch::SRAI_D, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
+ { 3036 /* srai.w */, LoongArch::SRAI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
+ { 3043 /* srl.d */, LoongArch::SRL_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3049 /* srl.w */, LoongArch::SRL_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3055 /* srli.d */, LoongArch::SRLI_D, Convert__Reg1_0__Reg1_1__UImm61_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_UImm6 }, },
+ { 3062 /* srli.w */, LoongArch::SRLI_W, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
+ { 3069 /* st.b */, LoongArch::ST_B, Convert__Reg1_0__Reg1_1__SImm12addlike1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12addlike }, },
+ { 3074 /* st.d */, LoongArch::ST_D, Convert__Reg1_0__Reg1_1__SImm12addlike1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_SImm12addlike }, },
+ { 3079 /* st.h */, LoongArch::ST_H, Convert__Reg1_0__Reg1_1__SImm12addlike1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12addlike }, },
+ { 3084 /* st.w */, LoongArch::ST_W, Convert__Reg1_0__Reg1_1__SImm12addlike1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12addlike }, },
+ { 3089 /* stgt.b */, LoongArch::STGT_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3096 /* stgt.d */, LoongArch::STGT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3103 /* stgt.h */, LoongArch::STGT_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3110 /* stgt.w */, LoongArch::STGT_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3117 /* stle.b */, LoongArch::STLE_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3124 /* stle.d */, LoongArch::STLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3131 /* stle.h */, LoongArch::STLE_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3138 /* stle.w */, LoongArch::STLE_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3145 /* stptr.d */, LoongArch::STPTR_D, Convert__Reg1_0__Reg1_1__SImm14lsl21_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_SImm14lsl2 }, },
+ { 3153 /* stptr.w */, LoongArch::STPTR_W, Convert__Reg1_0__Reg1_1__SImm14lsl21_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_SImm14lsl2 }, },
+ { 3161 /* stx.b */, LoongArch::STX_B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3167 /* stx.d */, LoongArch::STX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3173 /* stx.h */, LoongArch::STX_H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3179 /* stx.w */, LoongArch::STX_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3185 /* sub.d */, LoongArch::SUB_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsLA64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3191 /* sub.w */, LoongArch::SUB_W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3197 /* syscall */, LoongArch::SYSCALL, Convert__UImm151_0, AMFBS_None, { MCK_UImm15 }, },
+ { 3205 /* tlbclr */, LoongArch::TLBCLR, Convert_NoOperands, AMFBS_None, { }, },
+ { 3212 /* tlbfill */, LoongArch::TLBFILL, Convert_NoOperands, AMFBS_None, { }, },
+ { 3220 /* tlbflush */, LoongArch::TLBFLUSH, Convert_NoOperands, AMFBS_None, { }, },
+ { 3229 /* tlbrd */, LoongArch::TLBRD, Convert_NoOperands, AMFBS_None, { }, },
+ { 3235 /* tlbsrch */, LoongArch::TLBSRCH, Convert_NoOperands, AMFBS_None, { }, },
+ { 3243 /* tlbwr */, LoongArch::TLBWR, Convert_NoOperands, AMFBS_None, { }, },
+ { 3249 /* xor */, LoongArch::XOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 3253 /* xori */, LoongArch::XORI, Convert__Reg1_0__Reg1_1__UImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImm12 }, },
+};
+
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/Format.h"
+
+unsigned LoongArchAsmParser::
+MatchInstructionImpl(const OperandVector &Operands,
+ MCInst &Inst,
+ uint64_t &ErrorInfo,
+ FeatureBitset &MissingFeatures,
+ bool matchingInlineAsm, unsigned VariantID) {
+ // Eliminate obvious mismatches.
+ if (Operands.size() > 5) {
+ ErrorInfo = 5;
+ return Match_InvalidOperand;
+ }
+
+ // Get the current feature set.
+ const FeatureBitset &AvailableFeatures = getAvailableFeatures();
+
+ // Get the instruction mnemonic, which is the first token.
+ StringRef Mnemonic = ((LoongArchOperand &)*Operands[0]).getToken();
+
+ // Some state to try to produce better error messages.
+ bool HadMatchOtherThanFeatures = false;
+ bool HadMatchOtherThanPredicate = false;
+ unsigned RetCode = Match_InvalidOperand;
+ MissingFeatures.set();
+ // Set ErrorInfo to the operand that mismatches if it is
+ // wrong for all instances of the instruction.
+ ErrorInfo = ~0ULL;
+ // Find the appropriate table for this asm variant.
+ const MatchEntry *Start, *End;
+ switch (VariantID) {
+ default: llvm_unreachable("invalid variant!");
+ case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
+ }
+ // Search the table.
+ auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
+
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
+ std::distance(MnemonicRange.first, MnemonicRange.second) <<
+ " encodings with mnemonic '" << Mnemonic << "'\n");
+
+ // Return a more specific error code if no mnemonics match.
+ if (MnemonicRange.first == MnemonicRange.second)
+ return Match_MnemonicFail;
+
+ for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
+ it != ie; ++it) {
+ const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
+ bool HasRequiredFeatures =
+ (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
+ << MII.getName(it->Opcode) << "\n");
+ // equal_range guarantees that instruction mnemonic matches.
+ assert(Mnemonic == it->getMnemonic());
+ bool OperandsValid = true;
+ for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 4; ++FormalIdx) {
+ auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
+ DEBUG_WITH_TYPE("asm-matcher",
+ dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
+ << " against actual operand at index " << ActualIdx);
+ if (ActualIdx < Operands.size())
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
+ Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
+ else
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
+ if (ActualIdx >= Operands.size()) {
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
+ if (Formal == InvalidMatchClass) {
+ break;
+ }
+ if (isSubclass(Formal, OptionalMatchClass)) {
+ continue;
+ }
+ OperandsValid = false;
+ ErrorInfo = ActualIdx;
+ break;
+ }
+ MCParsedAsmOperand &Actual = *Operands[ActualIdx];
+ unsigned Diag = validateOperandClass(Actual, Formal);
+ if (Diag == Match_Success) {
+ DEBUG_WITH_TYPE("asm-matcher",
+ dbgs() << "match success using generic matcher\n");
+ ++ActualIdx;
+ continue;
+ }
+ // If the generic handler indicates an invalid operand
+ // failure, check for a special case.
+ if (Diag != Match_Success) {
+ unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
+ if (TargetDiag == Match_Success) {
+ DEBUG_WITH_TYPE("asm-matcher",
+ dbgs() << "match success using target matcher\n");
+ ++ActualIdx;
+ continue;
+ }
+ // If the target matcher returned a specific error code use
+ // that, else use the one from the generic matcher.
+ if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
+ Diag = TargetDiag;
+ }
+ // If current formal operand wasn't matched and it is optional
+ // then try to match next formal operand
+ if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
+ continue;
+ }
+ // If this operand is broken for all of the instances of this
+ // mnemonic, keep track of it so we can report loc info.
+ // If we already had a match that only failed due to a
+ // target predicate, that diagnostic is preferred.
+ if (!HadMatchOtherThanPredicate &&
+ (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
+ if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
+ RetCode = Diag;
+ ErrorInfo = ActualIdx;
+ }
+ // Otherwise, just reject this instance of the mnemonic.
+ OperandsValid = false;
+ break;
+ }
+
+ if (!OperandsValid) {
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
+ "operand mismatches, ignoring "
+ "this opcode\n");
+ continue;
+ }
+ if (!HasRequiredFeatures) {
+ HadMatchOtherThanFeatures = true;
+ FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
+ for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
+ if (NewMissingFeatures[I])
+ dbgs() << ' ' << I;
+ dbgs() << "\n");
+ if (NewMissingFeatures.count() <=
+ MissingFeatures.count())
+ MissingFeatures = NewMissingFeatures;
+ continue;
+ }
+
+ Inst.clear();
+
+ Inst.setOpcode(it->Opcode);
+ // We have a potential match but have not rendered the operands.
+ // Check the target predicate to handle any context sensitive
+ // constraints.
+ // For example, Ties that are referenced multiple times must be
+ // checked here to ensure the input is the same for each match
+ // constraints. If we leave it any later the ties will have been
+ // canonicalized
+ unsigned MatchResult;
+ if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
+ Inst.clear();
+ DEBUG_WITH_TYPE(
+ "asm-matcher",
+ dbgs() << "Early target match predicate failed with diag code "
+ << MatchResult << "\n");
+ RetCode = MatchResult;
+ HadMatchOtherThanPredicate = true;
+ continue;
+ }
+
+ if (matchingInlineAsm) {
+ convertToMapAndConstraints(it->ConvertFn, Operands);
+ if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
+ return Match_InvalidTiedOperand;
+
+ return Match_Success;
+ }
+
+ // We have selected a definite instruction, convert the parsed
+ // operands into the appropriate MCInst.
+ convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
+
+ // We have a potential match. Check the target predicate to
+ // handle any context sensitive constraints.
+ if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
+ DEBUG_WITH_TYPE("asm-matcher",
+ dbgs() << "Target match predicate failed with diag code "
+ << MatchResult << "\n");
+ Inst.clear();
+ RetCode = MatchResult;
+ HadMatchOtherThanPredicate = true;
+ continue;
+ }
+
+ if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
+ return Match_InvalidTiedOperand;
+
+ DEBUG_WITH_TYPE(
+ "asm-matcher",
+ dbgs() << "Opcode result: complete match, selecting this opcode\n");
+ return Match_Success;
+ }
+
+ // Okay, we had no match. Try to return a useful error code.
+ if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
+ return RetCode;
+
+ ErrorInfo = 0;
+ return Match_MissingFeature;
+}
+
+namespace {
+ struct OperandMatchEntry {
+ uint16_t Mnemonic;
+ uint8_t OperandMask;
+ uint8_t Class;
+ uint8_t RequiredFeaturesIdx;
+
+ StringRef getMnemonic() const {
+ return StringRef(MnemonicTable + Mnemonic + 1,
+ MnemonicTable[Mnemonic]);
+ }
+ };
+
+ // Predicate for searching for an opcode.
+ struct LessOpcodeOperand {
+ bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
+ return LHS.getMnemonic() < RHS;
+ }
+ bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
+ return LHS < RHS.getMnemonic();
+ }
+ bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
+ return LHS.getMnemonic() < RHS.getMnemonic();
+ }
+ };
+} // end anonymous namespace
+
+static const OperandMatchEntry OperandMatchTable[64] = {
+ /* Operand List Mnemonic, Mask, Operand Class, Features */
+ { 58 /* amadd.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 66 /* amadd.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 74 /* amadd_db.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 85 /* amadd_db.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 96 /* amand.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 104 /* amand.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 112 /* amand_db.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 123 /* amand_db.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 134 /* ammax.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 142 /* ammax.du */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 151 /* ammax.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 159 /* ammax.wu */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 168 /* ammax_db.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 179 /* ammax_db.du */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 191 /* ammax_db.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 202 /* ammax_db.wu */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 214 /* ammin.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 222 /* ammin.du */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 231 /* ammin.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 239 /* ammin.wu */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 248 /* ammin_db.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 259 /* ammin_db.du */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 271 /* ammin_db.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 282 /* ammin_db.wu */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 294 /* amor.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 301 /* amor.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 308 /* amor_db.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 318 /* amor_db.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 328 /* amswap.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 337 /* amswap.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 346 /* amswap_db.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 358 /* amswap_db.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 370 /* amxor.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 378 /* amxor.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 386 /* amxor_db.d */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 397 /* amxor_db.w */, 4 /* 2 */, MCK_AtomicMemAsmOperand, AMFBS_IsLA64 },
+ { 440 /* b */, 1 /* 0 */, MCK_SImm26OperandB, AMFBS_None },
+ { 529 /* bl */, 1 /* 0 */, MCK_SImm26OperandBL, AMFBS_None },
+ { 2253 /* la */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasLaGlobalWithPcrel },
+ { 2253 /* la */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasLaGlobalWithAbs },
+ { 2253 /* la */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2256 /* la.abs */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2256 /* la.abs */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2263 /* la.global */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasLaGlobalWithPcrel },
+ { 2263 /* la.global */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasLaGlobalWithAbs },
+ { 2263 /* la.global */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2263 /* la.global */, 4 /* 2 */, MCK_BareSymbol, AMFBS_HasLaGlobalWithPcrel },
+ { 2263 /* la.global */, 4 /* 2 */, MCK_BareSymbol, AMFBS_HasLaGlobalWithAbs },
+ { 2263 /* la.global */, 4 /* 2 */, MCK_BareSymbol, AMFBS_None },
+ { 2273 /* la.got */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2273 /* la.got */, 4 /* 2 */, MCK_BareSymbol, AMFBS_IsLA64 },
+ { 2280 /* la.local */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasLaLocalWithAbs },
+ { 2280 /* la.local */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2280 /* la.local */, 4 /* 2 */, MCK_BareSymbol, AMFBS_HasLaLocalWithAbs },
+ { 2280 /* la.local */, 4 /* 2 */, MCK_BareSymbol, AMFBS_None },
+ { 2289 /* la.pcrel */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2289 /* la.pcrel */, 4 /* 2 */, MCK_BareSymbol, AMFBS_IsLA64 },
+ { 2298 /* la.tls.gd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2298 /* la.tls.gd */, 4 /* 2 */, MCK_BareSymbol, AMFBS_IsLA64 },
+ { 2308 /* la.tls.ie */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2308 /* la.tls.ie */, 4 /* 2 */, MCK_BareSymbol, AMFBS_IsLA64 },
+ { 2318 /* la.tls.ld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2318 /* la.tls.ld */, 4 /* 2 */, MCK_BareSymbol, AMFBS_IsLA64 },
+ { 2328 /* la.tls.le */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+};
+
+OperandMatchResultTy LoongArchAsmParser::
+tryCustomParseOperand(OperandVector &Operands,
+ unsigned MCK) {
+
+ switch(MCK) {
+ case MCK_AtomicMemAsmOperand:
+ return parseAtomicMemOp(Operands);
+ case MCK_BareSymbol:
+ return parseImmediate(Operands);
+ case MCK_SImm26OperandB:
+ return parseImmediate(Operands);
+ case MCK_SImm26OperandBL:
+ return parseSImm26Operand(Operands);
+ default:
+ return MatchOperand_NoMatch;
+ }
+ return MatchOperand_NoMatch;
+}
+
+OperandMatchResultTy LoongArchAsmParser::
+MatchOperandParserImpl(OperandVector &Operands,
+ StringRef Mnemonic,
+ bool ParseForAllFeatures) {
+ // Get the current feature set.
+ const FeatureBitset &AvailableFeatures = getAvailableFeatures();
+
+ // Get the next operand index.
+ unsigned NextOpNum = Operands.size() - 1;
+ // Search the table.
+ auto MnemonicRange =
+ std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
+ Mnemonic, LessOpcodeOperand());
+
+ if (MnemonicRange.first == MnemonicRange.second)
+ return MatchOperand_NoMatch;
+
+ for (const OperandMatchEntry *it = MnemonicRange.first,
+ *ie = MnemonicRange.second; it != ie; ++it) {
+ // equal_range guarantees that instruction mnemonic matches.
+ assert(Mnemonic == it->getMnemonic());
+
+ // check if the available features match
+ const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
+ if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
+ continue;
+
+ // check if the operand in question has a custom parser.
+ if (!(it->OperandMask & (1 << NextOpNum)))
+ continue;
+
+ // call custom parse method to handle the operand
+ OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
+ if (Result != MatchOperand_NoMatch)
+ return Result;
+ }
+
+ // Okay, we had no match.
+ return MatchOperand_NoMatch;
+}
+
+#endif // GET_MATCHER_IMPLEMENTATION
+
+
+#ifdef GET_MNEMONIC_SPELL_CHECKER
+#undef GET_MNEMONIC_SPELL_CHECKER
+
+static std::string LoongArchMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
+ const unsigned MaxEditDist = 2;
+ std::vector<StringRef> Candidates;
+ StringRef Prev = "";
+
+ // Find the appropriate table for this asm variant.
+ const MatchEntry *Start, *End;
+ switch (VariantID) {
+ default: llvm_unreachable("invalid variant!");
+ case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
+ }
+
+ for (auto I = Start; I < End; I++) {
+ // Ignore unsupported instructions.
+ const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
+ if ((FBS & RequiredFeatures) != RequiredFeatures)
+ continue;
+
+ StringRef T = I->getMnemonic();
+ // Avoid recomputing the edit distance for the same string.
+ if (T.equals(Prev))
+ continue;
+
+ Prev = T;
+ unsigned Dist = S.edit_distance(T, false, MaxEditDist);
+ if (Dist <= MaxEditDist)
+ Candidates.push_back(T);
+ }
+
+ if (Candidates.empty())
+ return "";
+
+ std::string Res = ", did you mean: ";
+ unsigned i = 0;
+ for (; i < Candidates.size() - 1; i++)
+ Res += Candidates[i].str() + ", ";
+ return Res + Candidates[i].str() + "?";
+}
+
+#endif // GET_MNEMONIC_SPELL_CHECKER
+
+
+#ifdef GET_MNEMONIC_CHECKER
+#undef GET_MNEMONIC_CHECKER
+
+static bool LoongArchCheckMnemonic(StringRef Mnemonic,
+ const FeatureBitset &AvailableFeatures,
+ unsigned VariantID) {
+ // Find the appropriate table for this asm variant.
+ const MatchEntry *Start, *End;
+ switch (VariantID) {
+ default: llvm_unreachable("invalid variant!");
+ case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
+ }
+
+ // Search the table.
+ auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
+
+ if (MnemonicRange.first == MnemonicRange.second)
+ return false;
+
+ for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
+ it != ie; ++it) {
+ const FeatureBitset &RequiredFeatures =
+ FeatureBitsets[it->RequiredFeaturesIdx];
+ if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
+ return true;
+ }
+ return false;
+}
+
+#endif // GET_MNEMONIC_CHECKER
+
diff --git a/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenAsmWriter.inc b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenAsmWriter.inc
new file mode 100644
index 0000000..f5808ee
--- /dev/null
+++ b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenAsmWriter.inc
@@ -0,0 +1,2204 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Assembly Writer Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/// getMnemonic - This method is automatically generated by tablegen
+/// from the instruction set description.
+std::pair<const char *, uint64_t> LoongArchInstPrinter::getMnemonic(const MCInst *MI) {
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Woverlength-strings"
+#endif
+ static const char AsmStrs[] = {
+ /* 0 */ "ld.b\t\0"
+ /* 6 */ "iocsrrd.b\t\0"
+ /* 17 */ "ldle.b\t\0"
+ /* 25 */ "stle.b\t\0"
+ /* 33 */ "iocsrwr.b\t\0"
+ /* 44 */ "ldgt.b\t\0"
+ /* 52 */ "stgt.b\t\0"
+ /* 60 */ "st.b\t\0"
+ /* 66 */ "ext.w.b\t\0"
+ /* 75 */ "ldx.b\t\0"
+ /* 82 */ "stx.b\t\0"
+ /* 89 */ "bitrev.4b\t\0"
+ /* 100 */ "bitrev.8b\t\0"
+ /* 111 */ "invtlb\t\0"
+ /* 119 */ "fmina.d\t\0"
+ /* 128 */ "sra.d\t\0"
+ /* 135 */ "fmaxa.d\t\0"
+ /* 144 */ "amadd_db.d\t\0"
+ /* 156 */ "amand_db.d\t\0"
+ /* 168 */ "ammin_db.d\t\0"
+ /* 180 */ "amswap_db.d\t\0"
+ /* 193 */ "amor_db.d\t\0"
+ /* 204 */ "amxor_db.d\t\0"
+ /* 216 */ "ammax_db.d\t\0"
+ /* 228 */ "fscaleb.d\t\0"
+ /* 239 */ "flogb.d\t\0"
+ /* 248 */ "fsub.d\t\0"
+ /* 256 */ "fmsub.d\t\0"
+ /* 265 */ "fnmsub.d\t\0"
+ /* 275 */ "revb.d\t\0"
+ /* 283 */ "sc.d\t\0"
+ /* 289 */ "fadd.d\t\0"
+ /* 297 */ "amadd.d\t\0"
+ /* 306 */ "fmadd.d\t\0"
+ /* 315 */ "fnmadd.d\t\0"
+ /* 325 */ "fld.d\t\0"
+ /* 332 */ "amand.d\t\0"
+ /* 341 */ "mod.d\t\0"
+ /* 348 */ "iocsrrd.d\t\0"
+ /* 359 */ "fcmp.cle.d\t\0"
+ /* 371 */ "fldle.d\t\0"
+ /* 380 */ "fcmp.sle.d\t\0"
+ /* 392 */ "asrtle.d\t\0"
+ /* 402 */ "fstle.d\t\0"
+ /* 411 */ "fcmp.cule.d\t\0"
+ /* 424 */ "fcmp.sule.d\t\0"
+ /* 437 */ "rdtime.d\t\0"
+ /* 447 */ "fcmp.cne.d\t\0"
+ /* 459 */ "fcmp.sne.d\t\0"
+ /* 471 */ "fcmp.cune.d\t\0"
+ /* 484 */ "fcmp.sune.d\t\0"
+ /* 497 */ "fcmp.caf.d\t\0"
+ /* 509 */ "fcmp.saf.d\t\0"
+ /* 521 */ "fneg.d\t\0"
+ /* 529 */ "mulh.d\t\0"
+ /* 537 */ "revh.d\t\0"
+ /* 545 */ "lu32i.d\t\0"
+ /* 554 */ "lu52i.d\t\0"
+ /* 563 */ "addu16i.d\t\0"
+ /* 574 */ "srai.d\t\0"
+ /* 582 */ "addi.d\t\0"
+ /* 590 */ "slli.d\t\0"
+ /* 598 */ "srli.d\t\0"
+ /* 606 */ "rotri.d\t\0"
+ /* 615 */ "bytepick.d\t\0"
+ /* 627 */ "bstrpick.d\t\0"
+ /* 639 */ "ftintrne.l.d\t\0"
+ /* 653 */ "ftintrm.l.d\t\0"
+ /* 666 */ "ftintrp.l.d\t\0"
+ /* 679 */ "ftint.l.d\t\0"
+ /* 690 */ "ftintrz.l.d\t\0"
+ /* 703 */ "sll.d\t\0"
+ /* 710 */ "srl.d\t\0"
+ /* 717 */ "alsl.d\t\0"
+ /* 725 */ "fmul.d\t\0"
+ /* 733 */ "fcopysign.d\t\0"
+ /* 746 */ "fmin.d\t\0"
+ /* 754 */ "ammin.d\t\0"
+ /* 763 */ "fcmp.cun.d\t\0"
+ /* 775 */ "fcmp.sun.d\t\0"
+ /* 787 */ "clo.d\t\0"
+ /* 794 */ "cto.d\t\0"
+ /* 801 */ "amswap.d\t\0"
+ /* 811 */ "frecip.d\t\0"
+ /* 821 */ "fcmp.ceq.d\t\0"
+ /* 833 */ "fcmp.seq.d\t\0"
+ /* 845 */ "fcmp.cueq.d\t\0"
+ /* 858 */ "fcmp.sueq.d\t\0"
+ /* 871 */ "movgr2fr.d\t\0"
+ /* 883 */ "movfr2gr.d\t\0"
+ /* 895 */ "fcmp.cor.d\t\0"
+ /* 907 */ "amor.d\t\0"
+ /* 915 */ "fcmp.sor.d\t\0"
+ /* 927 */ "amxor.d\t\0"
+ /* 936 */ "rotr.d\t\0"
+ /* 944 */ "ldptr.d\t\0"
+ /* 953 */ "stptr.d\t\0"
+ /* 962 */ "iocsrwr.d\t\0"
+ /* 973 */ "fcvt.s.d\t\0"
+ /* 983 */ "fabs.d\t\0"
+ /* 991 */ "bstrins.d\t\0"
+ /* 1002 */ "fclass.d\t\0"
+ /* 1012 */ "fldgt.d\t\0"
+ /* 1021 */ "asrtgt.d\t\0"
+ /* 1031 */ "fstgt.d\t\0"
+ /* 1040 */ "fcmp.clt.d\t\0"
+ /* 1052 */ "fcmp.slt.d\t\0"
+ /* 1064 */ "fcmp.cult.d\t\0"
+ /* 1077 */ "fcmp.sult.d\t\0"
+ /* 1090 */ "frint.d\t\0"
+ /* 1099 */ "fsqrt.d\t\0"
+ /* 1108 */ "frsqrt.d\t\0"
+ /* 1118 */ "fst.d\t\0"
+ /* 1125 */ "bitrev.d\t\0"
+ /* 1135 */ "fdiv.d\t\0"
+ /* 1143 */ "fmov.d\t\0"
+ /* 1151 */ "ftintrne.w.d\t\0"
+ /* 1165 */ "ftintrm.w.d\t\0"
+ /* 1178 */ "ftintrp.w.d\t\0"
+ /* 1191 */ "ftint.w.d\t\0"
+ /* 1202 */ "ftintrz.w.d\t\0"
+ /* 1215 */ "fmax.d\t\0"
+ /* 1223 */ "ammax.d\t\0"
+ /* 1232 */ "fldx.d\t\0"
+ /* 1240 */ "fstx.d\t\0"
+ /* 1248 */ "clz.d\t\0"
+ /* 1255 */ "ctz.d\t\0"
+ /* 1262 */ "la.tls.gd\t\0"
+ /* 1273 */ "la.tls.ld\t\0"
+ /* 1284 */ "preld\t\0"
+ /* 1291 */ "and\t\0"
+ /* 1296 */ "tlbrd\t\0"
+ /* 1303 */ "csrrd\t\0"
+ /* 1310 */ "bge\t\0"
+ /* 1315 */ "la.tls.ie\t\0"
+ /* 1326 */ "la.tls.le\t\0"
+ /* 1337 */ "idle\t\0"
+ /* 1343 */ "bne\t\0"
+ /* 1348 */ "ldpte\t\0"
+ /* 1355 */ "movfr2cf\t\0"
+ /* 1365 */ "movgr2cf\t\0"
+ /* 1375 */ "cpucfg\t\0"
+ /* 1383 */ "csrxchg\t\0"
+ /* 1392 */ "ld.h\t\0"
+ /* 1398 */ "iocsrrd.h\t\0"
+ /* 1409 */ "ldle.h\t\0"
+ /* 1417 */ "stle.h\t\0"
+ /* 1425 */ "iocsrwr.h\t\0"
+ /* 1436 */ "ldgt.h\t\0"
+ /* 1444 */ "stgt.h\t\0"
+ /* 1452 */ "st.h\t\0"
+ /* 1458 */ "ext.w.h\t\0"
+ /* 1467 */ "ldx.h\t\0"
+ /* 1474 */ "stx.h\t\0"
+ /* 1481 */ "revb.2h\t\0"
+ /* 1490 */ "revb.4h\t\0"
+ /* 1499 */ "tlbsrch\t\0"
+ /* 1508 */ "tlbflush\t\0"
+ /* 1518 */ "pcalau12i\t\0"
+ /* 1529 */ "pcaddu12i\t\0"
+ /* 1540 */ "pcaddu18i\t\0"
+ /* 1551 */ "pcaddi\t\0"
+ /* 1559 */ "andi\t\0"
+ /* 1565 */ "xori\t\0"
+ /* 1571 */ "slti\t\0"
+ /* 1577 */ "sltui\t\0"
+ /* 1584 */ "break\t\0"
+ /* 1591 */ "ffint.d.l\t\0"
+ /* 1602 */ "ffint.s.l\t\0"
+ /* 1613 */ "bl\t\0"
+ /* 1617 */ "dbcl\t\0"
+ /* 1623 */ "la.pcrel\t\0"
+ /* 1633 */ "fsel\t\0"
+ /* 1639 */ "syscall\t\0"
+ /* 1648 */ "tlbfill\t\0"
+ /* 1657 */ "jirl\t\0"
+ /* 1663 */ "andn\t\0"
+ /* 1669 */ "orn\t\0"
+ /* 1674 */ "ertn\t\0"
+ /* 1680 */ "cacop\t\0"
+ /* 1687 */ "beq\t\0"
+ /* 1692 */ "dbar\t\0"
+ /* 1698 */ "ibar\t\0"
+ /* 1704 */ "movcf2fr\t\0"
+ /* 1714 */ "movcf2gr\t\0"
+ /* 1724 */ "movfcsr2gr\t\0"
+ /* 1736 */ "lddir\t\0"
+ /* 1743 */ "tlbclr\t\0"
+ /* 1751 */ "nor\t\0"
+ /* 1756 */ "xor\t\0"
+ /* 1761 */ "movgr2fcsr\t\0"
+ /* 1773 */ "tlbwr\t\0"
+ /* 1780 */ "csrwr\t\0"
+ /* 1787 */ "fmina.s\t\0"
+ /* 1796 */ "fmaxa.s\t\0"
+ /* 1805 */ "fscaleb.s\t\0"
+ /* 1816 */ "flogb.s\t\0"
+ /* 1825 */ "fsub.s\t\0"
+ /* 1833 */ "fmsub.s\t\0"
+ /* 1842 */ "fnmsub.s\t\0"
+ /* 1852 */ "fcvt.d.s\t\0"
+ /* 1862 */ "fadd.s\t\0"
+ /* 1870 */ "fmadd.s\t\0"
+ /* 1879 */ "fnmadd.s\t\0"
+ /* 1889 */ "fld.s\t\0"
+ /* 1896 */ "fcmp.cle.s\t\0"
+ /* 1908 */ "fldle.s\t\0"
+ /* 1917 */ "fcmp.sle.s\t\0"
+ /* 1929 */ "fstle.s\t\0"
+ /* 1938 */ "fcmp.cule.s\t\0"
+ /* 1951 */ "fcmp.sule.s\t\0"
+ /* 1964 */ "fcmp.cne.s\t\0"
+ /* 1976 */ "fcmp.sne.s\t\0"
+ /* 1988 */ "fcmp.cune.s\t\0"
+ /* 2001 */ "fcmp.sune.s\t\0"
+ /* 2014 */ "fcmp.caf.s\t\0"
+ /* 2026 */ "fcmp.saf.s\t\0"
+ /* 2038 */ "fneg.s\t\0"
+ /* 2046 */ "ftintrne.l.s\t\0"
+ /* 2060 */ "ftintrm.l.s\t\0"
+ /* 2073 */ "ftintrp.l.s\t\0"
+ /* 2086 */ "ftint.l.s\t\0"
+ /* 2097 */ "ftintrz.l.s\t\0"
+ /* 2110 */ "fmul.s\t\0"
+ /* 2118 */ "fcopysign.s\t\0"
+ /* 2131 */ "fmin.s\t\0"
+ /* 2139 */ "fcmp.cun.s\t\0"
+ /* 2151 */ "fcmp.sun.s\t\0"
+ /* 2163 */ "frecip.s\t\0"
+ /* 2173 */ "fcmp.ceq.s\t\0"
+ /* 2185 */ "fcmp.seq.s\t\0"
+ /* 2197 */ "fcmp.cueq.s\t\0"
+ /* 2210 */ "fcmp.sueq.s\t\0"
+ /* 2223 */ "movfrh2gr.s\t\0"
+ /* 2236 */ "movfr2gr.s\t\0"
+ /* 2248 */ "fcmp.cor.s\t\0"
+ /* 2260 */ "fcmp.sor.s\t\0"
+ /* 2272 */ "fabs.s\t\0"
+ /* 2280 */ "fclass.s\t\0"
+ /* 2290 */ "fldgt.s\t\0"
+ /* 2299 */ "fstgt.s\t\0"
+ /* 2308 */ "fcmp.clt.s\t\0"
+ /* 2320 */ "fcmp.slt.s\t\0"
+ /* 2332 */ "fcmp.cult.s\t\0"
+ /* 2345 */ "fcmp.sult.s\t\0"
+ /* 2358 */ "frint.s\t\0"
+ /* 2367 */ "fsqrt.s\t\0"
+ /* 2376 */ "frsqrt.s\t\0"
+ /* 2386 */ "fst.s\t\0"
+ /* 2393 */ "fdiv.s\t\0"
+ /* 2401 */ "fmov.s\t\0"
+ /* 2409 */ "ftintrne.w.s\t\0"
+ /* 2423 */ "ftintrm.w.s\t\0"
+ /* 2436 */ "ftintrp.w.s\t\0"
+ /* 2449 */ "ftint.w.s\t\0"
+ /* 2460 */ "ftintrz.w.s\t\0"
+ /* 2473 */ "fmax.s\t\0"
+ /* 2481 */ "fldx.s\t\0"
+ /* 2489 */ "fstx.s\t\0"
+ /* 2497 */ "la.abs\t\0"
+ /* 2505 */ "blt\t\0"
+ /* 2510 */ "slt\t\0"
+ /* 2515 */ "la.got\t\0"
+ /* 2523 */ "ld.bu\t\0"
+ /* 2530 */ "ldx.bu\t\0"
+ /* 2538 */ "ammin_db.du\t\0"
+ /* 2551 */ "ammax_db.du\t\0"
+ /* 2564 */ "mod.du\t\0"
+ /* 2572 */ "mulh.du\t\0"
+ /* 2581 */ "ammin.du\t\0"
+ /* 2591 */ "div.du\t\0"
+ /* 2599 */ "ammax.du\t\0"
+ /* 2609 */ "bgeu\t\0"
+ /* 2615 */ "ld.hu\t\0"
+ /* 2622 */ "ldx.hu\t\0"
+ /* 2630 */ "bltu\t\0"
+ /* 2636 */ "sltu\t\0"
+ /* 2642 */ "ammin_db.wu\t\0"
+ /* 2655 */ "ammax_db.wu\t\0"
+ /* 2668 */ "mulw.d.wu\t\0"
+ /* 2679 */ "ld.wu\t\0"
+ /* 2686 */ "mod.wu\t\0"
+ /* 2694 */ "mulh.wu\t\0"
+ /* 2703 */ "alsl.wu\t\0"
+ /* 2712 */ "ammin.wu\t\0"
+ /* 2722 */ "div.wu\t\0"
+ /* 2730 */ "ammax.wu\t\0"
+ /* 2740 */ "ldx.wu\t\0"
+ /* 2748 */ "sra.w\t\0"
+ /* 2755 */ "crcc.w.b.w\t\0"
+ /* 2767 */ "crc.w.b.w\t\0"
+ /* 2778 */ "amadd_db.w\t\0"
+ /* 2790 */ "amand_db.w\t\0"
+ /* 2802 */ "ammin_db.w\t\0"
+ /* 2814 */ "amswap_db.w\t\0"
+ /* 2827 */ "amor_db.w\t\0"
+ /* 2838 */ "amxor_db.w\t\0"
+ /* 2850 */ "ammax_db.w\t\0"
+ /* 2862 */ "sub.w\t\0"
+ /* 2869 */ "sc.w\t\0"
+ /* 2875 */ "ffint.d.w\t\0"
+ /* 2886 */ "crcc.w.d.w\t\0"
+ /* 2898 */ "crc.w.d.w\t\0"
+ /* 2909 */ "mulw.d.w\t\0"
+ /* 2919 */ "amadd.w\t\0"
+ /* 2928 */ "ld.w\t\0"
+ /* 2934 */ "amand.w\t\0"
+ /* 2943 */ "mod.w\t\0"
+ /* 2950 */ "iocsrrd.w\t\0"
+ /* 2961 */ "ldle.w\t\0"
+ /* 2969 */ "stle.w\t\0"
+ /* 2977 */ "crcc.w.h.w\t\0"
+ /* 2989 */ "crc.w.h.w\t\0"
+ /* 3000 */ "rdtimeh.w\t\0"
+ /* 3011 */ "mulh.w\t\0"
+ /* 3019 */ "movgr2frh.w\t\0"
+ /* 3032 */ "lu12i.w\t\0"
+ /* 3041 */ "srai.w\t\0"
+ /* 3049 */ "addi.w\t\0"
+ /* 3057 */ "slli.w\t\0"
+ /* 3065 */ "srli.w\t\0"
+ /* 3073 */ "rotri.w\t\0"
+ /* 3082 */ "bytepick.w\t\0"
+ /* 3094 */ "bstrpick.w\t\0"
+ /* 3106 */ "rdtimel.w\t\0"
+ /* 3117 */ "sll.w\t\0"
+ /* 3124 */ "srl.w\t\0"
+ /* 3131 */ "alsl.w\t\0"
+ /* 3139 */ "mul.w\t\0"
+ /* 3146 */ "ammin.w\t\0"
+ /* 3155 */ "clo.w\t\0"
+ /* 3162 */ "cto.w\t\0"
+ /* 3169 */ "amswap.w\t\0"
+ /* 3179 */ "movgr2fr.w\t\0"
+ /* 3191 */ "amor.w\t\0"
+ /* 3199 */ "amxor.w\t\0"
+ /* 3208 */ "rotr.w\t\0"
+ /* 3216 */ "ldptr.w\t\0"
+ /* 3225 */ "stptr.w\t\0"
+ /* 3234 */ "iocsrwr.w\t\0"
+ /* 3245 */ "ffint.s.w\t\0"
+ /* 3256 */ "bstrins.w\t\0"
+ /* 3267 */ "ldgt.w\t\0"
+ /* 3275 */ "stgt.w\t\0"
+ /* 3283 */ "st.w\t\0"
+ /* 3289 */ "bitrev.w\t\0"
+ /* 3299 */ "div.w\t\0"
+ /* 3306 */ "crcc.w.w.w\t\0"
+ /* 3318 */ "crc.w.w.w\t\0"
+ /* 3329 */ "ammax.w\t\0"
+ /* 3338 */ "ldx.w\t\0"
+ /* 3345 */ "stx.w\t\0"
+ /* 3352 */ "clz.w\t\0"
+ /* 3359 */ "ctz.w\t\0"
+ /* 3366 */ "revb.2w\t\0"
+ /* 3375 */ "revh.2w\t\0"
+ /* 3384 */ "preldx\t\0"
+ /* 3392 */ "bnez\t\0"
+ /* 3398 */ "bcnez\t\0"
+ /* 3405 */ "masknez\t\0"
+ /* 3414 */ "beqz\t\0"
+ /* 3420 */ "bceqz\t\0"
+ /* 3427 */ "maskeqz\t\0"
+ /* 3436 */ "# XRay Function Patchable RET.\0"
+ /* 3467 */ "# XRay Typed Event Log.\0"
+ /* 3491 */ "# XRay Custom Event Log.\0"
+ /* 3516 */ "# XRay Function Enter.\0"
+ /* 3539 */ "# XRay Tail Call Exit.\0"
+ /* 3562 */ "# XRay Function Exit.\0"
+ /* 3584 */ "LIFETIME_END\0"
+ /* 3597 */ "PSEUDO_PROBE\0"
+ /* 3610 */ "BUNDLE\0"
+ /* 3617 */ "DBG_VALUE\0"
+ /* 3627 */ "DBG_INSTR_REF\0"
+ /* 3641 */ "DBG_PHI\0"
+ /* 3649 */ "DBG_LABEL\0"
+ /* 3659 */ "LIFETIME_START\0"
+ /* 3674 */ "DBG_VALUE_LIST\0"
+ /* 3689 */ "# FEntry call\0"
+};
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+ static const uint16_t OpInfo0[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // INLINEASM_BR
+ 0U, // CFI_INSTRUCTION
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // ANNOTATION_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 3618U, // DBG_VALUE
+ 3675U, // DBG_VALUE_LIST
+ 3628U, // DBG_INSTR_REF
+ 3642U, // DBG_PHI
+ 3650U, // DBG_LABEL
+ 0U, // REG_SEQUENCE
+ 0U, // COPY
+ 3611U, // BUNDLE
+ 3660U, // LIFETIME_START
+ 3585U, // LIFETIME_END
+ 3598U, // PSEUDO_PROBE
+ 0U, // ARITH_FENCE
+ 0U, // STACKMAP
+ 3690U, // FENTRY_CALL
+ 0U, // PATCHPOINT
+ 0U, // LOAD_STACK_GUARD
+ 0U, // PREALLOCATED_SETUP
+ 0U, // PREALLOCATED_ARG
+ 0U, // STATEPOINT
+ 0U, // LOCAL_ESCAPE
+ 0U, // FAULTING_OP
+ 0U, // PATCHABLE_OP
+ 3517U, // PATCHABLE_FUNCTION_ENTER
+ 3437U, // PATCHABLE_RET
+ 3563U, // PATCHABLE_FUNCTION_EXIT
+ 3540U, // PATCHABLE_TAIL_CALL
+ 3492U, // PATCHABLE_EVENT_CALL
+ 3468U, // PATCHABLE_TYPED_EVENT_CALL
+ 0U, // ICALL_BRANCH_FUNNEL
+ 0U, // MEMBARRIER
+ 0U, // G_ASSERT_SEXT
+ 0U, // G_ASSERT_ZEXT
+ 0U, // G_ASSERT_ALIGN
+ 0U, // G_ADD
+ 0U, // G_SUB
+ 0U, // G_MUL
+ 0U, // G_SDIV
+ 0U, // G_UDIV
+ 0U, // G_SREM
+ 0U, // G_UREM
+ 0U, // G_SDIVREM
+ 0U, // G_UDIVREM
+ 0U, // G_AND
+ 0U, // G_OR
+ 0U, // G_XOR
+ 0U, // G_IMPLICIT_DEF
+ 0U, // G_PHI
+ 0U, // G_FRAME_INDEX
+ 0U, // G_GLOBAL_VALUE
+ 0U, // G_EXTRACT
+ 0U, // G_UNMERGE_VALUES
+ 0U, // G_INSERT
+ 0U, // G_MERGE_VALUES
+ 0U, // G_BUILD_VECTOR
+ 0U, // G_BUILD_VECTOR_TRUNC
+ 0U, // G_CONCAT_VECTORS
+ 0U, // G_PTRTOINT
+ 0U, // G_INTTOPTR
+ 0U, // G_BITCAST
+ 0U, // G_FREEZE
+ 0U, // G_INTRINSIC_FPTRUNC_ROUND
+ 0U, // G_INTRINSIC_TRUNC
+ 0U, // G_INTRINSIC_ROUND
+ 0U, // G_INTRINSIC_LRINT
+ 0U, // G_INTRINSIC_ROUNDEVEN
+ 0U, // G_READCYCLECOUNTER
+ 0U, // G_LOAD
+ 0U, // G_SEXTLOAD
+ 0U, // G_ZEXTLOAD
+ 0U, // G_INDEXED_LOAD
+ 0U, // G_INDEXED_SEXTLOAD
+ 0U, // G_INDEXED_ZEXTLOAD
+ 0U, // G_STORE
+ 0U, // G_INDEXED_STORE
+ 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
+ 0U, // G_ATOMIC_CMPXCHG
+ 0U, // G_ATOMICRMW_XCHG
+ 0U, // G_ATOMICRMW_ADD
+ 0U, // G_ATOMICRMW_SUB
+ 0U, // G_ATOMICRMW_AND
+ 0U, // G_ATOMICRMW_NAND
+ 0U, // G_ATOMICRMW_OR
+ 0U, // G_ATOMICRMW_XOR
+ 0U, // G_ATOMICRMW_MAX
+ 0U, // G_ATOMICRMW_MIN
+ 0U, // G_ATOMICRMW_UMAX
+ 0U, // G_ATOMICRMW_UMIN
+ 0U, // G_ATOMICRMW_FADD
+ 0U, // G_ATOMICRMW_FSUB
+ 0U, // G_ATOMICRMW_FMAX
+ 0U, // G_ATOMICRMW_FMIN
+ 0U, // G_ATOMICRMW_UINC_WRAP
+ 0U, // G_ATOMICRMW_UDEC_WRAP
+ 0U, // G_FENCE
+ 0U, // G_BRCOND
+ 0U, // G_BRINDIRECT
+ 0U, // G_INVOKE_REGION_START
+ 0U, // G_INTRINSIC
+ 0U, // G_INTRINSIC_W_SIDE_EFFECTS
+ 0U, // G_ANYEXT
+ 0U, // G_TRUNC
+ 0U, // G_CONSTANT
+ 0U, // G_FCONSTANT
+ 0U, // G_VASTART
+ 0U, // G_VAARG
+ 0U, // G_SEXT
+ 0U, // G_SEXT_INREG
+ 0U, // G_ZEXT
+ 0U, // G_SHL
+ 0U, // G_LSHR
+ 0U, // G_ASHR
+ 0U, // G_FSHL
+ 0U, // G_FSHR
+ 0U, // G_ROTR
+ 0U, // G_ROTL
+ 0U, // G_ICMP
+ 0U, // G_FCMP
+ 0U, // G_SELECT
+ 0U, // G_UADDO
+ 0U, // G_UADDE
+ 0U, // G_USUBO
+ 0U, // G_USUBE
+ 0U, // G_SADDO
+ 0U, // G_SADDE
+ 0U, // G_SSUBO
+ 0U, // G_SSUBE
+ 0U, // G_UMULO
+ 0U, // G_SMULO
+ 0U, // G_UMULH
+ 0U, // G_SMULH
+ 0U, // G_UADDSAT
+ 0U, // G_SADDSAT
+ 0U, // G_USUBSAT
+ 0U, // G_SSUBSAT
+ 0U, // G_USHLSAT
+ 0U, // G_SSHLSAT
+ 0U, // G_SMULFIX
+ 0U, // G_UMULFIX
+ 0U, // G_SMULFIXSAT
+ 0U, // G_UMULFIXSAT
+ 0U, // G_SDIVFIX
+ 0U, // G_UDIVFIX
+ 0U, // G_SDIVFIXSAT
+ 0U, // G_UDIVFIXSAT
+ 0U, // G_FADD
+ 0U, // G_FSUB
+ 0U, // G_FMUL
+ 0U, // G_FMA
+ 0U, // G_FMAD
+ 0U, // G_FDIV
+ 0U, // G_FREM
+ 0U, // G_FPOW
+ 0U, // G_FPOWI
+ 0U, // G_FEXP
+ 0U, // G_FEXP2
+ 0U, // G_FLOG
+ 0U, // G_FLOG2
+ 0U, // G_FLOG10
+ 0U, // G_FNEG
+ 0U, // G_FPEXT
+ 0U, // G_FPTRUNC
+ 0U, // G_FPTOSI
+ 0U, // G_FPTOUI
+ 0U, // G_SITOFP
+ 0U, // G_UITOFP
+ 0U, // G_FABS
+ 0U, // G_FCOPYSIGN
+ 0U, // G_IS_FPCLASS
+ 0U, // G_FCANONICALIZE
+ 0U, // G_FMINNUM
+ 0U, // G_FMAXNUM
+ 0U, // G_FMINNUM_IEEE
+ 0U, // G_FMAXNUM_IEEE
+ 0U, // G_FMINIMUM
+ 0U, // G_FMAXIMUM
+ 0U, // G_PTR_ADD
+ 0U, // G_PTRMASK
+ 0U, // G_SMIN
+ 0U, // G_SMAX
+ 0U, // G_UMIN
+ 0U, // G_UMAX
+ 0U, // G_ABS
+ 0U, // G_LROUND
+ 0U, // G_LLROUND
+ 0U, // G_BR
+ 0U, // G_BRJT
+ 0U, // G_INSERT_VECTOR_ELT
+ 0U, // G_EXTRACT_VECTOR_ELT
+ 0U, // G_SHUFFLE_VECTOR
+ 0U, // G_CTTZ
+ 0U, // G_CTTZ_ZERO_UNDEF
+ 0U, // G_CTLZ
+ 0U, // G_CTLZ_ZERO_UNDEF
+ 0U, // G_CTPOP
+ 0U, // G_BSWAP
+ 0U, // G_BITREVERSE
+ 0U, // G_FCEIL
+ 0U, // G_FCOS
+ 0U, // G_FSIN
+ 0U, // G_FSQRT
+ 0U, // G_FFLOOR
+ 0U, // G_FRINT
+ 0U, // G_FNEARBYINT
+ 0U, // G_ADDRSPACE_CAST
+ 0U, // G_BLOCK_ADDR
+ 0U, // G_JUMP_TABLE
+ 0U, // G_DYN_STACKALLOC
+ 0U, // G_STRICT_FADD
+ 0U, // G_STRICT_FSUB
+ 0U, // G_STRICT_FMUL
+ 0U, // G_STRICT_FDIV
+ 0U, // G_STRICT_FREM
+ 0U, // G_STRICT_FMA
+ 0U, // G_STRICT_FSQRT
+ 0U, // G_READ_REGISTER
+ 0U, // G_WRITE_REGISTER
+ 0U, // G_MEMCPY
+ 0U, // G_MEMCPY_INLINE
+ 0U, // G_MEMMOVE
+ 0U, // G_MEMSET
+ 0U, // G_BZERO
+ 0U, // G_VECREDUCE_SEQ_FADD
+ 0U, // G_VECREDUCE_SEQ_FMUL
+ 0U, // G_VECREDUCE_FADD
+ 0U, // G_VECREDUCE_FMUL
+ 0U, // G_VECREDUCE_FMAX
+ 0U, // G_VECREDUCE_FMIN
+ 0U, // G_VECREDUCE_ADD
+ 0U, // G_VECREDUCE_MUL
+ 0U, // G_VECREDUCE_AND
+ 0U, // G_VECREDUCE_OR
+ 0U, // G_VECREDUCE_XOR
+ 0U, // G_VECREDUCE_SMAX
+ 0U, // G_VECREDUCE_SMIN
+ 0U, // G_VECREDUCE_UMAX
+ 0U, // G_VECREDUCE_UMIN
+ 0U, // G_SBFX
+ 0U, // G_UBFX
+ 5U, // ADJCALLSTACKDOWN
+ 5U, // ADJCALLSTACKUP
+ 5U, // PseudoAtomicLoadAdd32
+ 5U, // PseudoAtomicLoadAnd32
+ 5U, // PseudoAtomicLoadNand32
+ 5U, // PseudoAtomicLoadNand64
+ 5U, // PseudoAtomicLoadOr32
+ 5U, // PseudoAtomicLoadSub32
+ 5U, // PseudoAtomicLoadXor32
+ 5U, // PseudoAtomicStoreD
+ 5U, // PseudoAtomicStoreW
+ 5U, // PseudoAtomicSwap32
+ 5U, // PseudoBR
+ 5U, // PseudoBRIND
+ 5U, // PseudoB_TAIL
+ 5U, // PseudoCALL
+ 5U, // PseudoCALLIndirect
+ 5U, // PseudoCmpXchg32
+ 5U, // PseudoCmpXchg64
+ 5U, // PseudoJIRL_CALL
+ 5U, // PseudoJIRL_TAIL
+ 6594U, // PseudoLA_ABS
+ 39362U, // PseudoLA_ABS_LARGE
+ 6612U, // PseudoLA_GOT
+ 6612U, // PseudoLA_GOT_LARGE
+ 5720U, // PseudoLA_PCREL
+ 5720U, // PseudoLA_PCREL_LARGE
+ 5359U, // PseudoLA_TLS_GD
+ 5359U, // PseudoLA_TLS_GD_LARGE
+ 5412U, // PseudoLA_TLS_IE
+ 5412U, // PseudoLA_TLS_IE_LARGE
+ 5370U, // PseudoLA_TLS_LD
+ 5370U, // PseudoLA_TLS_LD_LARGE
+ 5423U, // PseudoLA_TLS_LE
+ 5U, // PseudoLD_CFR
+ 4689U, // PseudoLI_D
+ 7156U, // PseudoLI_W
+ 5U, // PseudoMaskedAtomicLoadAdd32
+ 5U, // PseudoMaskedAtomicLoadMax32
+ 5U, // PseudoMaskedAtomicLoadMin32
+ 5U, // PseudoMaskedAtomicLoadNand32
+ 5U, // PseudoMaskedAtomicLoadSub32
+ 5U, // PseudoMaskedAtomicLoadUMax32
+ 5U, // PseudoMaskedAtomicLoadUMin32
+ 5U, // PseudoMaskedAtomicSwap32
+ 5U, // PseudoMaskedCmpXchg32
+ 5U, // PseudoRET
+ 5U, // PseudoST_CFR
+ 5U, // PseudoTAIL
+ 5U, // PseudoTAILIndirect
+ 5U, // PseudoUNIMP
+ 5U, // RDFCSR
+ 5U, // WRFCSR
+ 4679U, // ADDI_D
+ 7146U, // ADDI_W
+ 4660U, // ADDU16I_D
+ 4387U, // ADD_D
+ 7018U, // ADD_W
+ 4814U, // ALSL_D
+ 7228U, // ALSL_W
+ 6800U, // ALSL_WU
+ 4394U, // AMADD_D
+ 4241U, // AMADD_DB_D
+ 6875U, // AMADD_DB_W
+ 7016U, // AMADD_W
+ 4429U, // AMAND_D
+ 4253U, // AMAND_DB_D
+ 6887U, // AMAND_DB_W
+ 7031U, // AMAND_W
+ 5320U, // AMMAX_D
+ 4313U, // AMMAX_DB_D
+ 6648U, // AMMAX_DB_DU
+ 6947U, // AMMAX_DB_W
+ 6752U, // AMMAX_DB_WU
+ 6696U, // AMMAX_DU
+ 7426U, // AMMAX_W
+ 6827U, // AMMAX_WU
+ 4851U, // AMMIN_D
+ 4265U, // AMMIN_DB_D
+ 6635U, // AMMIN_DB_DU
+ 6899U, // AMMIN_DB_W
+ 6739U, // AMMIN_DB_WU
+ 6678U, // AMMIN_DU
+ 7243U, // AMMIN_W
+ 6809U, // AMMIN_WU
+ 5004U, // AMOR_D
+ 4290U, // AMOR_DB_D
+ 6924U, // AMOR_DB_W
+ 7288U, // AMOR_W
+ 4898U, // AMSWAP_D
+ 4277U, // AMSWAP_DB_D
+ 6911U, // AMSWAP_DB_W
+ 7266U, // AMSWAP_W
+ 5024U, // AMXOR_D
+ 4301U, // AMXOR_DB_D
+ 6935U, // AMXOR_DB_W
+ 7296U, // AMXOR_W
+ 5388U, // AND
+ 5656U, // ANDI
+ 5760U, // ANDN
+ 5118U, // ASRTGT_D
+ 4489U, // ASRTLE_D
+ 20484U, // B
+ 7517U, // BCEQZ
+ 7495U, // BCNEZ
+ 5784U, // BEQ
+ 7511U, // BEQZ
+ 5407U, // BGE
+ 6706U, // BGEU
+ 4186U, // BITREV_4B
+ 4197U, // BITREV_8B
+ 5222U, // BITREV_D
+ 7386U, // BITREV_W
+ 22094U, // BL
+ 6602U, // BLT
+ 6727U, // BLTU
+ 5440U, // BNE
+ 7489U, // BNEZ
+ 22065U, // BREAK
+ 9184U, // BSTRINS_D
+ 11449U, // BSTRINS_W
+ 4724U, // BSTRPICK_D
+ 7191U, // BSTRPICK_W
+ 4712U, // BYTEPICK_D
+ 7179U, // BYTEPICK_W
+ 5777U, // CACOP
+ 4884U, // CLO_D
+ 7252U, // CLO_W
+ 5345U, // CLZ_D
+ 7449U, // CLZ_W
+ 5472U, // CPUCFG
+ 6852U, // CRCC_W_B_W
+ 6983U, // CRCC_W_D_W
+ 7074U, // CRCC_W_H_W
+ 7403U, // CRCC_W_W_W
+ 6864U, // CRC_W_B_W
+ 6995U, // CRC_W_D_W
+ 7086U, // CRC_W_H_W
+ 7415U, // CRC_W_W_W
+ 5400U, // CSRRD
+ 26357U, // CSRWR
+ 9576U, // CSRXCHG
+ 4891U, // CTO_D
+ 7259U, // CTO_W
+ 5352U, // CTZ_D
+ 7456U, // CTZ_W
+ 22173U, // DBAR
+ 22098U, // DBCL
+ 5233U, // DIV_D
+ 6688U, // DIV_DU
+ 7396U, // DIV_W
+ 6819U, // DIV_WU
+ 1675U, // ERTN
+ 4163U, // EXT_W_B
+ 5555U, // EXT_W_H
+ 5080U, // FABS_D
+ 6369U, // FABS_S
+ 4386U, // FADD_D
+ 5959U, // FADD_S
+ 5099U, // FCLASS_D
+ 6377U, // FCLASS_S
+ 4594U, // FCMP_CAF_D
+ 6111U, // FCMP_CAF_S
+ 4918U, // FCMP_CEQ_D
+ 6270U, // FCMP_CEQ_S
+ 4456U, // FCMP_CLE_D
+ 5993U, // FCMP_CLE_S
+ 5137U, // FCMP_CLT_D
+ 6405U, // FCMP_CLT_S
+ 4544U, // FCMP_CNE_D
+ 6061U, // FCMP_CNE_S
+ 4992U, // FCMP_COR_D
+ 6345U, // FCMP_COR_S
+ 4942U, // FCMP_CUEQ_D
+ 6294U, // FCMP_CUEQ_S
+ 4508U, // FCMP_CULE_D
+ 6035U, // FCMP_CULE_S
+ 5161U, // FCMP_CULT_D
+ 6429U, // FCMP_CULT_S
+ 4568U, // FCMP_CUNE_D
+ 6085U, // FCMP_CUNE_S
+ 4860U, // FCMP_CUN_D
+ 6236U, // FCMP_CUN_S
+ 4606U, // FCMP_SAF_D
+ 6123U, // FCMP_SAF_S
+ 4930U, // FCMP_SEQ_D
+ 6282U, // FCMP_SEQ_S
+ 4477U, // FCMP_SLE_D
+ 6014U, // FCMP_SLE_S
+ 5149U, // FCMP_SLT_D
+ 6417U, // FCMP_SLT_S
+ 4556U, // FCMP_SNE_D
+ 6073U, // FCMP_SNE_S
+ 5012U, // FCMP_SOR_D
+ 6357U, // FCMP_SOR_S
+ 4955U, // FCMP_SUEQ_D
+ 6307U, // FCMP_SUEQ_S
+ 4521U, // FCMP_SULE_D
+ 6048U, // FCMP_SULE_S
+ 5174U, // FCMP_SULT_D
+ 6442U, // FCMP_SULT_S
+ 4581U, // FCMP_SUNE_D
+ 6098U, // FCMP_SUNE_S
+ 4872U, // FCMP_SUN_D
+ 6248U, // FCMP_SUN_S
+ 4830U, // FCOPYSIGN_D
+ 6215U, // FCOPYSIGN_S
+ 5949U, // FCVT_D_S
+ 5070U, // FCVT_S_D
+ 5232U, // FDIV_D
+ 6490U, // FDIV_S
+ 5688U, // FFINT_D_L
+ 6972U, // FFINT_D_W
+ 5699U, // FFINT_S_L
+ 7342U, // FFINT_S_W
+ 5109U, // FLDGT_D
+ 6387U, // FLDGT_S
+ 4468U, // FLDLE_D
+ 6005U, // FLDLE_S
+ 5329U, // FLDX_D
+ 6578U, // FLDX_S
+ 4422U, // FLD_D
+ 5986U, // FLD_S
+ 4336U, // FLOGB_D
+ 5913U, // FLOGB_S
+ 4403U, // FMADD_D
+ 5967U, // FMADD_S
+ 4232U, // FMAXA_D
+ 5893U, // FMAXA_S
+ 5312U, // FMAX_D
+ 6570U, // FMAX_S
+ 4216U, // FMINA_D
+ 5884U, // FMINA_S
+ 4843U, // FMIN_D
+ 6228U, // FMIN_S
+ 5240U, // FMOV_D
+ 6498U, // FMOV_S
+ 4353U, // FMSUB_D
+ 5930U, // FMSUB_S
+ 4822U, // FMUL_D
+ 6207U, // FMUL_S
+ 4618U, // FNEG_D
+ 6135U, // FNEG_S
+ 4412U, // FNMADD_D
+ 5976U, // FNMADD_S
+ 4362U, // FNMSUB_D
+ 5939U, // FNMSUB_S
+ 4908U, // FRECIP_D
+ 6260U, // FRECIP_S
+ 5187U, // FRINT_D
+ 6455U, // FRINT_S
+ 5205U, // FRSQRT_D
+ 6473U, // FRSQRT_S
+ 4325U, // FSCALEB_D
+ 5902U, // FSCALEB_S
+ 5730U, // FSEL_D
+ 5730U, // FSEL_S
+ 5196U, // FSQRT_D
+ 6464U, // FSQRT_S
+ 5128U, // FSTGT_D
+ 6396U, // FSTGT_S
+ 4499U, // FSTLE_D
+ 6026U, // FSTLE_S
+ 5337U, // FSTX_D
+ 6586U, // FSTX_S
+ 5215U, // FST_D
+ 6483U, // FST_S
+ 4345U, // FSUB_D
+ 5922U, // FSUB_S
+ 4750U, // FTINTRM_L_D
+ 6157U, // FTINTRM_L_S
+ 5262U, // FTINTRM_W_D
+ 6520U, // FTINTRM_W_S
+ 4736U, // FTINTRNE_L_D
+ 6143U, // FTINTRNE_L_S
+ 5248U, // FTINTRNE_W_D
+ 6506U, // FTINTRNE_W_S
+ 4763U, // FTINTRP_L_D
+ 6170U, // FTINTRP_L_S
+ 5275U, // FTINTRP_W_D
+ 6533U, // FTINTRP_W_S
+ 4787U, // FTINTRZ_L_D
+ 6194U, // FTINTRZ_L_S
+ 5299U, // FTINTRZ_W_D
+ 6557U, // FTINTRZ_W_S
+ 4776U, // FTINT_L_D
+ 6183U, // FTINT_L_S
+ 5288U, // FTINT_W_D
+ 6546U, // FTINT_W_S
+ 22179U, // IBAR
+ 21818U, // IDLE
+ 12400U, // INVTLB
+ 4103U, // IOCSRRD_B
+ 4445U, // IOCSRRD_D
+ 5495U, // IOCSRRD_H
+ 7047U, // IOCSRRD_W
+ 4130U, // IOCSRWR_B
+ 5059U, // IOCSRWR_D
+ 5522U, // IOCSRWR_H
+ 7331U, // IOCSRWR_W
+ 5754U, // JIRL
+ 5833U, // LDDIR
+ 4141U, // LDGT_B
+ 5110U, // LDGT_D
+ 5533U, // LDGT_H
+ 7364U, // LDGT_W
+ 4114U, // LDLE_B
+ 4469U, // LDLE_D
+ 5506U, // LDLE_H
+ 7058U, // LDLE_W
+ 5445U, // LDPTE
+ 5041U, // LDPTR_D
+ 7313U, // LDPTR_W
+ 4172U, // LDX_B
+ 6627U, // LDX_BU
+ 5330U, // LDX_D
+ 5564U, // LDX_H
+ 6719U, // LDX_HU
+ 7435U, // LDX_W
+ 6837U, // LDX_WU
+ 4097U, // LD_B
+ 6620U, // LD_BU
+ 4423U, // LD_D
+ 5489U, // LD_H
+ 6712U, // LD_HU
+ 7025U, // LD_W
+ 6776U, // LD_WU
+ 4801U, // LL_D
+ 7215U, // LL_W
+ 7129U, // LU12I_W
+ 25122U, // LU32I_D
+ 4651U, // LU52I_D
+ 7524U, // MASKEQZ
+ 7502U, // MASKNEZ
+ 4438U, // MOD_D
+ 6661U, // MOD_DU
+ 7040U, // MOD_W
+ 6783U, // MOD_WU
+ 5801U, // MOVCF2FR_S
+ 5811U, // MOVCF2GR
+ 5821U, // MOVFCSR2GR
+ 5452U, // MOVFR2CF_S
+ 4980U, // MOVFR2GR_D
+ 6333U, // MOVFR2GR_S
+ 6333U, // MOVFR2GR_S_64
+ 6320U, // MOVFRH2GR_S
+ 5462U, // MOVGR2CF
+ 5858U, // MOVGR2FCSR
+ 27596U, // MOVGR2FRH_W
+ 4968U, // MOVGR2FR_D
+ 7276U, // MOVGR2FR_W
+ 7276U, // MOVGR2FR_W_64
+ 4626U, // MULH_D
+ 6669U, // MULH_DU
+ 7108U, // MULH_W
+ 6791U, // MULH_WU
+ 7006U, // MULW_D_W
+ 6765U, // MULW_D_WU
+ 4823U, // MUL_D
+ 7236U, // MUL_W
+ 5848U, // NOR
+ 5849U, // OR
+ 5663U, // ORI
+ 5766U, // ORN
+ 5648U, // PCADDI
+ 5626U, // PCADDU12I
+ 5637U, // PCADDU18I
+ 5615U, // PCALAU12I
+ 5381U, // PRELD
+ 7481U, // PRELDX
+ 7097U, // RDTIMEH_W
+ 7203U, // RDTIMEL_W
+ 4534U, // RDTIME_D
+ 5578U, // REVB_2H
+ 7463U, // REVB_2W
+ 5587U, // REVB_4H
+ 4372U, // REVB_D
+ 7472U, // REVH_2W
+ 4634U, // REVH_D
+ 4703U, // ROTRI_D
+ 7170U, // ROTRI_W
+ 5033U, // ROTR_D
+ 7305U, // ROTR_W
+ 8476U, // SC_D
+ 11062U, // SC_W
+ 4687U, // SLLI_D
+ 7154U, // SLLI_W
+ 4800U, // SLL_D
+ 7214U, // SLL_W
+ 6607U, // SLT
+ 5668U, // SLTI
+ 6733U, // SLTU
+ 5674U, // SLTUI
+ 4671U, // SRAI_D
+ 7138U, // SRAI_W
+ 4225U, // SRA_D
+ 6845U, // SRA_W
+ 4695U, // SRLI_D
+ 7162U, // SRLI_W
+ 4807U, // SRL_D
+ 7221U, // SRL_W
+ 4149U, // STGT_B
+ 5129U, // STGT_D
+ 5541U, // STGT_H
+ 7372U, // STGT_W
+ 4122U, // STLE_B
+ 4500U, // STLE_D
+ 5514U, // STLE_H
+ 7066U, // STLE_W
+ 5050U, // STPTR_D
+ 7322U, // STPTR_W
+ 4179U, // STX_B
+ 5338U, // STX_D
+ 5571U, // STX_H
+ 7442U, // STX_W
+ 4157U, // ST_B
+ 5216U, // ST_D
+ 5549U, // ST_H
+ 7380U, // ST_W
+ 4346U, // SUB_D
+ 6959U, // SUB_W
+ 22120U, // SYSCALL
+ 1744U, // TLBCLR
+ 1649U, // TLBFILL
+ 1509U, // TLBFLUSH
+ 1297U, // TLBRD
+ 1500U, // TLBSRCH
+ 1774U, // TLBWR
+ 5853U, // XOR
+ 5662U, // XORI
+ };
+
+ static const uint8_t OpInfo1[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // INLINEASM_BR
+ 0U, // CFI_INSTRUCTION
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // ANNOTATION_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 0U, // DBG_VALUE
+ 0U, // DBG_VALUE_LIST
+ 0U, // DBG_INSTR_REF
+ 0U, // DBG_PHI
+ 0U, // DBG_LABEL
+ 0U, // REG_SEQUENCE
+ 0U, // COPY
+ 0U, // BUNDLE
+ 0U, // LIFETIME_START
+ 0U, // LIFETIME_END
+ 0U, // PSEUDO_PROBE
+ 0U, // ARITH_FENCE
+ 0U, // STACKMAP
+ 0U, // FENTRY_CALL
+ 0U, // PATCHPOINT
+ 0U, // LOAD_STACK_GUARD
+ 0U, // PREALLOCATED_SETUP
+ 0U, // PREALLOCATED_ARG
+ 0U, // STATEPOINT
+ 0U, // LOCAL_ESCAPE
+ 0U, // FAULTING_OP
+ 0U, // PATCHABLE_OP
+ 0U, // PATCHABLE_FUNCTION_ENTER
+ 0U, // PATCHABLE_RET
+ 0U, // PATCHABLE_FUNCTION_EXIT
+ 0U, // PATCHABLE_TAIL_CALL
+ 0U, // PATCHABLE_EVENT_CALL
+ 0U, // PATCHABLE_TYPED_EVENT_CALL
+ 0U, // ICALL_BRANCH_FUNNEL
+ 0U, // MEMBARRIER
+ 0U, // G_ASSERT_SEXT
+ 0U, // G_ASSERT_ZEXT
+ 0U, // G_ASSERT_ALIGN
+ 0U, // G_ADD
+ 0U, // G_SUB
+ 0U, // G_MUL
+ 0U, // G_SDIV
+ 0U, // G_UDIV
+ 0U, // G_SREM
+ 0U, // G_UREM
+ 0U, // G_SDIVREM
+ 0U, // G_UDIVREM
+ 0U, // G_AND
+ 0U, // G_OR
+ 0U, // G_XOR
+ 0U, // G_IMPLICIT_DEF
+ 0U, // G_PHI
+ 0U, // G_FRAME_INDEX
+ 0U, // G_GLOBAL_VALUE
+ 0U, // G_EXTRACT
+ 0U, // G_UNMERGE_VALUES
+ 0U, // G_INSERT
+ 0U, // G_MERGE_VALUES
+ 0U, // G_BUILD_VECTOR
+ 0U, // G_BUILD_VECTOR_TRUNC
+ 0U, // G_CONCAT_VECTORS
+ 0U, // G_PTRTOINT
+ 0U, // G_INTTOPTR
+ 0U, // G_BITCAST
+ 0U, // G_FREEZE
+ 0U, // G_INTRINSIC_FPTRUNC_ROUND
+ 0U, // G_INTRINSIC_TRUNC
+ 0U, // G_INTRINSIC_ROUND
+ 0U, // G_INTRINSIC_LRINT
+ 0U, // G_INTRINSIC_ROUNDEVEN
+ 0U, // G_READCYCLECOUNTER
+ 0U, // G_LOAD
+ 0U, // G_SEXTLOAD
+ 0U, // G_ZEXTLOAD
+ 0U, // G_INDEXED_LOAD
+ 0U, // G_INDEXED_SEXTLOAD
+ 0U, // G_INDEXED_ZEXTLOAD
+ 0U, // G_STORE
+ 0U, // G_INDEXED_STORE
+ 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
+ 0U, // G_ATOMIC_CMPXCHG
+ 0U, // G_ATOMICRMW_XCHG
+ 0U, // G_ATOMICRMW_ADD
+ 0U, // G_ATOMICRMW_SUB
+ 0U, // G_ATOMICRMW_AND
+ 0U, // G_ATOMICRMW_NAND
+ 0U, // G_ATOMICRMW_OR
+ 0U, // G_ATOMICRMW_XOR
+ 0U, // G_ATOMICRMW_MAX
+ 0U, // G_ATOMICRMW_MIN
+ 0U, // G_ATOMICRMW_UMAX
+ 0U, // G_ATOMICRMW_UMIN
+ 0U, // G_ATOMICRMW_FADD
+ 0U, // G_ATOMICRMW_FSUB
+ 0U, // G_ATOMICRMW_FMAX
+ 0U, // G_ATOMICRMW_FMIN
+ 0U, // G_ATOMICRMW_UINC_WRAP
+ 0U, // G_ATOMICRMW_UDEC_WRAP
+ 0U, // G_FENCE
+ 0U, // G_BRCOND
+ 0U, // G_BRINDIRECT
+ 0U, // G_INVOKE_REGION_START
+ 0U, // G_INTRINSIC
+ 0U, // G_INTRINSIC_W_SIDE_EFFECTS
+ 0U, // G_ANYEXT
+ 0U, // G_TRUNC
+ 0U, // G_CONSTANT
+ 0U, // G_FCONSTANT
+ 0U, // G_VASTART
+ 0U, // G_VAARG
+ 0U, // G_SEXT
+ 0U, // G_SEXT_INREG
+ 0U, // G_ZEXT
+ 0U, // G_SHL
+ 0U, // G_LSHR
+ 0U, // G_ASHR
+ 0U, // G_FSHL
+ 0U, // G_FSHR
+ 0U, // G_ROTR
+ 0U, // G_ROTL
+ 0U, // G_ICMP
+ 0U, // G_FCMP
+ 0U, // G_SELECT
+ 0U, // G_UADDO
+ 0U, // G_UADDE
+ 0U, // G_USUBO
+ 0U, // G_USUBE
+ 0U, // G_SADDO
+ 0U, // G_SADDE
+ 0U, // G_SSUBO
+ 0U, // G_SSUBE
+ 0U, // G_UMULO
+ 0U, // G_SMULO
+ 0U, // G_UMULH
+ 0U, // G_SMULH
+ 0U, // G_UADDSAT
+ 0U, // G_SADDSAT
+ 0U, // G_USUBSAT
+ 0U, // G_SSUBSAT
+ 0U, // G_USHLSAT
+ 0U, // G_SSHLSAT
+ 0U, // G_SMULFIX
+ 0U, // G_UMULFIX
+ 0U, // G_SMULFIXSAT
+ 0U, // G_UMULFIXSAT
+ 0U, // G_SDIVFIX
+ 0U, // G_UDIVFIX
+ 0U, // G_SDIVFIXSAT
+ 0U, // G_UDIVFIXSAT
+ 0U, // G_FADD
+ 0U, // G_FSUB
+ 0U, // G_FMUL
+ 0U, // G_FMA
+ 0U, // G_FMAD
+ 0U, // G_FDIV
+ 0U, // G_FREM
+ 0U, // G_FPOW
+ 0U, // G_FPOWI
+ 0U, // G_FEXP
+ 0U, // G_FEXP2
+ 0U, // G_FLOG
+ 0U, // G_FLOG2
+ 0U, // G_FLOG10
+ 0U, // G_FNEG
+ 0U, // G_FPEXT
+ 0U, // G_FPTRUNC
+ 0U, // G_FPTOSI
+ 0U, // G_FPTOUI
+ 0U, // G_SITOFP
+ 0U, // G_UITOFP
+ 0U, // G_FABS
+ 0U, // G_FCOPYSIGN
+ 0U, // G_IS_FPCLASS
+ 0U, // G_FCANONICALIZE
+ 0U, // G_FMINNUM
+ 0U, // G_FMAXNUM
+ 0U, // G_FMINNUM_IEEE
+ 0U, // G_FMAXNUM_IEEE
+ 0U, // G_FMINIMUM
+ 0U, // G_FMAXIMUM
+ 0U, // G_PTR_ADD
+ 0U, // G_PTRMASK
+ 0U, // G_SMIN
+ 0U, // G_SMAX
+ 0U, // G_UMIN
+ 0U, // G_UMAX
+ 0U, // G_ABS
+ 0U, // G_LROUND
+ 0U, // G_LLROUND
+ 0U, // G_BR
+ 0U, // G_BRJT
+ 0U, // G_INSERT_VECTOR_ELT
+ 0U, // G_EXTRACT_VECTOR_ELT
+ 0U, // G_SHUFFLE_VECTOR
+ 0U, // G_CTTZ
+ 0U, // G_CTTZ_ZERO_UNDEF
+ 0U, // G_CTLZ
+ 0U, // G_CTLZ_ZERO_UNDEF
+ 0U, // G_CTPOP
+ 0U, // G_BSWAP
+ 0U, // G_BITREVERSE
+ 0U, // G_FCEIL
+ 0U, // G_FCOS
+ 0U, // G_FSIN
+ 0U, // G_FSQRT
+ 0U, // G_FFLOOR
+ 0U, // G_FRINT
+ 0U, // G_FNEARBYINT
+ 0U, // G_ADDRSPACE_CAST
+ 0U, // G_BLOCK_ADDR
+ 0U, // G_JUMP_TABLE
+ 0U, // G_DYN_STACKALLOC
+ 0U, // G_STRICT_FADD
+ 0U, // G_STRICT_FSUB
+ 0U, // G_STRICT_FMUL
+ 0U, // G_STRICT_FDIV
+ 0U, // G_STRICT_FREM
+ 0U, // G_STRICT_FMA
+ 0U, // G_STRICT_FSQRT
+ 0U, // G_READ_REGISTER
+ 0U, // G_WRITE_REGISTER
+ 0U, // G_MEMCPY
+ 0U, // G_MEMCPY_INLINE
+ 0U, // G_MEMMOVE
+ 0U, // G_MEMSET
+ 0U, // G_BZERO
+ 0U, // G_VECREDUCE_SEQ_FADD
+ 0U, // G_VECREDUCE_SEQ_FMUL
+ 0U, // G_VECREDUCE_FADD
+ 0U, // G_VECREDUCE_FMUL
+ 0U, // G_VECREDUCE_FMAX
+ 0U, // G_VECREDUCE_FMIN
+ 0U, // G_VECREDUCE_ADD
+ 0U, // G_VECREDUCE_MUL
+ 0U, // G_VECREDUCE_AND
+ 0U, // G_VECREDUCE_OR
+ 0U, // G_VECREDUCE_XOR
+ 0U, // G_VECREDUCE_SMAX
+ 0U, // G_VECREDUCE_SMIN
+ 0U, // G_VECREDUCE_UMAX
+ 0U, // G_VECREDUCE_UMIN
+ 0U, // G_SBFX
+ 0U, // G_UBFX
+ 0U, // ADJCALLSTACKDOWN
+ 0U, // ADJCALLSTACKUP
+ 0U, // PseudoAtomicLoadAdd32
+ 0U, // PseudoAtomicLoadAnd32
+ 0U, // PseudoAtomicLoadNand32
+ 0U, // PseudoAtomicLoadNand64
+ 0U, // PseudoAtomicLoadOr32
+ 0U, // PseudoAtomicLoadSub32
+ 0U, // PseudoAtomicLoadXor32
+ 0U, // PseudoAtomicStoreD
+ 0U, // PseudoAtomicStoreW
+ 0U, // PseudoAtomicSwap32
+ 0U, // PseudoBR
+ 0U, // PseudoBRIND
+ 0U, // PseudoB_TAIL
+ 0U, // PseudoCALL
+ 0U, // PseudoCALLIndirect
+ 0U, // PseudoCmpXchg32
+ 0U, // PseudoCmpXchg64
+ 0U, // PseudoJIRL_CALL
+ 0U, // PseudoJIRL_TAIL
+ 0U, // PseudoLA_ABS
+ 0U, // PseudoLA_ABS_LARGE
+ 0U, // PseudoLA_GOT
+ 2U, // PseudoLA_GOT_LARGE
+ 0U, // PseudoLA_PCREL
+ 2U, // PseudoLA_PCREL_LARGE
+ 0U, // PseudoLA_TLS_GD
+ 2U, // PseudoLA_TLS_GD_LARGE
+ 0U, // PseudoLA_TLS_IE
+ 2U, // PseudoLA_TLS_IE_LARGE
+ 0U, // PseudoLA_TLS_LD
+ 2U, // PseudoLA_TLS_LD_LARGE
+ 0U, // PseudoLA_TLS_LE
+ 0U, // PseudoLD_CFR
+ 0U, // PseudoLI_D
+ 0U, // PseudoLI_W
+ 0U, // PseudoMaskedAtomicLoadAdd32
+ 0U, // PseudoMaskedAtomicLoadMax32
+ 0U, // PseudoMaskedAtomicLoadMin32
+ 0U, // PseudoMaskedAtomicLoadNand32
+ 0U, // PseudoMaskedAtomicLoadSub32
+ 0U, // PseudoMaskedAtomicLoadUMax32
+ 0U, // PseudoMaskedAtomicLoadUMin32
+ 0U, // PseudoMaskedAtomicSwap32
+ 0U, // PseudoMaskedCmpXchg32
+ 0U, // PseudoRET
+ 0U, // PseudoST_CFR
+ 0U, // PseudoTAIL
+ 0U, // PseudoTAILIndirect
+ 0U, // PseudoUNIMP
+ 0U, // RDFCSR
+ 0U, // WRFCSR
+ 2U, // ADDI_D
+ 2U, // ADDI_W
+ 2U, // ADDU16I_D
+ 2U, // ADD_D
+ 2U, // ADD_W
+ 18U, // ALSL_D
+ 18U, // ALSL_W
+ 18U, // ALSL_WU
+ 6U, // AMADD_D
+ 6U, // AMADD_DB_D
+ 6U, // AMADD_DB_W
+ 6U, // AMADD_W
+ 6U, // AMAND_D
+ 6U, // AMAND_DB_D
+ 6U, // AMAND_DB_W
+ 6U, // AMAND_W
+ 6U, // AMMAX_D
+ 6U, // AMMAX_DB_D
+ 6U, // AMMAX_DB_DU
+ 6U, // AMMAX_DB_W
+ 6U, // AMMAX_DB_WU
+ 6U, // AMMAX_DU
+ 6U, // AMMAX_W
+ 6U, // AMMAX_WU
+ 6U, // AMMIN_D
+ 6U, // AMMIN_DB_D
+ 6U, // AMMIN_DB_DU
+ 6U, // AMMIN_DB_W
+ 6U, // AMMIN_DB_WU
+ 6U, // AMMIN_DU
+ 6U, // AMMIN_W
+ 6U, // AMMIN_WU
+ 6U, // AMOR_D
+ 6U, // AMOR_DB_D
+ 6U, // AMOR_DB_W
+ 6U, // AMOR_W
+ 6U, // AMSWAP_D
+ 6U, // AMSWAP_DB_D
+ 6U, // AMSWAP_DB_W
+ 6U, // AMSWAP_W
+ 6U, // AMXOR_D
+ 6U, // AMXOR_DB_D
+ 6U, // AMXOR_DB_W
+ 6U, // AMXOR_W
+ 2U, // AND
+ 2U, // ANDI
+ 2U, // ANDN
+ 0U, // ASRTGT_D
+ 0U, // ASRTLE_D
+ 0U, // B
+ 0U, // BCEQZ
+ 0U, // BCNEZ
+ 2U, // BEQ
+ 0U, // BEQZ
+ 2U, // BGE
+ 2U, // BGEU
+ 0U, // BITREV_4B
+ 0U, // BITREV_8B
+ 0U, // BITREV_D
+ 0U, // BITREV_W
+ 0U, // BL
+ 2U, // BLT
+ 2U, // BLTU
+ 2U, // BNE
+ 0U, // BNEZ
+ 0U, // BREAK
+ 11U, // BSTRINS_D
+ 11U, // BSTRINS_W
+ 18U, // BSTRPICK_D
+ 18U, // BSTRPICK_W
+ 18U, // BYTEPICK_D
+ 18U, // BYTEPICK_W
+ 2U, // CACOP
+ 0U, // CLO_D
+ 0U, // CLO_W
+ 0U, // CLZ_D
+ 0U, // CLZ_W
+ 0U, // CPUCFG
+ 2U, // CRCC_W_B_W
+ 2U, // CRCC_W_D_W
+ 2U, // CRCC_W_H_W
+ 2U, // CRCC_W_W_W
+ 2U, // CRC_W_B_W
+ 2U, // CRC_W_D_W
+ 2U, // CRC_W_H_W
+ 2U, // CRC_W_W_W
+ 0U, // CSRRD
+ 0U, // CSRWR
+ 1U, // CSRXCHG
+ 0U, // CTO_D
+ 0U, // CTO_W
+ 0U, // CTZ_D
+ 0U, // CTZ_W
+ 0U, // DBAR
+ 0U, // DBCL
+ 2U, // DIV_D
+ 2U, // DIV_DU
+ 2U, // DIV_W
+ 2U, // DIV_WU
+ 0U, // ERTN
+ 0U, // EXT_W_B
+ 0U, // EXT_W_H
+ 0U, // FABS_D
+ 0U, // FABS_S
+ 2U, // FADD_D
+ 2U, // FADD_S
+ 0U, // FCLASS_D
+ 0U, // FCLASS_S
+ 2U, // FCMP_CAF_D
+ 2U, // FCMP_CAF_S
+ 2U, // FCMP_CEQ_D
+ 2U, // FCMP_CEQ_S
+ 2U, // FCMP_CLE_D
+ 2U, // FCMP_CLE_S
+ 2U, // FCMP_CLT_D
+ 2U, // FCMP_CLT_S
+ 2U, // FCMP_CNE_D
+ 2U, // FCMP_CNE_S
+ 2U, // FCMP_COR_D
+ 2U, // FCMP_COR_S
+ 2U, // FCMP_CUEQ_D
+ 2U, // FCMP_CUEQ_S
+ 2U, // FCMP_CULE_D
+ 2U, // FCMP_CULE_S
+ 2U, // FCMP_CULT_D
+ 2U, // FCMP_CULT_S
+ 2U, // FCMP_CUNE_D
+ 2U, // FCMP_CUNE_S
+ 2U, // FCMP_CUN_D
+ 2U, // FCMP_CUN_S
+ 2U, // FCMP_SAF_D
+ 2U, // FCMP_SAF_S
+ 2U, // FCMP_SEQ_D
+ 2U, // FCMP_SEQ_S
+ 2U, // FCMP_SLE_D
+ 2U, // FCMP_SLE_S
+ 2U, // FCMP_SLT_D
+ 2U, // FCMP_SLT_S
+ 2U, // FCMP_SNE_D
+ 2U, // FCMP_SNE_S
+ 2U, // FCMP_SOR_D
+ 2U, // FCMP_SOR_S
+ 2U, // FCMP_SUEQ_D
+ 2U, // FCMP_SUEQ_S
+ 2U, // FCMP_SULE_D
+ 2U, // FCMP_SULE_S
+ 2U, // FCMP_SULT_D
+ 2U, // FCMP_SULT_S
+ 2U, // FCMP_SUNE_D
+ 2U, // FCMP_SUNE_S
+ 2U, // FCMP_SUN_D
+ 2U, // FCMP_SUN_S
+ 2U, // FCOPYSIGN_D
+ 2U, // FCOPYSIGN_S
+ 0U, // FCVT_D_S
+ 0U, // FCVT_S_D
+ 2U, // FDIV_D
+ 2U, // FDIV_S
+ 0U, // FFINT_D_L
+ 0U, // FFINT_D_W
+ 0U, // FFINT_S_L
+ 0U, // FFINT_S_W
+ 2U, // FLDGT_D
+ 2U, // FLDGT_S
+ 2U, // FLDLE_D
+ 2U, // FLDLE_S
+ 2U, // FLDX_D
+ 2U, // FLDX_S
+ 2U, // FLD_D
+ 2U, // FLD_S
+ 0U, // FLOGB_D
+ 0U, // FLOGB_S
+ 18U, // FMADD_D
+ 18U, // FMADD_S
+ 2U, // FMAXA_D
+ 2U, // FMAXA_S
+ 2U, // FMAX_D
+ 2U, // FMAX_S
+ 2U, // FMINA_D
+ 2U, // FMINA_S
+ 2U, // FMIN_D
+ 2U, // FMIN_S
+ 0U, // FMOV_D
+ 0U, // FMOV_S
+ 18U, // FMSUB_D
+ 18U, // FMSUB_S
+ 2U, // FMUL_D
+ 2U, // FMUL_S
+ 0U, // FNEG_D
+ 0U, // FNEG_S
+ 18U, // FNMADD_D
+ 18U, // FNMADD_S
+ 18U, // FNMSUB_D
+ 18U, // FNMSUB_S
+ 0U, // FRECIP_D
+ 0U, // FRECIP_S
+ 0U, // FRINT_D
+ 0U, // FRINT_S
+ 0U, // FRSQRT_D
+ 0U, // FRSQRT_S
+ 2U, // FSCALEB_D
+ 2U, // FSCALEB_S
+ 18U, // FSEL_D
+ 18U, // FSEL_S
+ 0U, // FSQRT_D
+ 0U, // FSQRT_S
+ 2U, // FSTGT_D
+ 2U, // FSTGT_S
+ 2U, // FSTLE_D
+ 2U, // FSTLE_S
+ 2U, // FSTX_D
+ 2U, // FSTX_S
+ 2U, // FST_D
+ 2U, // FST_S
+ 2U, // FSUB_D
+ 2U, // FSUB_S
+ 0U, // FTINTRM_L_D
+ 0U, // FTINTRM_L_S
+ 0U, // FTINTRM_W_D
+ 0U, // FTINTRM_W_S
+ 0U, // FTINTRNE_L_D
+ 0U, // FTINTRNE_L_S
+ 0U, // FTINTRNE_W_D
+ 0U, // FTINTRNE_W_S
+ 0U, // FTINTRP_L_D
+ 0U, // FTINTRP_L_S
+ 0U, // FTINTRP_W_D
+ 0U, // FTINTRP_W_S
+ 0U, // FTINTRZ_L_D
+ 0U, // FTINTRZ_L_S
+ 0U, // FTINTRZ_W_D
+ 0U, // FTINTRZ_W_S
+ 0U, // FTINT_L_D
+ 0U, // FTINT_L_S
+ 0U, // FTINT_W_D
+ 0U, // FTINT_W_S
+ 0U, // IBAR
+ 0U, // IDLE
+ 0U, // INVTLB
+ 0U, // IOCSRRD_B
+ 0U, // IOCSRRD_D
+ 0U, // IOCSRRD_H
+ 0U, // IOCSRRD_W
+ 0U, // IOCSRWR_B
+ 0U, // IOCSRWR_D
+ 0U, // IOCSRWR_H
+ 0U, // IOCSRWR_W
+ 2U, // JIRL
+ 2U, // LDDIR
+ 2U, // LDGT_B
+ 2U, // LDGT_D
+ 2U, // LDGT_H
+ 2U, // LDGT_W
+ 2U, // LDLE_B
+ 2U, // LDLE_D
+ 2U, // LDLE_H
+ 2U, // LDLE_W
+ 0U, // LDPTE
+ 2U, // LDPTR_D
+ 2U, // LDPTR_W
+ 2U, // LDX_B
+ 2U, // LDX_BU
+ 2U, // LDX_D
+ 2U, // LDX_H
+ 2U, // LDX_HU
+ 2U, // LDX_W
+ 2U, // LDX_WU
+ 2U, // LD_B
+ 2U, // LD_BU
+ 2U, // LD_D
+ 2U, // LD_H
+ 2U, // LD_HU
+ 2U, // LD_W
+ 2U, // LD_WU
+ 2U, // LL_D
+ 2U, // LL_W
+ 0U, // LU12I_W
+ 0U, // LU32I_D
+ 2U, // LU52I_D
+ 2U, // MASKEQZ
+ 2U, // MASKNEZ
+ 2U, // MOD_D
+ 2U, // MOD_DU
+ 2U, // MOD_W
+ 2U, // MOD_WU
+ 0U, // MOVCF2FR_S
+ 0U, // MOVCF2GR
+ 0U, // MOVFCSR2GR
+ 0U, // MOVFR2CF_S
+ 0U, // MOVFR2GR_D
+ 0U, // MOVFR2GR_S
+ 0U, // MOVFR2GR_S_64
+ 0U, // MOVFRH2GR_S
+ 0U, // MOVGR2CF
+ 0U, // MOVGR2FCSR
+ 0U, // MOVGR2FRH_W
+ 0U, // MOVGR2FR_D
+ 0U, // MOVGR2FR_W
+ 0U, // MOVGR2FR_W_64
+ 2U, // MULH_D
+ 2U, // MULH_DU
+ 2U, // MULH_W
+ 2U, // MULH_WU
+ 2U, // MULW_D_W
+ 2U, // MULW_D_WU
+ 2U, // MUL_D
+ 2U, // MUL_W
+ 2U, // NOR
+ 2U, // OR
+ 2U, // ORI
+ 2U, // ORN
+ 0U, // PCADDI
+ 0U, // PCADDU12I
+ 0U, // PCADDU18I
+ 0U, // PCALAU12I
+ 2U, // PRELD
+ 2U, // PRELDX
+ 0U, // RDTIMEH_W
+ 0U, // RDTIMEL_W
+ 0U, // RDTIME_D
+ 0U, // REVB_2H
+ 0U, // REVB_2W
+ 0U, // REVB_4H
+ 0U, // REVB_D
+ 0U, // REVH_2W
+ 0U, // REVH_D
+ 2U, // ROTRI_D
+ 2U, // ROTRI_W
+ 2U, // ROTR_D
+ 2U, // ROTR_W
+ 1U, // SC_D
+ 1U, // SC_W
+ 2U, // SLLI_D
+ 2U, // SLLI_W
+ 2U, // SLL_D
+ 2U, // SLL_W
+ 2U, // SLT
+ 2U, // SLTI
+ 2U, // SLTU
+ 2U, // SLTUI
+ 2U, // SRAI_D
+ 2U, // SRAI_W
+ 2U, // SRA_D
+ 2U, // SRA_W
+ 2U, // SRLI_D
+ 2U, // SRLI_W
+ 2U, // SRL_D
+ 2U, // SRL_W
+ 2U, // STGT_B
+ 2U, // STGT_D
+ 2U, // STGT_H
+ 2U, // STGT_W
+ 2U, // STLE_B
+ 2U, // STLE_D
+ 2U, // STLE_H
+ 2U, // STLE_W
+ 2U, // STPTR_D
+ 2U, // STPTR_W
+ 2U, // STX_B
+ 2U, // STX_D
+ 2U, // STX_H
+ 2U, // STX_W
+ 2U, // ST_B
+ 2U, // ST_D
+ 2U, // ST_H
+ 2U, // ST_W
+ 2U, // SUB_D
+ 2U, // SUB_W
+ 0U, // SYSCALL
+ 0U, // TLBCLR
+ 0U, // TLBFILL
+ 0U, // TLBFLUSH
+ 0U, // TLBRD
+ 0U, // TLBSRCH
+ 0U, // TLBWR
+ 2U, // XOR
+ 2U, // XORI
+ };
+
+ // Emit the opcode for the instruction.
+ uint32_t Bits = 0;
+ Bits |= OpInfo0[MI->getOpcode()] << 0;
+ Bits |= OpInfo1[MI->getOpcode()] << 16;
+ return {AsmStrs+(Bits & 4095)-1, Bits};
+
+}
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+LLVM_NO_PROFILE_INSTRUMENT_FUNCTION
+void LoongArchInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) {
+ O << "\t";
+
+ auto MnemonicInfo = getMnemonic(MI);
+
+ O << MnemonicInfo.first;
+
+ uint32_t Bits = MnemonicInfo.second;
+ assert(Bits != 0 && "Cannot print this instruction.");
+
+ // Fragment 0 encoded into 2 bits for 4 unique commands.
+ switch ((Bits >> 12) & 3) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
+ return;
+ break;
+ case 1:
+ // PseudoLA_ABS, PseudoLA_ABS_LARGE, PseudoLA_GOT, PseudoLA_GOT_LARGE, Ps...
+ printOperand(MI, 0, STI, O);
+ break;
+ case 2:
+ // BSTRINS_D, BSTRINS_W, CSRWR, CSRXCHG, LU32I_D, MOVGR2FRH_W, SC_D, SC_W
+ printOperand(MI, 1, STI, O);
+ O << ", ";
+ printOperand(MI, 2, STI, O);
+ break;
+ case 3:
+ // INVTLB
+ printOperand(MI, 2, STI, O);
+ O << ", ";
+ printOperand(MI, 1, STI, O);
+ O << ", ";
+ printOperand(MI, 0, STI, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 1 encoded into 1 bits for 2 unique commands.
+ if ((Bits >> 14) & 1) {
+ // B, BL, BREAK, CSRWR, DBAR, DBCL, IBAR, IDLE, LU32I_D, MOVGR2FRH_W, SYS...
+ return;
+ } else {
+ // PseudoLA_ABS, PseudoLA_ABS_LARGE, PseudoLA_GOT, PseudoLA_GOT_LARGE, Ps...
+ O << ", ";
+ }
+
+
+ // Fragment 2 encoded into 2 bits for 3 unique commands.
+ switch ((Bits >> 15) & 3) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // PseudoLA_ABS, PseudoLA_GOT, PseudoLA_GOT_LARGE, PseudoLA_PCREL, Pseudo...
+ printOperand(MI, 1, STI, O);
+ break;
+ case 1:
+ // PseudoLA_ABS_LARGE
+ printOperand(MI, 2, STI, O);
+ return;
+ break;
+ case 2:
+ // BSTRINS_D, BSTRINS_W, CSRXCHG, SC_D, SC_W
+ printOperand(MI, 3, STI, O);
+ break;
+ }
+
+
+ // Fragment 3 encoded into 1 bits for 2 unique commands.
+ if ((Bits >> 17) & 1) {
+ // PseudoLA_GOT_LARGE, PseudoLA_PCREL_LARGE, PseudoLA_TLS_GD_LARGE, Pseud...
+ O << ", ";
+ } else {
+ // PseudoLA_ABS, PseudoLA_GOT, PseudoLA_PCREL, PseudoLA_TLS_GD, PseudoLA_...
+ return;
+ }
+
+
+ // Fragment 4 encoded into 2 bits for 3 unique commands.
+ switch ((Bits >> 18) & 3) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // PseudoLA_GOT_LARGE, PseudoLA_PCREL_LARGE, PseudoLA_TLS_GD_LARGE, Pseud...
+ printOperand(MI, 2, STI, O);
+ break;
+ case 1:
+ // AMADD_D, AMADD_DB_D, AMADD_DB_W, AMADD_W, AMAND_D, AMAND_DB_D, AMAND_D...
+ printAtomicMemOp(MI, 2, STI, O);
+ return;
+ break;
+ case 2:
+ // BSTRINS_D, BSTRINS_W
+ printOperand(MI, 4, STI, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 5 encoded into 1 bits for 2 unique commands.
+ if ((Bits >> 20) & 1) {
+ // ALSL_D, ALSL_W, ALSL_WU, BSTRPICK_D, BSTRPICK_W, BYTEPICK_D, BYTEPICK_...
+ O << ", ";
+ printOperand(MI, 3, STI, O);
+ return;
+ } else {
+ // PseudoLA_GOT_LARGE, PseudoLA_PCREL_LARGE, PseudoLA_TLS_GD_LARGE, Pseud...
+ return;
+ }
+
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description. This returns the assembler name
+/// for the specified register.
+const char *LoongArchInstPrinter::
+getRegisterName(MCRegister Reg, unsigned AltIdx) {
+ unsigned RegNo = Reg.id();
+ assert(RegNo && RegNo < 109 && "Invalid register number!");
+
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Woverlength-strings"
+#endif
+ static const char AsmStrsNoRegAltName[] = {
+ /* 0 */ "f10\0"
+ /* 4 */ "r10\0"
+ /* 8 */ "f20\0"
+ /* 12 */ "r20\0"
+ /* 16 */ "f30\0"
+ /* 20 */ "r30\0"
+ /* 24 */ "fcc0\0"
+ /* 29 */ "f0\0"
+ /* 32 */ "fcsr0\0"
+ /* 38 */ "f11\0"
+ /* 42 */ "r11\0"
+ /* 46 */ "f21\0"
+ /* 50 */ "r21\0"
+ /* 54 */ "f31\0"
+ /* 58 */ "r31\0"
+ /* 62 */ "fcc1\0"
+ /* 67 */ "f1\0"
+ /* 70 */ "fcsr1\0"
+ /* 76 */ "f12\0"
+ /* 80 */ "r12\0"
+ /* 84 */ "f22\0"
+ /* 88 */ "r22\0"
+ /* 92 */ "fcc2\0"
+ /* 97 */ "f2\0"
+ /* 100 */ "fcsr2\0"
+ /* 106 */ "f13\0"
+ /* 110 */ "r13\0"
+ /* 114 */ "f23\0"
+ /* 118 */ "r23\0"
+ /* 122 */ "fcc3\0"
+ /* 127 */ "f3\0"
+ /* 130 */ "fcsr3\0"
+ /* 136 */ "f14\0"
+ /* 140 */ "r14\0"
+ /* 144 */ "f24\0"
+ /* 148 */ "r24\0"
+ /* 152 */ "fcc4\0"
+ /* 157 */ "f4\0"
+ /* 160 */ "r4\0"
+ /* 163 */ "f15\0"
+ /* 167 */ "r15\0"
+ /* 171 */ "f25\0"
+ /* 175 */ "r25\0"
+ /* 179 */ "fcc5\0"
+ /* 184 */ "f5\0"
+ /* 187 */ "r5\0"
+ /* 190 */ "f16\0"
+ /* 194 */ "r16\0"
+ /* 198 */ "f26\0"
+ /* 202 */ "r26\0"
+ /* 206 */ "fcc6\0"
+ /* 211 */ "f6\0"
+ /* 214 */ "r6\0"
+ /* 217 */ "f17\0"
+ /* 221 */ "r17\0"
+ /* 225 */ "f27\0"
+ /* 229 */ "r27\0"
+ /* 233 */ "fcc7\0"
+ /* 238 */ "f7\0"
+ /* 241 */ "r7\0"
+ /* 244 */ "f18\0"
+ /* 248 */ "r18\0"
+ /* 252 */ "f28\0"
+ /* 256 */ "r28\0"
+ /* 260 */ "f8\0"
+ /* 263 */ "r8\0"
+ /* 266 */ "f19\0"
+ /* 270 */ "r19\0"
+ /* 274 */ "f29\0"
+ /* 278 */ "r29\0"
+ /* 282 */ "f9\0"
+ /* 285 */ "r9\0"
+};
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+ static const uint16_t RegAsmOffsetNoRegAltName[] = {
+ 29, 67, 97, 127, 157, 184, 211, 238, 260, 282, 0, 38, 76, 106,
+ 136, 163, 190, 217, 244, 266, 8, 46, 84, 114, 144, 171, 198, 225,
+ 252, 274, 16, 54, 24, 62, 92, 122, 152, 179, 206, 233, 32, 70,
+ 100, 130, 35, 73, 103, 133, 160, 187, 214, 241, 263, 285, 4, 42,
+ 80, 110, 140, 167, 194, 221, 248, 270, 12, 50, 88, 118, 148, 175,
+ 202, 229, 256, 278, 20, 58, 29, 67, 97, 127, 157, 184, 211, 238,
+ 260, 282, 0, 38, 76, 106, 136, 163, 190, 217, 244, 266, 8, 46,
+ 84, 114, 144, 171, 198, 225, 252, 274, 16, 54,
+ };
+
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Woverlength-strings"
+#endif
+ static const char AsmStrsRegAliasName[] = {
+ /* 0 */ "ft10\0"
+ /* 5 */ "fa0\0"
+ /* 9 */ "fs0\0"
+ /* 13 */ "ft0\0"
+ /* 17 */ "ft11\0"
+ /* 22 */ "fa1\0"
+ /* 26 */ "fs1\0"
+ /* 30 */ "ft1\0"
+ /* 34 */ "ft12\0"
+ /* 39 */ "fa2\0"
+ /* 43 */ "fs2\0"
+ /* 47 */ "ft2\0"
+ /* 51 */ "ft13\0"
+ /* 56 */ "fa3\0"
+ /* 60 */ "fs3\0"
+ /* 64 */ "ft3\0"
+ /* 68 */ "ft14\0"
+ /* 73 */ "fa4\0"
+ /* 77 */ "fs4\0"
+ /* 81 */ "ft4\0"
+ /* 85 */ "ft15\0"
+ /* 90 */ "fa5\0"
+ /* 94 */ "fs5\0"
+ /* 98 */ "ft5\0"
+ /* 102 */ "fa6\0"
+ /* 106 */ "fs6\0"
+ /* 110 */ "ft6\0"
+ /* 114 */ "fa7\0"
+ /* 118 */ "fs7\0"
+ /* 122 */ "ft7\0"
+ /* 126 */ "s8\0"
+ /* 129 */ "ft8\0"
+ /* 133 */ "ft9\0"
+ /* 137 */ "ra\0"
+ /* 140 */ "zero\0"
+ /* 145 */ "fp\0"
+ /* 148 */ "sp\0"
+ /* 151 */ "tp\0"
+};
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+ static const uint8_t RegAsmOffsetRegAliasName[] = {
+ 5, 22, 39, 56, 73, 90, 102, 114, 13, 30, 47, 64, 81, 98,
+ 110, 122, 129, 133, 0, 17, 34, 51, 68, 85, 9, 26, 43, 60,
+ 77, 94, 106, 118, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+ 4, 4, 140, 137, 151, 148, 6, 23, 40, 57, 74, 91, 103, 115,
+ 14, 31, 48, 65, 82, 99, 111, 123, 130, 4, 145, 10, 27, 44,
+ 61, 78, 95, 107, 119, 126, 5, 22, 39, 56, 73, 90, 102, 114,
+ 13, 30, 47, 64, 81, 98, 110, 122, 129, 133, 0, 17, 34, 51,
+ 68, 85, 9, 26, 43, 60, 77, 94, 106, 118,
+ };
+
+ switch(AltIdx) {
+ default: llvm_unreachable("Invalid register alt name index!");
+ case LoongArch::NoRegAltName:
+ assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
+ "Invalid alt name index for register!");
+ return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
+ case LoongArch::RegAliasName:
+ if (!*(AsmStrsRegAliasName+RegAsmOffsetRegAliasName[RegNo-1]))
+ return getRegisterName(RegNo, LoongArch::NoRegAltName);
+ return AsmStrsRegAliasName+RegAsmOffsetRegAliasName[RegNo-1];
+ }
+}
+
+#ifdef PRINT_ALIAS_INSTR
+#undef PRINT_ALIAS_INSTR
+
+bool LoongArchInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) {
+ static const PatternsForOpcode OpToPatterns[] = {
+ {LoongArch::PseudoLA_ABS, 0, 1 },
+ {LoongArch::PseudoLA_GOT_LARGE, 1, 1 },
+ {LoongArch::PseudoLA_PCREL, 2, 1 },
+ {LoongArch::PseudoLA_PCREL_LARGE, 3, 2 },
+ {LoongArch::ANDI, 5, 1 },
+ {LoongArch::JIRL, 6, 2 },
+ {LoongArch::OR, 8, 1 },
+ };
+
+ static const AliasPattern Patterns[] = {
+ // LoongArch::PseudoLA_ABS - 0
+ {0, 0, 2, 2 },
+ // LoongArch::PseudoLA_GOT_LARGE - 1
+ {16, 2, 3, 2 },
+ // LoongArch::PseudoLA_PCREL - 2
+ {0, 4, 2, 1 },
+ // LoongArch::PseudoLA_PCREL_LARGE - 3
+ {37, 5, 3, 2 },
+ {16, 7, 3, 3 },
+ // LoongArch::ANDI - 5
+ {57, 10, 3, 3 },
+ // LoongArch::JIRL - 6
+ {61, 13, 3, 3 },
+ {65, 16, 3, 3 },
+ // LoongArch::OR - 8
+ {71, 19, 3, 3 },
+ };
+
+ static const AliasPatternCond Conds[] = {
+ // (PseudoLA_ABS GPR:$dst, bare_symbol:$src) - 0
+ {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID},
+ {AliasPatternCond::K_Feature, LoongArch::LaLocalWithAbs},
+ // (PseudoLA_GOT_LARGE GPR:$dst, GPR:$tmp, bare_symbol:$src) - 2
+ {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID},
+ // (PseudoLA_PCREL GPR:$dst, bare_symbol:$src) - 4
+ {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID},
+ // (PseudoLA_PCREL_LARGE GPR:$dst, GPR:$tmp, bare_symbol:$src) - 5
+ {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID},
+ // (PseudoLA_PCREL_LARGE GPR:$dst, GPR:$tmp, bare_symbol:$src) - 7
+ {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID},
+ {AliasPatternCond::K_Feature, LoongArch::LaGlobalWithPcrel},
+ // (ANDI R0, R0, 0) - 10
+ {AliasPatternCond::K_Reg, LoongArch::R0},
+ {AliasPatternCond::K_Reg, LoongArch::R0},
+ {AliasPatternCond::K_Imm, uint32_t(0)},
+ // (JIRL R0, R1, 0) - 13
+ {AliasPatternCond::K_Reg, LoongArch::R0},
+ {AliasPatternCond::K_Reg, LoongArch::R1},
+ {AliasPatternCond::K_Imm, uint32_t(0)},
+ // (JIRL R0, GPR:$rj, 0) - 16
+ {AliasPatternCond::K_Reg, LoongArch::R0},
+ {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(0)},
+ // (OR GPR:$dst, GPR:$src, R0) - 19
+ {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID},
+ {AliasPatternCond::K_Reg, LoongArch::R0},
+ };
+
+ static const char AsmStrings[] =
+ /* 0 */ "la.local $\x01, $\x02\0"
+ /* 16 */ "la.global $\x01, $\x02, $\x03\0"
+ /* 37 */ "la.local $\x01, $\x02, $\x03\0"
+ /* 57 */ "nop\0"
+ /* 61 */ "ret\0"
+ /* 65 */ "jr $\x02\0"
+ /* 71 */ "move $\x01, $\x02\0"
+ ;
+
+#ifndef NDEBUG
+ static struct SortCheck {
+ SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
+ assert(std::is_sorted(
+ OpToPatterns.begin(), OpToPatterns.end(),
+ [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
+ return L.Opcode < R.Opcode;
+ }) &&
+ "tablegen failed to sort opcode patterns");
+ }
+ } sortCheckVar(OpToPatterns);
+#endif
+
+ AliasMatchingData M {
+ ArrayRef(OpToPatterns),
+ ArrayRef(Patterns),
+ ArrayRef(Conds),
+ StringRef(AsmStrings, std::size(AsmStrings)),
+ nullptr,
+ };
+ const char *AsmString = matchAliasPatterns(MI, &STI, M);
+ if (!AsmString) return false;
+
+ unsigned I = 0;
+ while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
+ AsmString[I] != '$' && AsmString[I] != '\0')
+ ++I;
+ OS << '\t' << StringRef(AsmString, I);
+ if (AsmString[I] != '\0') {
+ if (AsmString[I] == ' ' || AsmString[I] == '\t') {
+ OS << '\t';
+ ++I;
+ }
+ do {
+ if (AsmString[I] == '$') {
+ ++I;
+ if (AsmString[I] == (char)0xff) {
+ ++I;
+ int OpIdx = AsmString[I++] - 1;
+ int PrintMethodIdx = AsmString[I++] - 1;
+ printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, OS);
+ } else
+ printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS);
+ } else {
+ OS << AsmString[I++];
+ }
+ } while (AsmString[I] != '\0');
+ }
+
+ return true;
+}
+
+void LoongArchInstPrinter::printCustomAliasOperand(
+ const MCInst *MI, uint64_t Address, unsigned OpIdx,
+ unsigned PrintMethodIdx,
+ const MCSubtargetInfo &STI,
+ raw_ostream &OS) {
+ llvm_unreachable("Unknown PrintMethod kind");
+}
+
+#endif // PRINT_ALIAS_INSTR
diff --git a/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenDAGISel.inc b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenDAGISel.inc
new file mode 100644
index 0000000..d0f8a81
--- /dev/null
+++ b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenDAGISel.inc
@@ -0,0 +1,10214 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* DAG Instruction Selector for the LoongArch target *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+// *** NOTE: This file is #included into the middle of the target
+// *** instruction selector class. These functions are really methods.
+
+// If GET_DAGISEL_DECL is #defined with any value, only function
+// declarations will be included when this file is included.
+// If GET_DAGISEL_BODY is #defined, its value should be the name of
+// the instruction selector class. Function bodies will be emitted
+// and each function's name will be qualified with the name of the
+// class.
+//
+// When neither of the GET_DAGISEL* macros is defined, the functions
+// are emitted inline.
+
+#if defined(GET_DAGISEL_DECL) && defined(GET_DAGISEL_BODY)
+#error GET_DAGISEL_DECL and GET_DAGISEL_BODY cannot be both defined, undef both for inline definitions
+#endif
+
+#ifdef GET_DAGISEL_BODY
+#define LOCAL_DAGISEL_STRINGIZE(X) LOCAL_DAGISEL_STRINGIZE_(X)
+#define LOCAL_DAGISEL_STRINGIZE_(X) #X
+static_assert(sizeof(LOCAL_DAGISEL_STRINGIZE(GET_DAGISEL_BODY)) > 1,
+ "GET_DAGISEL_BODY is empty: it should be defined with the class name");
+#undef LOCAL_DAGISEL_STRINGIZE_
+#undef LOCAL_DAGISEL_STRINGIZE
+#endif
+
+#if !defined(GET_DAGISEL_DECL) && !defined(GET_DAGISEL_BODY)
+#define DAGISEL_INLINE 1
+#else
+#define DAGISEL_INLINE 0
+#endif
+
+#if !DAGISEL_INLINE
+#define DAGISEL_CLASS_COLONCOLON GET_DAGISEL_BODY ::
+#else
+#define DAGISEL_CLASS_COLONCOLON
+#endif
+
+#ifdef GET_DAGISEL_DECL
+void SelectCode(SDNode *N);
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+void DAGISEL_CLASS_COLONCOLON SelectCode(SDNode *N)
+{
+ // Some target values are emitted as 2 bytes, TARGET_VAL handles
+ // this.
+ #define TARGET_VAL(X) X & 255, unsigned(X) >> 8
+ static const unsigned char MatcherTable[] = {
+ OPC_SwitchOpcode , 127, TARGET_VAL(ISD::MUL),
+ OPC_Scope, 67,
+ OPC_MoveChild0,
+ OPC_SwitchOpcode , 32, TARGET_VAL(LoongArchISD::BSTRPICK),
+ OPC_RecordChild0,
+ OPC_CheckChild1Integer, 62,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckChild2Integer, 0,
+ OPC_MoveParent,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(LoongArchISD::BSTRPICK),
+ OPC_RecordChild0,
+ OPC_CheckChild1Integer, 62,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckChild2Integer, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MULW_D_WU), 0,
+ MVT::i64, 2, 0, 1,
+ 26, TARGET_VAL(ISD::SIGN_EXTEND_INREG),
+ OPC_RecordChild0,
+ OPC_MoveChild1,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND_INREG),
+ OPC_RecordChild0,
+ OPC_MoveChild1,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MULW_D_W), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 56,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MUL_W), 0,
+ MVT::i64, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MUL_D), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 24, MVT::i32,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MUL_W), 0,
+ MVT::i32, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MUL_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 0,
+ 23|128,2, TARGET_VAL(LoongArchISD::BSTRPICK),
+ OPC_Scope, 15|128,1,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
+ OPC_Scope, 67,
+ OPC_RecordChild0,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 0,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 62,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckChild2Integer, 0,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ALSL_WU), 0,
+ MVT::i64, 3, 1, 0, 3,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 62,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckChild2Integer, 0,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ALSL_WU), 0,
+ MVT::i32, 3, 1, 0, 3,
+ 0,
+ 68,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 0,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 62,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckChild2Integer, 0,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ALSL_WU), 0,
+ MVT::i64, 3, 0, 2, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 62,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckChild2Integer, 0,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ALSL_WU), 0,
+ MVT::i32, 3, 0, 2, 3,
+ 0,
+ 0,
+ 2|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_Scope, 60,
+ OPC_CheckPredicate, 1,
+ OPC_SwitchType , 26, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BSTRPICK_W), 0,
+ MVT::i64, 3, 0, 3, 4,
+ 26, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BSTRPICK_W), 0,
+ MVT::i32, 3, 0, 3, 4,
+ 0,
+ 60,
+ OPC_CheckPredicate, 2,
+ OPC_SwitchType , 26, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BSTRPICK_D), 0,
+ MVT::i64, 3, 0, 3, 4,
+ 26, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BSTRPICK_D), 0,
+ MVT::i32, 3, 0, 3, 4,
+ 0,
+ 0,
+ 0,
+ 36|128,17, TARGET_VAL(ISD::LOAD),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_Scope, 54|128,10,
+ OPC_MoveChild1,
+ OPC_SwitchOpcode , 89|128,6, TARGET_VAL(ISD::ADD),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 80|128,3,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_Scope, 17|128,3,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 107|128,1, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 5,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 42,
+ OPC_CheckPredicate, 11,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_BU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_HU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 0,
+ 20,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 11,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_WU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 0,
+ 25|128,1, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 5,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 42,
+ OPC_CheckPredicate, 11,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_BU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_HU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 0,
+ 0,
+ 0,
+ 54,
+ OPC_CheckPredicate, 13,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 5,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDPTR_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDPTR_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 0,
+ 0,
+ 1|128,3,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 5,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 2,
+ 18,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 2,
+ 18,
+ OPC_CheckPredicate, 11,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_BU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 2,
+ 18,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 2,
+ 18,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 2,
+ 18,
+ OPC_CheckPredicate, 11,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_HU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 2,
+ 18,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 2,
+ 18,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 2,
+ 18,
+ OPC_CheckPredicate, 11,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_WU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 2,
+ 16,
+ OPC_CheckPredicate, 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 2,
+ 18,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 1,
+ 18,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 1,
+ 18,
+ OPC_CheckPredicate, 11,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_BU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 1,
+ 18,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 1,
+ 18,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 1,
+ 18,
+ OPC_CheckPredicate, 11,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_HU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 1,
+ 18,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 1,
+ 18,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 1,
+ 18,
+ OPC_CheckPredicate, 11,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_WU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 1,
+ 16,
+ OPC_CheckPredicate, 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 1,
+ 0,
+ 0,
+ 82|128,3, TARGET_VAL(ISD::OR),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_Scope, 17|128,3,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 107|128,1, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 5,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 42,
+ OPC_CheckPredicate, 11,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_BU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_HU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 0,
+ 20,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 11,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_WU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 0,
+ 25|128,1, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 5,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 20,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 42,
+ OPC_CheckPredicate, 11,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_BU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_HU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 0,
+ 0,
+ 0,
+ 54,
+ OPC_CheckPredicate, 13,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 5,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDPTR_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDPTR_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 0,
+ 0,
+ 0,
+ 29|128,3,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 5,
+ OPC_Scope, 44,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 7,
+ OPC_SwitchType , 17, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 17, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 3,
+ 0,
+ 44,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 7,
+ OPC_SwitchType , 17, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 17, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 3,
+ 0,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 9,
+ OPC_SwitchType , 17, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 17, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 3,
+ 0,
+ 44,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_SwitchType , 17, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 17, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 3,
+ 0,
+ 42,
+ OPC_CheckPredicate, 10,
+ OPC_SwitchType , 17, MVT::i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 17, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 3,
+ 0,
+ 90,
+ OPC_CheckPredicate, 11,
+ OPC_Scope, 42,
+ OPC_CheckPredicate, 7,
+ OPC_SwitchType , 17, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_BU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 17, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_BU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 3,
+ 0,
+ 42,
+ OPC_CheckPredicate, 9,
+ OPC_SwitchType , 17, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_HU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 17, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_HU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 3,
+ 0,
+ 0,
+ 23,
+ OPC_CheckPredicate, 6,
+ OPC_CheckPredicate, 12,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 23,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 12,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 23,
+ OPC_CheckPredicate, 11,
+ OPC_CheckPredicate, 12,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_WU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 21,
+ OPC_CheckPredicate, 10,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 0,
+ 111|128,2,
+ OPC_MoveChild1,
+ OPC_SwitchOpcode , 126|128,1, TARGET_VAL(ISD::ADD),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 101,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 43, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPredicate, 10,
+ OPC_SwitchType , 16, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLD_S), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2, 3, 4,
+ 16, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2, 3, 4,
+ 0,
+ 43, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPredicate, 10,
+ OPC_SwitchType , 16, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLD_S), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2, 3, 4,
+ 16, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2, 3, 4,
+ 0,
+ 0,
+ 73,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPredicate, 10,
+ OPC_SwitchType , 30, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_Scope, 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLDX_S), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2, 3, 2,
+ 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLDX_S), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2, 3, 1,
+ 0,
+ 30, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_Scope, 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLDX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2, 3, 2,
+ 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLDX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2, 3, 1,
+ 0,
+ 0,
+ 73,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPredicate, 10,
+ OPC_SwitchType , 30, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_Scope, 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLDX_S), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2, 3, 2,
+ 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLDX_S), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2, 3, 1,
+ 0,
+ 30, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_Scope, 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLDX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2, 3, 2,
+ 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLDX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2, 3, 1,
+ 0,
+ 0,
+ 0,
+ 103, TARGET_VAL(ISD::OR),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 43, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPredicate, 10,
+ OPC_SwitchType , 16, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLD_S), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2, 3, 4,
+ 16, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2, 3, 4,
+ 0,
+ 43, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPredicate, 10,
+ OPC_SwitchType , 16, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLD_S), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2, 3, 4,
+ 16, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2, 3, 4,
+ 0,
+ 0,
+ 0,
+ 87,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPredicate, 10,
+ OPC_SwitchType , 38, MVT::f32,
+ OPC_Scope, 17,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLD_S), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2, 2, 3,
+ 17,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLD_S), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2, 2, 3,
+ 0,
+ 38, MVT::f64,
+ OPC_Scope, 17,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2, 2, 3,
+ 17,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FLD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2, 2, 3,
+ 0,
+ 0,
+ 0,
+ 70|128,10, TARGET_VAL(ISD::STORE),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 65|128,4,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_Scope, 96|128,3,
+ OPC_MoveChild2,
+ OPC_SwitchOpcode , 58|128,2, TARGET_VAL(ISD::ADD),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 25|128,1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_Scope, 93,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_Scope, 61,
+ OPC_CheckPredicate, 15,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 16,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 18,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 18,
+ OPC_CheckPredicate, 18,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 18,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 52,
+ OPC_CheckPredicate, 13,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 15,
+ OPC_CheckPredicate, 18,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::STPTR_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 18,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::STPTR_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 0,
+ 25|128,1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_Scope, 55,
+ OPC_CheckPredicate, 15,
+ OPC_Scope, 16,
+ OPC_CheckPredicate, 16,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::STX_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 3,
+ 16,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::STX_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 3,
+ 16,
+ OPC_CheckPredicate, 18,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::STX_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 3,
+ 0,
+ 16,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::STX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 3,
+ 55,
+ OPC_CheckPredicate, 15,
+ OPC_Scope, 16,
+ OPC_CheckPredicate, 16,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::STX_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 2,
+ 16,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::STX_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 2,
+ 16,
+ OPC_CheckPredicate, 18,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::STX_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 2,
+ 0,
+ 16,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::STX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 2,
+ 0,
+ 0,
+ 27|128,1, TARGET_VAL(ISD::OR),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_Scope, 93,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_Scope, 61,
+ OPC_CheckPredicate, 15,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 16,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 18,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 18,
+ OPC_CheckPredicate, 18,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 18,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 52,
+ OPC_CheckPredicate, 13,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 15,
+ OPC_CheckPredicate, 18,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::STPTR_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 18,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::STPTR_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 0,
+ 0,
+ 90,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 14,
+ OPC_Scope, 64,
+ OPC_CheckPredicate, 15,
+ OPC_Scope, 19,
+ OPC_CheckPredicate, 16,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 3, 4,
+ 19,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 3, 4,
+ 19,
+ OPC_CheckPredicate, 18,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 3, 4,
+ 0,
+ 19,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 3, 4,
+ 0,
+ 0,
+ 118|128,1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_Scope, 41|128,1,
+ OPC_MoveChild2,
+ OPC_SwitchOpcode , 80, TARGET_VAL(ISD::ADD),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_Scope, 42,
+ OPC_CheckPredicate, 15,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 16,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 18,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 18,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 80, TARGET_VAL(ISD::OR),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_Scope, 42,
+ OPC_CheckPredicate, 15,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 16,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 18,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 18,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 0,
+ 70,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 14,
+ OPC_Scope, 44,
+ OPC_CheckPredicate, 15,
+ OPC_Scope, 19,
+ OPC_CheckPredicate, 16,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 3, 4,
+ 19,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 3, 4,
+ 0,
+ 19,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 3, 4,
+ 0,
+ 0,
+ 1|128,2,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_Scope, 79|128,1,
+ OPC_MoveChild2,
+ OPC_SwitchOpcode , 10|128,1, TARGET_VAL(ISD::ADD),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 57,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 21, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FST_S), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 21, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FST_S), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 37,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 6,
+ OPC_Scope, 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FSTX_S), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 3,
+ 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FSTX_S), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 2,
+ 0,
+ 37,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 8,
+ OPC_Scope, 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FSTX_S), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 3,
+ 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FSTX_S), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 2,
+ 0,
+ 0,
+ 59, TARGET_VAL(ISD::OR),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 21, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FST_S), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 21, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FST_S), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 0,
+ 43,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_Scope, 17,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FST_S), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 3, 4,
+ 17,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FST_S), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 3, 4,
+ 0,
+ 0,
+ 1|128,2,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_Scope, 79|128,1,
+ OPC_MoveChild2,
+ OPC_SwitchOpcode , 10|128,1, TARGET_VAL(ISD::ADD),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 57,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 21, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 21, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 37,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_Scope, 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FSTX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 3,
+ 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FSTX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 2,
+ 0,
+ 37,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 9,
+ OPC_Scope, 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FSTX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 3,
+ 12,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FSTX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 2,
+ 0,
+ 0,
+ 59, TARGET_VAL(ISD::OR),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 21, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 21, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 4, 5,
+ 0,
+ 0,
+ 43,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPredicate, 19,
+ OPC_Scope, 17,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 3, 4,
+ 17,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::FST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 1, 3, 4,
+ 0,
+ 0,
+ 0,
+ 40|128,4, TARGET_VAL(ISD::ATOMIC_LOAD),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_Scope, 113|128,2,
+ OPC_MoveChild1,
+ OPC_SwitchOpcode , 51|128,1, TARGET_VAL(ISD::ADD),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 81, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 0,
+ 81, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 0,
+ 0,
+ 51|128,1, TARGET_VAL(ISD::OR),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 81, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 3, 4,
+ 0,
+ 81, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 3, 4,
+ 0,
+ 0,
+ 0,
+ 47|128,1,
+ OPC_RecordChild1,
+ OPC_Scope, 42,
+ OPC_CheckPredicate, 7,
+ OPC_SwitchType , 17, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 17, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 3,
+ 0,
+ 42,
+ OPC_CheckPredicate, 9,
+ OPC_SwitchType , 17, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 17, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 3,
+ 0,
+ 42,
+ OPC_CheckPredicate, 12,
+ OPC_SwitchType , 17, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 17, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 3,
+ 0,
+ 42,
+ OPC_CheckPredicate, 20,
+ OPC_SwitchType , 17, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 3,
+ 17, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 3,
+ 0,
+ 0,
+ 0,
+ 87|128,4, TARGET_VAL(ISD::ATOMIC_STORE),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_Scope, 91|128,2,
+ OPC_MoveChild1,
+ OPC_SwitchOpcode , 40|128,1, TARGET_VAL(ISD::ADD),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 86, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 18,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 20,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPredicate, 21,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 20,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPredicate, 21,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 0,
+ 65, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 18,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 20,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPredicate, 21,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 0,
+ 0,
+ 40|128,1, TARGET_VAL(ISD::OR),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 86, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 18,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 20,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPredicate, 21,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 20,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPredicate, 21,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 0,
+ 65, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 18,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 20,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPredicate, 21,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 3, 4, 5,
+ 0,
+ 0,
+ 0,
+ 116|128,1,
+ OPC_RecordChild1,
+ OPC_Scope, 31|128,1,
+ OPC_RecordChild2,
+ OPC_Scope, 88,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_Scope, 19,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 2, 3, 4,
+ 19,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 2, 3, 4,
+ 21,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPredicate, 21,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 2, 3, 4,
+ 21,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPredicate, 21,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 2, 3, 4,
+ 0,
+ 66,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_Scope, 19,
+ OPC_CheckPredicate, 7,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 2, 3, 4,
+ 19,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 2, 3, 4,
+ 21,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPredicate, 21,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3, 2, 3, 4,
+ 0,
+ 0,
+ 39,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_Scope, 15,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPredicate, 22,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::PseudoAtomicStoreW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 1, 2,
+ 15,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPredicate, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::PseudoAtomicStoreD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 1, 2,
+ 0,
+ 39,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_Scope, 15,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPredicate, 22,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::PseudoAtomicStoreW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 1, 2,
+ 15,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPredicate, 22,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::PseudoAtomicStoreD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 0,
+ 0,
+ 104|128,2, TARGET_VAL(ISD::ADD),
+ OPC_Scope, 9|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 46,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 15, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i32, 2, 2, 3,
+ 15, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADDI_D), 0,
+ MVT::i64, 2, 2, 3,
+ 0,
+ 86,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 0,
+ OPC_SwitchType , 34, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 13,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ALSL_W), 0,
+ MVT::i64, 3, 1, 0, 3,
+ 13,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ALSL_D), 0,
+ MVT::i64, 3, 1, 0, 3,
+ 0,
+ 34, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 13,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ALSL_W), 0,
+ MVT::i32, 3, 1, 0, 3,
+ 13,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ALSL_D), 0,
+ MVT::i32, 3, 1, 0, 3,
+ 0,
+ 0,
+ 0,
+ 88,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 0,
+ OPC_SwitchType , 35, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 13,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ALSL_W), 0,
+ MVT::i64, 3, 0, 2, 3,
+ 13,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ALSL_D), 0,
+ MVT::i64, 3, 0, 2, 3,
+ 0,
+ 35, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 13,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ALSL_W), 0,
+ MVT::i32, 3, 0, 2, 3,
+ 13,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ALSL_D), 0,
+ MVT::i32, 3, 0, 2, 3,
+ 0,
+ 0,
+ 0|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 69,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_SwitchType , 28, MVT::i64,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i64, 2, 0, 2,
+ 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADDI_D), 0,
+ MVT::i64, 2, 0, 2,
+ 0,
+ 28, MVT::i32,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i32, 2, 0, 2,
+ 12,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADDI_D), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 26,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADD_W), 0,
+ MVT::i64, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADD_D), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 26,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADD_W), 0,
+ MVT::i32, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADD_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 0,
+ 65|128,1, TARGET_VAL(ISD::OR),
+ OPC_Scope, 85,
+ OPC_RecordChild0,
+ OPC_Scope, 46,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_SwitchType , 15, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i32, 2, 2, 3,
+ 15, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADDI_D), 0,
+ MVT::i64, 2, 2, 3,
+ 0,
+ 34,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+ OPC_RecordChild0,
+ OPC_CheckChild1Integer, 3,
+ OPC_MoveParent,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ORN), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ORN), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 35,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+ OPC_RecordChild0,
+ OPC_CheckChild1Integer, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ORN), 0,
+ MVT::i64, 2, 1, 0,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ORN), 0,
+ MVT::i32, 2, 1, 0,
+ 0,
+ 68,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 37,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 23,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ORI), 0,
+ MVT::i64, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ORI), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::OR), 0,
+ MVT::i64, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::OR), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 112, TARGET_VAL(ISD::INTRINSIC_VOID),
+ OPC_RecordNode,
+ OPC_Scope, 31,
+ OPC_CheckChild1Integer, 14|128,75,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_MoveChild4,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::CACOP), 0|OPFL_Chain,
+ 3, 4, 2, 5,
+ 22,
+ OPC_CheckChild1Integer, 70|128,75,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild3,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::LDPTE), 0|OPFL_Chain,
+ 2, 1, 3,
+ 21,
+ OPC_CheckChild1Integer, 16|128,75,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::CACOP), 0|OPFL_Chain,
+ 3, 4, 2, 5,
+ 15,
+ OPC_CheckChild1Integer, 10|128,75,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ASRTLE_D), 0|OPFL_Chain,
+ 2, 1, 2,
+ 15,
+ OPC_CheckChild1Integer, 8|128,75,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ASRTGT_D), 0|OPFL_Chain,
+ 2, 1, 2,
+ 0,
+ 94|128,25, TARGET_VAL(ISD::BRCOND),
+ OPC_RecordNode,
+ OPC_Scope, 47|128,25,
+ OPC_MoveChild1,
+ OPC_SwitchOpcode , 105|128,10, TARGET_VAL(ISD::XOR),
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
+ OPC_RecordChild0,
+ OPC_Scope, 47|128,5,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_RecordChild1,
+ OPC_Scope, 61,
+ OPC_CheckChild2CondCode, ISD::SETOEQ,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETOLT,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETOLE,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETONE,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CNE_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CNE_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETO,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_COR_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_COR_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETUEQ,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUEQ_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUEQ_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULT_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULT_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETULE,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULE_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULE_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETUNE,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUNE_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUNE_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETUO,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUN_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUN_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETLT,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 0,
+ 47|128,5,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_RecordChild1,
+ OPC_Scope, 61,
+ OPC_CheckChild2CondCode, ISD::SETOEQ,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETOLT,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETOLE,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETONE,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CNE_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CNE_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETO,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_COR_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_COR_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETUEQ,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUEQ_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUEQ_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULT_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULT_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETULE,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULE_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULE_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETUNE,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUNE_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUNE_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETUO,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUN_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUN_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 61,
+ OPC_CheckChild2CondCode, ISD::SETLT,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCEQZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 0,
+ 0,
+ 59|128,14, TARGET_VAL(ISD::SETCC),
+ OPC_RecordChild0,
+ OPC_Scope, 10|128,2,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 44,
+ OPC_CheckChild1Integer, 0,
+ OPC_Scope, 19,
+ OPC_CheckChild2CondCode, ISD::SETEQ,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BEQZ), 0|OPFL_Chain,
+ 2, 1, 2,
+ 19,
+ OPC_CheckChild2CondCode, ISD::SETNE,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BNEZ), 0|OPFL_Chain,
+ 2, 1, 2,
+ 0,
+ 85|128,1,
+ OPC_RecordChild1,
+ OPC_Scope, 20,
+ OPC_CheckChild2CondCode, ISD::SETEQ,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BEQ), 0|OPFL_Chain,
+ 3, 1, 2, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETNE,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BNE), 0|OPFL_Chain,
+ 3, 1, 2, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETLT,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BLT), 0|OPFL_Chain,
+ 3, 1, 2, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETGE,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BGE), 0|OPFL_Chain,
+ 3, 1, 2, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BLTU), 0|OPFL_Chain,
+ 3, 1, 2, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETUGE,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BGEU), 0|OPFL_Chain,
+ 3, 1, 2, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETGT,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BLT), 0|OPFL_Chain,
+ 3, 2, 1, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETLE,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BGE), 0|OPFL_Chain,
+ 3, 2, 1, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETUGT,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BLTU), 0|OPFL_Chain,
+ 3, 2, 1, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETULE,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BGEU), 0|OPFL_Chain,
+ 3, 2, 1, 3,
+ 0,
+ 0,
+ 10|128,2,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 44,
+ OPC_CheckChild1Integer, 0,
+ OPC_Scope, 19,
+ OPC_CheckChild2CondCode, ISD::SETEQ,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BEQZ), 0|OPFL_Chain,
+ 2, 1, 2,
+ 19,
+ OPC_CheckChild2CondCode, ISD::SETNE,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BNEZ), 0|OPFL_Chain,
+ 2, 1, 2,
+ 0,
+ 85|128,1,
+ OPC_RecordChild1,
+ OPC_Scope, 20,
+ OPC_CheckChild2CondCode, ISD::SETEQ,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BEQ), 0|OPFL_Chain,
+ 3, 1, 2, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETNE,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BNE), 0|OPFL_Chain,
+ 3, 1, 2, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETLT,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BLT), 0|OPFL_Chain,
+ 3, 1, 2, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETGE,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BGE), 0|OPFL_Chain,
+ 3, 1, 2, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BLTU), 0|OPFL_Chain,
+ 3, 1, 2, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETUGE,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BGEU), 0|OPFL_Chain,
+ 3, 1, 2, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETGT,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BLT), 0|OPFL_Chain,
+ 3, 2, 1, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETLE,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BGE), 0|OPFL_Chain,
+ 3, 2, 1, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETUGT,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BLTU), 0|OPFL_Chain,
+ 3, 2, 1, 3,
+ 20,
+ OPC_CheckChild2CondCode, ISD::SETULE,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BGEU), 0|OPFL_Chain,
+ 3, 2, 1, 3,
+ 0,
+ 0,
+ 14|128,5,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_RecordChild1,
+ OPC_Scope, 58,
+ OPC_CheckChild2CondCode, ISD::SETOEQ,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETOLT,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETOLE,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETONE,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CNE_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CNE_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETO,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_COR_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_COR_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETUEQ,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUEQ_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUEQ_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULT_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULT_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETULE,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULE_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULE_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETUNE,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUNE_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUNE_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETUO,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUN_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUN_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETLT,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 0,
+ 14|128,5,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_RecordChild1,
+ OPC_Scope, 58,
+ OPC_CheckChild2CondCode, ISD::SETOEQ,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETOLT,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETOLE,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETONE,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CNE_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CNE_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETO,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_COR_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_COR_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETUEQ,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUEQ_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUEQ_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULT_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULT_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETULE,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULE_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULE_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETUNE,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUNE_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUNE_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETUO,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUN_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUN_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETLT,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i64, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BCNEZ), 0|OPFL_Chain,
+ 2, 4, 3,
+ 0,
+ 0,
+ 0,
+ 0,
+ 41,
+ OPC_RecordChild1,
+ OPC_Scope, 18,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BNEZ), 0|OPFL_Chain,
+ 2, 1, 2,
+ 18,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BNEZ), 0|OPFL_Chain,
+ 2, 1, 2,
+ 0,
+ 0,
+ 17|128,1, TARGET_VAL(ISD::XOR),
+ OPC_Scope, 35,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::NOR), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::NOR), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 106,
+ OPC_RecordChild0,
+ OPC_Scope, 34,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 13, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::NOR), 0,
+ MVT::i64, 2, 0, 1,
+ 13, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::NOR), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 67,
+ OPC_RecordChild1,
+ OPC_Scope, 37,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 23,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::XORI), 0,
+ MVT::i64, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::XORI), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::XOR), 0,
+ MVT::i64, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::XOR), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 0,
+ 15|128,1, TARGET_VAL(ISD::AND),
+ OPC_Scope, 35,
+ OPC_RecordChild0,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+ OPC_RecordChild0,
+ OPC_CheckChild1Integer, 3,
+ OPC_MoveParent,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ANDN), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ANDN), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 35,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+ OPC_RecordChild0,
+ OPC_CheckChild1Integer, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ANDN), 0,
+ MVT::i64, 2, 1, 0,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ANDN), 0,
+ MVT::i32, 2, 1, 0,
+ 0,
+ 68,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 37,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 23,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ANDI), 0,
+ MVT::i64, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ANDI), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AND), 0,
+ MVT::i64, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AND), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 122, TARGET_VAL(ISD::CTLZ),
+ OPC_Scope, 63,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+ OPC_RecordChild0,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CLO_D), 0,
+ MVT::i64, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CLO_W), 0,
+ MVT::i64, 1, 0,
+ 0,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CLO_D), 0,
+ MVT::i32, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CLO_W), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 0,
+ 55,
+ OPC_RecordChild0,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CLZ_D), 0,
+ MVT::i64, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CLZ_W), 0,
+ MVT::i64, 1, 0,
+ 0,
+ 24, MVT::i32,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CLZ_D), 0,
+ MVT::i32, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CLZ_W), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 0,
+ 0,
+ 122, TARGET_VAL(ISD::CTTZ),
+ OPC_Scope, 63,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+ OPC_RecordChild0,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 25, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CTO_D), 0,
+ MVT::i64, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CTO_W), 0,
+ MVT::i64, 1, 0,
+ 0,
+ 25, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CTO_D), 0,
+ MVT::i32, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CTO_W), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 0,
+ 55,
+ OPC_RecordChild0,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CTZ_D), 0,
+ MVT::i64, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CTZ_W), 0,
+ MVT::i64, 1, 0,
+ 0,
+ 24, MVT::i32,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CTZ_D), 0,
+ MVT::i32, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CTZ_W), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 0,
+ 0,
+ 70, TARGET_VAL(LoongArchISD::CLZ_W),
+ OPC_Scope, 37,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+ OPC_RecordChild0,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CLO_W), 0,
+ MVT::i64, 1, 0,
+ 12, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CLO_W), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 29,
+ OPC_RecordChild0,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CLZ_W), 0,
+ MVT::i64, 1, 0,
+ 11, MVT::i32,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CLZ_W), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 0,
+ 70, TARGET_VAL(LoongArchISD::CTZ_W),
+ OPC_Scope, 37,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+ OPC_RecordChild0,
+ OPC_CheckChild1Integer, 3,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CTO_W), 0,
+ MVT::i64, 1, 0,
+ 12, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CTO_W), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 29,
+ OPC_RecordChild0,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CTZ_W), 0,
+ MVT::i64, 1, 0,
+ 11, MVT::i32,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CTZ_W), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 0,
+ 7|128,1, TARGET_VAL(LoongArchISD::BSTRINS),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_Scope, 62,
+ OPC_CheckPredicate, 1,
+ OPC_SwitchType , 27, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild3,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BSTRINS_W), 0,
+ MVT::i64, 4, 0, 1, 4, 5,
+ 27, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild3,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BSTRINS_W), 0,
+ MVT::i32, 4, 0, 1, 4, 5,
+ 0,
+ 62,
+ OPC_CheckPredicate, 2,
+ OPC_SwitchType , 27, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild3,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BSTRINS_D), 0,
+ MVT::i64, 4, 0, 1, 4, 5,
+ 27, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild3,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BSTRINS_D), 0,
+ MVT::i32, 4, 0, 1, 4, 5,
+ 0,
+ 0,
+ 34|128,3, TARGET_VAL(ISD::INTRINSIC_W_CHAIN),
+ OPC_RecordNode,
+ OPC_Scope, 28,
+ OPC_CheckChild1Integer, 98|128,75,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild5,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoMaskedAtomicSwap32), 0|OPFL_Chain,
+ MVT::i64, MVT::i64, 4, 1, 2, 3, 4,
+ 28,
+ OPC_CheckChild1Integer, 74|128,75,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild5,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoMaskedAtomicLoadAdd32), 0|OPFL_Chain,
+ MVT::i64, MVT::i64, 4, 1, 2, 3, 4,
+ 28,
+ OPC_CheckChild1Integer, 86|128,75,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild5,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoMaskedAtomicLoadSub32), 0|OPFL_Chain,
+ MVT::i64, MVT::i64, 4, 1, 2, 3, 4,
+ 28,
+ OPC_CheckChild1Integer, 82|128,75,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild5,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoMaskedAtomicLoadNand32), 0|OPFL_Chain,
+ MVT::i64, MVT::i64, 4, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Integer, 90|128,75,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild5,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo, TARGET_VAL(LoongArch::PseudoMaskedAtomicLoadUMax32), 0|OPFL_Chain,
+ 3, MVT::i64, MVT::i64, MVT::i64, 4, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Integer, 94|128,75,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild5,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo, TARGET_VAL(LoongArch::PseudoMaskedAtomicLoadUMin32), 0|OPFL_Chain,
+ 3, MVT::i64, MVT::i64, MVT::i64, 4, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Integer, 100|128,75,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_RecordChild6,
+ OPC_MoveChild6,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoMaskedCmpXchg32), 0|OPFL_Chain,
+ MVT::i64, MVT::i64, 5, 1, 2, 3, 4, 5,
+ 32,
+ OPC_CheckChild1Integer, 76|128,75,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_RecordChild6,
+ OPC_MoveChild6,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo, TARGET_VAL(LoongArch::PseudoMaskedAtomicLoadMax32), 0|OPFL_Chain,
+ 3, MVT::i64, MVT::i64, MVT::i64, 5, 1, 2, 3, 4, 5,
+ 32,
+ OPC_CheckChild1Integer, 78|128,75,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_RecordChild6,
+ OPC_MoveChild6,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo, TARGET_VAL(LoongArch::PseudoMaskedAtomicLoadMin32), 0|OPFL_Chain,
+ 3, MVT::i64, MVT::i64, MVT::i64, 5, 1, 2, 3, 4, 5,
+ 28,
+ OPC_CheckChild1Integer, 96|128,75,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild5,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoMaskedAtomicSwap32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 4, 1, 2, 3, 4,
+ 28,
+ OPC_CheckChild1Integer, 72|128,75,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild5,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoMaskedAtomicLoadAdd32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 4, 1, 2, 3, 4,
+ 28,
+ OPC_CheckChild1Integer, 84|128,75,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild5,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoMaskedAtomicLoadSub32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 4, 1, 2, 3, 4,
+ 28,
+ OPC_CheckChild1Integer, 80|128,75,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild5,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoMaskedAtomicLoadNand32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 4, 1, 2, 3, 4,
+ 23,
+ OPC_CheckChild1Integer, 68|128,75,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild3,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::LDDIR), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 3,
+ 0,
+ 88|128,1, TARGET_VAL(ISD::SIGN_EXTEND_INREG),
+ OPC_Scope, 6|128,1,
+ OPC_MoveChild0,
+ OPC_SwitchOpcode , 45, TARGET_VAL(ISD::ADD),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 24,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild1,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i64, 2, 0, 2,
+ 15,
+ OPC_MoveParent,
+ OPC_MoveChild1,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADD_W), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 28, TARGET_VAL(ISD::ROTR),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild1,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTRI_W), 0,
+ MVT::i64, 2, 0, 2,
+ 29, TARGET_VAL(LoongArchISD::ROTL_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild1,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTRI_W), 0,
+ MVT::i64, 2, 0, 3,
+ 17, TARGET_VAL(ISD::SUB),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild1,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SUB_W), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 77,
+ OPC_RecordChild0,
+ OPC_MoveChild1,
+ OPC_Scope, 27,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::EXT_W_B), 0,
+ MVT::i64, 1, 0,
+ 9, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::EXT_W_B), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 27,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::EXT_W_H), 0,
+ MVT::i64, 1, 0,
+ 9, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::EXT_W_H), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 16,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 85, TARGET_VAL(ISD::BRIND),
+ OPC_RecordNode,
+ OPC_Scope, 45,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 24,
+ OPC_MoveParent,
+ OPC_SwitchType , 13, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoBRIND), 0|OPFL_Chain,
+ 2, 1, 3,
+ 13, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoBRIND), 0|OPFL_Chain,
+ 2, 1, 3,
+ 0,
+ 35,
+ OPC_RecordChild1,
+ OPC_Scope, 15,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoBRIND), 0|OPFL_Chain,
+ 2, 1, 2,
+ 15,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoBRIND), 0|OPFL_Chain,
+ 2, 1, 2,
+ 0,
+ 0,
+ 21, TARGET_VAL(ISD::CALLSEQ_START),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ADJCALLSTACKDOWN), 0|OPFL_Chain|OPFL_GlueOutput,
+ 2, 1, 2,
+ 22, TARGET_VAL(ISD::CALLSEQ_END),
+ OPC_RecordNode,
+ OPC_CaptureGlueInput,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::ADJCALLSTACKUP), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput,
+ 2, 1, 2,
+ 39, TARGET_VAL(ISD::ATOMIC_FENCE),
+ OPC_RecordNode,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+ OPC_MoveParent,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::DBAR), 0|OPFL_Chain,
+ 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::DBAR), 0|OPFL_Chain,
+ 1, 1,
+ 0,
+ 111|128,12, TARGET_VAL(ISD::SETCC),
+ OPC_RecordChild0,
+ OPC_Scope, 52|128,3,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_Scope, 38,
+ OPC_CheckChild1Integer, 0,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 15,
+ OPC_CheckChild2CondCode, ISD::SETEQ,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitInteger, MVT::i64, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTUI), 0,
+ MVT::i64, 2, 0, 1,
+ 15,
+ OPC_CheckChild2CondCode, ISD::SETNE,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i64, 2, 1, 0,
+ 0,
+ 7|128,3,
+ OPC_RecordChild1,
+ OPC_Scope, 42|128,1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 14,
+ OPC_CheckChild2CondCode, ISD::SETLT,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTI), 0,
+ MVT::i64, 2, 0, 2,
+ 14,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTUI), 0,
+ MVT::i64, 2, 0, 2,
+ 0,
+ 125,
+ OPC_CheckPredicate, 25,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 58,
+ OPC_CheckChild2CondCode, ISD::SETEQ,
+ OPC_Scope, 26,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i64, 2, 0, 3,
+ OPC_EmitInteger, MVT::i64, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTUI), 0,
+ MVT::i64, 2, 4, 5,
+ 26,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_D), 0,
+ MVT::i64, 2, 0, 3,
+ OPC_EmitInteger, MVT::i64, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTUI), 0,
+ MVT::i64, 2, 4, 5,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETNE,
+ OPC_Scope, 26,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 3,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i64, 2, 0, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i64, 2, 2, 5,
+ 26,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 3,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_D), 0,
+ MVT::i64, 2, 0, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i64, 2, 2, 5,
+ 0,
+ 0,
+ 0,
+ 14,
+ OPC_CheckChild2CondCode, ISD::SETLT,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLT), 0,
+ MVT::i64, 2, 0, 1,
+ 14,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i64, 2, 0, 1,
+ 14,
+ OPC_CheckChild2CondCode, ISD::SETUGT,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i64, 2, 1, 0,
+ 14,
+ OPC_CheckChild2CondCode, ISD::SETGT,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLT), 0,
+ MVT::i64, 2, 1, 0,
+ 25,
+ OPC_CheckChild2CondCode, ISD::SETEQ,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::XOR), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_EmitInteger, MVT::i64, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTUI), 0,
+ MVT::i64, 2, 2, 3,
+ 25,
+ OPC_CheckChild2CondCode, ISD::SETNE,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::XOR), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i64, 2, 2, 3,
+ 25,
+ OPC_CheckChild2CondCode, ISD::SETUGE,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_EmitInteger, MVT::i64, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::XORI), 0,
+ MVT::i64, 2, 2, 3,
+ 25,
+ OPC_CheckChild2CondCode, ISD::SETULE,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i64, 2, 1, 0,
+ OPC_EmitInteger, MVT::i64, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::XORI), 0,
+ MVT::i64, 2, 2, 3,
+ 25,
+ OPC_CheckChild2CondCode, ISD::SETGE,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::SLT), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_EmitInteger, MVT::i64, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::XORI), 0,
+ MVT::i64, 2, 2, 3,
+ 25,
+ OPC_CheckChild2CondCode, ISD::SETLE,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::SLT), 0,
+ MVT::i64, 2, 1, 0,
+ OPC_EmitInteger, MVT::i64, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::XORI), 0,
+ MVT::i64, 2, 2, 3,
+ 0,
+ 0,
+ 52|128,3,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_Scope, 38,
+ OPC_CheckChild1Integer, 0,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 15,
+ OPC_CheckChild2CondCode, ISD::SETEQ,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTUI), 0,
+ MVT::i32, 2, 0, 1,
+ 15,
+ OPC_CheckChild2CondCode, ISD::SETNE,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i32, 2, 1, 0,
+ 0,
+ 7|128,3,
+ OPC_RecordChild1,
+ OPC_Scope, 42|128,1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 14,
+ OPC_CheckChild2CondCode, ISD::SETLT,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTI), 0,
+ MVT::i32, 2, 0, 2,
+ 14,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTUI), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 125,
+ OPC_CheckPredicate, 25,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 58,
+ OPC_CheckChild2CondCode, ISD::SETEQ,
+ OPC_Scope, 26,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i32, 2, 0, 3,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTUI), 0,
+ MVT::i32, 2, 4, 5,
+ 26,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_D), 0,
+ MVT::i32, 2, 0, 3,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTUI), 0,
+ MVT::i32, 2, 4, 5,
+ 0,
+ 58,
+ OPC_CheckChild2CondCode, ISD::SETNE,
+ OPC_Scope, 26,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 3,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i32, 2, 0, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i32, 2, 2, 5,
+ 26,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 3,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_D), 0,
+ MVT::i32, 2, 0, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i32, 2, 2, 5,
+ 0,
+ 0,
+ 0,
+ 14,
+ OPC_CheckChild2CondCode, ISD::SETLT,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLT), 0,
+ MVT::i32, 2, 0, 1,
+ 14,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i32, 2, 0, 1,
+ 14,
+ OPC_CheckChild2CondCode, ISD::SETUGT,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i32, 2, 1, 0,
+ 14,
+ OPC_CheckChild2CondCode, ISD::SETGT,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLT), 0,
+ MVT::i32, 2, 1, 0,
+ 25,
+ OPC_CheckChild2CondCode, ISD::SETEQ,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::XOR), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTUI), 0,
+ MVT::i32, 2, 2, 3,
+ 25,
+ OPC_CheckChild2CondCode, ISD::SETNE,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::XOR), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i32, 2, 2, 3,
+ 25,
+ OPC_CheckChild2CondCode, ISD::SETUGE,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::XORI), 0,
+ MVT::i32, 2, 2, 3,
+ 25,
+ OPC_CheckChild2CondCode, ISD::SETULE,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::SLTU), 0,
+ MVT::i32, 2, 1, 0,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::XORI), 0,
+ MVT::i32, 2, 2, 3,
+ 25,
+ OPC_CheckChild2CondCode, ISD::SETGE,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::SLT), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::XORI), 0,
+ MVT::i32, 2, 2, 3,
+ 25,
+ OPC_CheckChild2CondCode, ISD::SETLE,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::SLT), 0,
+ MVT::i32, 2, 1, 0,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::XORI), 0,
+ MVT::i32, 2, 2, 3,
+ 0,
+ 0,
+ 126|128,2,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_RecordChild1,
+ OPC_Scope, 28,
+ OPC_CheckChild2CondCode, ISD::SETOEQ,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETEQ,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETOLT,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETOLE,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETLE,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETONE,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CNE_S), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CNE_S), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETO,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_COR_S), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_COR_S), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETUEQ,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUEQ_S), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUEQ_S), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULT_S), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULT_S), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETULE,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULE_S), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULE_S), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETUNE,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUNE_S), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUNE_S), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETUO,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUN_S), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUN_S), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETLT,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 126|128,2,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_RecordChild1,
+ OPC_Scope, 28,
+ OPC_CheckChild2CondCode, ISD::SETOEQ,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETEQ,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETOLT,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETOLE,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETLE,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETONE,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CNE_D), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CNE_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETO,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_COR_D), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_COR_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETUEQ,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUEQ_D), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUEQ_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULT_D), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULT_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETULE,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULE_D), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULE_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETUNE,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUNE_D), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUNE_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETUO,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUN_D), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUN_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild2CondCode, ISD::SETLT,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i64, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 0,
+ 19|128,1, TARGET_VAL(ISD::ROTR),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 84,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 1,
+ OPC_SwitchType , 15, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTRI_W), 0,
+ MVT::i64, 2, 0, 2,
+ 15, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTRI_W), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 38,
+ OPC_CheckPredicate, 2,
+ OPC_SwitchType , 15, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTRI_D), 0,
+ MVT::i64, 2, 0, 2,
+ 15, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTRI_D), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 28,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTR_W), 0,
+ MVT::i64, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTR_D), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 28,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTR_W), 0,
+ MVT::i32, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTR_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 24, TARGET_VAL(LoongArchISD::ROTL_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTRI_W), 0,
+ MVT::i64, 2, 0, 3,
+ 31|128,1, TARGET_VAL(ISD::SHL),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 84,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 1,
+ OPC_SwitchType , 15, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLLI_W), 0,
+ MVT::i64, 2, 0, 2,
+ 15, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLLI_W), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 38,
+ OPC_CheckPredicate, 2,
+ OPC_SwitchType , 15, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLLI_D), 0,
+ MVT::i64, 2, 0, 2,
+ 15, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLLI_D), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 34,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 13,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLL_W), 0,
+ MVT::i64, 2, 0, 2,
+ 13,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLL_D), 0,
+ MVT::i64, 2, 0, 2,
+ 0,
+ 34,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 13,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLL_W), 0,
+ MVT::i32, 2, 0, 2,
+ 13,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLL_D), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 31|128,1, TARGET_VAL(ISD::SRA),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 84,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 1,
+ OPC_SwitchType , 15, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRAI_W), 0,
+ MVT::i64, 2, 0, 2,
+ 15, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRAI_W), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 38,
+ OPC_CheckPredicate, 2,
+ OPC_SwitchType , 15, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRAI_D), 0,
+ MVT::i64, 2, 0, 2,
+ 15, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRAI_D), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 34,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 13,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRA_W), 0,
+ MVT::i64, 2, 0, 2,
+ 13,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRA_D), 0,
+ MVT::i64, 2, 0, 2,
+ 0,
+ 34,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 13,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRA_W), 0,
+ MVT::i32, 2, 0, 2,
+ 13,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRA_D), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 31|128,1, TARGET_VAL(ISD::SRL),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 84,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 1,
+ OPC_SwitchType , 15, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRLI_W), 0,
+ MVT::i64, 2, 0, 2,
+ 15, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRLI_W), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 38,
+ OPC_CheckPredicate, 2,
+ OPC_SwitchType , 15, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRLI_D), 0,
+ MVT::i64, 2, 0, 2,
+ 15, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRLI_D), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 34,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 13,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRL_W), 0,
+ MVT::i64, 2, 0, 2,
+ 13,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRL_D), 0,
+ MVT::i64, 2, 0, 2,
+ 0,
+ 34,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 13,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRL_W), 0,
+ MVT::i32, 2, 0, 2,
+ 13,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRL_D), 0,
+ MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 38, TARGET_VAL(LoongArchISD::DBAR),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 26,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::DBAR), 0|OPFL_Chain,
+ 1, 2,
+ 12, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::DBAR), 0|OPFL_Chain,
+ 1, 2,
+ 0,
+ 38, TARGET_VAL(LoongArchISD::IBAR),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 26,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::IBAR), 0|OPFL_Chain,
+ 1, 2,
+ 12, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::IBAR), 0|OPFL_Chain,
+ 1, 2,
+ 0,
+ 38, TARGET_VAL(LoongArchISD::BREAK),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 26,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BREAK), 0|OPFL_Chain,
+ 1, 2,
+ 12, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BREAK), 0|OPFL_Chain,
+ 1, 2,
+ 0,
+ 38, TARGET_VAL(LoongArchISD::SYSCALL),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 26,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::SYSCALL), 0|OPFL_Chain,
+ 1, 2,
+ 12, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::SYSCALL), 0|OPFL_Chain,
+ 1, 2,
+ 0,
+ 44, TARGET_VAL(LoongArchISD::CSRRD),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 27,
+ OPC_SwitchType , 15, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CSRRD), 0|OPFL_Chain,
+ MVT::i64, 1, 2,
+ 15, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CSRRD), 0|OPFL_Chain,
+ MVT::i32, 1, 2,
+ 0,
+ 47, TARGET_VAL(LoongArchISD::CSRWR),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 27,
+ OPC_SwitchType , 16, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CSRWR), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 3,
+ 16, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CSRWR), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 3,
+ 0,
+ 50, TARGET_VAL(LoongArchISD::CSRXCHG),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild3,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 27,
+ OPC_SwitchType , 17, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CSRXCHG), 0|OPFL_Chain,
+ MVT::i64, 3, 1, 2, 4,
+ 17, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CSRXCHG), 0|OPFL_Chain,
+ MVT::i32, 3, 1, 2, 4,
+ 0,
+ 46, TARGET_VAL(LoongArchISD::MOVGR2FCSR),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 28,
+ OPC_SwitchType , 16, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::WRFCSR), 0|OPFL_Chain,
+ 2, 3, 2,
+ 16, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::WRFCSR), 0|OPFL_Chain,
+ 2, 3, 2,
+ 0,
+ 41, TARGET_VAL(LoongArchISD::MOVFCSR2GR),
+ OPC_RecordChild0,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+ OPC_CheckPredicate, 28,
+ OPC_SwitchType , 14, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::RDFCSR), 0,
+ MVT::i64, 1, 1,
+ 14, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::RDFCSR), 0,
+ MVT::i32, 1, 1,
+ 0,
+ 15, TARGET_VAL(LoongArchISD::SLL_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SLL_W), 0,
+ MVT::i64, 2, 0, 2,
+ 15, TARGET_VAL(LoongArchISD::SRA_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRA_W), 0,
+ MVT::i64, 2, 0, 2,
+ 15, TARGET_VAL(LoongArchISD::SRL_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SRL_W), 0,
+ MVT::i64, 2, 0, 2,
+ 91, TARGET_VAL(LoongArchISD::CALL),
+ OPC_RecordNode,
+ OPC_CaptureGlueInput,
+ OPC_RecordChild1,
+ OPC_Scope, 61,
+ OPC_MoveChild1,
+ OPC_SwitchOpcode , 26, TARGET_VAL(ISD::TargetGlobalAddress),
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoCALL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1, 1,
+ 10, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoCALL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1, 1,
+ 0,
+ 26, TARGET_VAL(ISD::TargetExternalSymbol),
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoCALL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1, 1,
+ 10, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoCALL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1, 1,
+ 0,
+ 0,
+ 11,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoCALLIndirect), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1, 1,
+ 11,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoCALLIndirect), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1, 1,
+ 0,
+ 91, TARGET_VAL(LoongArchISD::TAIL),
+ OPC_RecordNode,
+ OPC_CaptureGlueInput,
+ OPC_RecordChild1,
+ OPC_Scope, 61,
+ OPC_MoveChild1,
+ OPC_SwitchOpcode , 26, TARGET_VAL(ISD::TargetGlobalAddress),
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoTAIL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1, 1,
+ 10, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoTAIL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1, 1,
+ 0,
+ 26, TARGET_VAL(ISD::TargetExternalSymbol),
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoTAIL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1, 1,
+ 10, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoTAIL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1, 1,
+ 0,
+ 0,
+ 11,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoTAILIndirect), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1, 1,
+ 11,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoTAILIndirect), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1, 1,
+ 0,
+ 5|128,1, TARGET_VAL(ISD::BSWAP),
+ OPC_Scope, 56,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BITREVERSE),
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::i64,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_4B), 0,
+ MVT::i64, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_8B), 0,
+ MVT::i64, 1, 0,
+ 0,
+ 22, MVT::i32,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_4B), 0,
+ MVT::i32, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_8B), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 0,
+ 73,
+ OPC_RecordChild0,
+ OPC_SwitchType , 33, MVT::i64,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::REVB_D), 0,
+ MVT::i64, 1, 0,
+ 20,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::REVB_2H), 0,
+ MVT::i64, 1, 0,
+ OPC_EmitInteger, MVT::i64, 32,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTRI_W), 0,
+ MVT::i64, 2, 1, 2,
+ 0,
+ 33, MVT::i32,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::REVB_D), 0,
+ MVT::i32, 1, 0,
+ 20,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::REVB_2H), 0,
+ MVT::i32, 1, 0,
+ OPC_EmitInteger, MVT::i32, 32,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTRI_W), 0,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 0,
+ 0,
+ 111, TARGET_VAL(ISD::BITREVERSE),
+ OPC_Scope, 56,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BSWAP),
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::i64,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_4B), 0,
+ MVT::i64, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_8B), 0,
+ MVT::i64, 1, 0,
+ 0,
+ 22, MVT::i32,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_4B), 0,
+ MVT::i32, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_8B), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 0,
+ 51,
+ OPC_RecordChild0,
+ OPC_SwitchType , 22, MVT::i64,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_W), 0,
+ MVT::i64, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_D), 0,
+ MVT::i64, 1, 0,
+ 0,
+ 22, MVT::i32,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_W), 0,
+ MVT::i32, 1, 0,
+ 9,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_D), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 0,
+ 0,
+ 37|128,3, TARGET_VAL(ISD::ATOMIC_LOAD_NAND),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 77|128,1, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_Scope, 99,
+ OPC_CheckPredicate, 20,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 0,
+ 99,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 0,
+ 0,
+ 77|128,1, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 99,
+ OPC_CheckPredicate, 20,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 99,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 0,
+ 0,
+ 21|128,2, TARGET_VAL(ISD::ATOMIC_SWAP),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 5|128,1, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMSWAP_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMSWAP_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 99,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicSwap32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicSwap32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicSwap32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicSwap32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicSwap32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 0,
+ 0,
+ 5|128,1, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMSWAP_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMSWAP_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 99,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicSwap32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicSwap32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicSwap32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicSwap32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicSwap32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 0,
+ 0,
+ 17|128,2, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 3|128,1, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMADD_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 111,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMADD_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAdd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAdd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAdd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAdd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAdd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 0,
+ 0,
+ 3|128,1, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMADD_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 111,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMADD_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAdd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAdd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAdd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAdd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAdd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 0,
+ 0,
+ 21|128,2, TARGET_VAL(ISD::ATOMIC_LOAD_AND),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 5|128,1, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMAND_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMAND_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 99,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAnd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAnd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAnd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAnd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAnd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 0,
+ 0,
+ 5|128,1, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMAND_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMAND_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 99,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAnd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAnd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAnd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAnd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadAnd32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 0,
+ 0,
+ 21|128,2, TARGET_VAL(ISD::ATOMIC_LOAD_OR),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 5|128,1, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMOR_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMOR_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 99,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadOr32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadOr32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadOr32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadOr32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadOr32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 0,
+ 0,
+ 5|128,1, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMOR_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMOR_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 99,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadOr32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadOr32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadOr32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadOr32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadOr32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 0,
+ 0,
+ 21|128,2, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 5|128,1, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMXOR_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMXOR_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 99,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadXor32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadXor32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadXor32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadXor32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadXor32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 0,
+ 0,
+ 5|128,1, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMXOR_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMXOR_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 99,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadXor32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadXor32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadXor32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadXor32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadXor32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 0,
+ 0,
+ 75, TARGET_VAL(ISD::ATOMIC_LOAD_UMIN),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 33, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMIN_DB_WU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMIN_DB_DU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 0,
+ 33, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMIN_DB_WU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMIN_DB_DU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 0,
+ 0,
+ 75, TARGET_VAL(ISD::ATOMIC_LOAD_UMAX),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 33, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMAX_DB_WU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMAX_DB_DU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 0,
+ 33, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMAX_DB_WU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMAX_DB_DU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 0,
+ 0,
+ 75, TARGET_VAL(ISD::ATOMIC_LOAD_MIN),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 33, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMIN_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMIN_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 0,
+ 33, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMIN_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMIN_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 0,
+ 0,
+ 75, TARGET_VAL(ISD::ATOMIC_LOAD_MAX),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 33, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMAX_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMAX_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 2, 1,
+ 0,
+ 33, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMAX_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 13,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMMAX_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 2, 1,
+ 0,
+ 0,
+ 85, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 38, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_Scope, 15,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 15,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 0,
+ 38, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_Scope, 15,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 15,
+ OPC_CheckPredicate, 12,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 0,
+ 61|128,2, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 25|128,1, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_Scope, 122,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadSub32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadSub32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadSub32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadSub32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadSub32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3, 1, 2, 3,
+ 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::SUB_W), 0,
+ MVT::i64, 2, 3, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMADD_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 4, 1,
+ 0,
+ 24,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::SUB_D), 0,
+ MVT::i64, 2, 3, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMADD_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2, 4, 1,
+ 0,
+ 25|128,1, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 122,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadSub32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 30,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 8,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadSub32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 10,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadSub32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 12,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadSub32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_MorphNodeTo2, TARGET_VAL(LoongArch::PseudoAtomicLoadSub32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3, 1, 2, 3,
+ 22,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::SUB_W), 0,
+ MVT::i32, 2, 3, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMADD_DB_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 4, 1,
+ 0,
+ 24,
+ OPC_CheckPredicate, 20,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::SUB_D), 0,
+ MVT::i32, 2, 3, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::AMADD_DB_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2, 4, 1,
+ 0,
+ 0,
+ 7, TARGET_VAL(ISD::TRAP),
+ OPC_RecordNode,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoUNIMP), 0|OPFL_Chain,
+ 0,
+ 14, TARGET_VAL(ISD::BR),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoBR), 0|OPFL_Chain,
+ 1, 1,
+ 8, TARGET_VAL(LoongArchISD::RET),
+ OPC_RecordNode,
+ OPC_CaptureGlueInput,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::PseudoRET), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic0,
+ 0,
+ 56, TARGET_VAL(ISD::SUB),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SUB_W), 0,
+ MVT::i64, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SUB_D), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 24, MVT::i32,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SUB_W), 0,
+ MVT::i32, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::SUB_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 56, TARGET_VAL(ISD::MULHS),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MULH_W), 0,
+ MVT::i64, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MULH_D), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 24, MVT::i32,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MULH_W), 0,
+ MVT::i32, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MULH_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 56, TARGET_VAL(ISD::MULHU),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MULH_WU), 0,
+ MVT::i64, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MULH_DU), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 24, MVT::i32,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MULH_WU), 0,
+ MVT::i32, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MULH_DU), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 12, TARGET_VAL(LoongArchISD::ROTR_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::ROTR_W), 0,
+ MVT::i64, 2, 0, 1,
+ 29, TARGET_VAL(ISD::DEBUGTRAP),
+ OPC_RecordNode,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BREAK), 0|OPFL_Chain,
+ 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::BREAK), 0|OPFL_Chain,
+ 1, 1,
+ 0,
+ 29, TARGET_VAL(LoongArchISD::REVB_2H),
+ OPC_RecordChild0,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::REVB_2H), 0,
+ MVT::i64, 1, 0,
+ 11, MVT::i32,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::REVB_2H), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 29, TARGET_VAL(LoongArchISD::BITREV_4B),
+ OPC_RecordChild0,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_4B), 0,
+ MVT::i64, 1, 0,
+ 11, MVT::i32,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_4B), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 29, TARGET_VAL(LoongArchISD::REVB_2W),
+ OPC_RecordChild0,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::REVB_2W), 0,
+ MVT::i64, 1, 0,
+ 11, MVT::i32,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::REVB_2W), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 29, TARGET_VAL(LoongArchISD::BITREV_W),
+ OPC_RecordChild0,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_W), 0,
+ MVT::i64, 1, 0,
+ 11, MVT::i32,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::BITREV_W), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 12, TARGET_VAL(LoongArchISD::CRC_W_B_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CRC_W_B_W), 0,
+ MVT::i64, 2, 0, 1,
+ 12, TARGET_VAL(LoongArchISD::CRC_W_H_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CRC_W_H_W), 0,
+ MVT::i64, 2, 0, 1,
+ 12, TARGET_VAL(LoongArchISD::CRC_W_W_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CRC_W_W_W), 0,
+ MVT::i64, 2, 0, 1,
+ 12, TARGET_VAL(LoongArchISD::CRC_W_D_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CRC_W_D_W), 0,
+ MVT::i64, 2, 0, 1,
+ 12, TARGET_VAL(LoongArchISD::CRCC_W_B_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CRCC_W_B_W), 0,
+ MVT::i64, 2, 0, 1,
+ 12, TARGET_VAL(LoongArchISD::CRCC_W_H_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CRCC_W_H_W), 0,
+ MVT::i64, 2, 0, 1,
+ 12, TARGET_VAL(LoongArchISD::CRCC_W_W_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CRCC_W_W_W), 0,
+ MVT::i64, 2, 0, 1,
+ 12, TARGET_VAL(LoongArchISD::CRCC_W_D_W),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CRCC_W_D_W), 0,
+ MVT::i64, 2, 0, 1,
+ 84|128,6, TARGET_VAL(ISD::STRICT_FSETCC),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 38|128,3,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_MoveChild3,
+ OPC_Scope, 31,
+ OPC_CheckCondCode, ISD::SETOEQ,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETEQ,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETOLT,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETOLE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETLE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETONE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CNE_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CNE_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETO,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_COR_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_COR_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETUEQ,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUEQ_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUEQ_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETULT,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULT_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULT_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETULE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULE_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULE_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETUNE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUNE_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUNE_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETUO,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUN_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUN_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETLT,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 0,
+ 38|128,3,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_MoveChild3,
+ OPC_Scope, 31,
+ OPC_CheckCondCode, ISD::SETOEQ,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETEQ,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETOLT,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETOLE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETLE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETONE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CNE_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CNE_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETO,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_COR_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_COR_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETUEQ,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUEQ_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUEQ_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETULT,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULT_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULT_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETULE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULE_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CULE_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETUNE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUNE_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUNE_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETUO,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUN_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CUN_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETLT,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 0,
+ 0,
+ 84|128,5, TARGET_VAL(ISD::STRICT_FSETCCS),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 102|128,2,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_MoveChild3,
+ OPC_Scope, 31,
+ OPC_CheckCondCode, ISD::SETOEQ,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SEQ_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SEQ_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETOLT,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SLT_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SLT_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETOLE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SLE_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SLE_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETONE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SNE_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SNE_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETO,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SOR_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SOR_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETUEQ,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SUEQ_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SUEQ_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETULT,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SULT_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SULT_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETULE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SULE_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SULE_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETUNE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SUNE_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SUNE_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETUO,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SUN_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SUN_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETLT,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SLT_S), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SLT_S), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 0,
+ 102|128,2,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_MoveChild3,
+ OPC_Scope, 31,
+ OPC_CheckCondCode, ISD::SETOEQ,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SEQ_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SEQ_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETOLT,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SLT_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SLT_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETOLE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SLE_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SLE_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETONE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SNE_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SNE_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETO,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SOR_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SOR_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETUEQ,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SUEQ_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SUEQ_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETULT,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SULT_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SULT_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETULE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SULE_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SULE_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETUNE,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SUNE_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SUNE_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETUO,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SUN_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SUN_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 31,
+ OPC_CheckCondCode, ISD::SETLT,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SLT_D), 0|OPFL_Chain,
+ MVT::i64, 2, 1, 2,
+ 11, MVT::i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCMP_SLT_D), 0|OPFL_Chain,
+ MVT::i32, 2, 1, 2,
+ 0,
+ 0,
+ 0,
+ 10, TARGET_VAL(LoongArchISD::MOVFR2GR_S_LA64),
+ OPC_RecordChild0,
+ OPC_CheckPatternPredicate, 10,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVFR2GR_S), 0,
+ MVT::i64, 1, 0,
+ 85, TARGET_VAL(ISD::BITCAST),
+ OPC_RecordChild0,
+ OPC_Scope, 13,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVFR2GR_S), 0,
+ MVT::i32, 1, 0,
+ 26,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_SwitchType , 9, MVT::i64,
+ OPC_CheckPatternPredicate, 12,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVFR2GR_D), 0,
+ MVT::i64, 1, 0,
+ 9, MVT::i32,
+ OPC_CheckPatternPredicate, 13,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVFR2GR_D), 0,
+ MVT::i32, 1, 0,
+ 0,
+ 26,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_SwitchType , 9, MVT::f32,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 0,
+ 9, MVT::f64,
+ OPC_CheckPatternPredicate, 13,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVGR2FR_D), 0,
+ MVT::f64, 1, 0,
+ 0,
+ 13,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 12,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVGR2FR_D), 0,
+ MVT::f64, 1, 0,
+ 0,
+ 32, TARGET_VAL(LoongArchISD::IOCSRRD_B),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::IOCSRRD_B), 0|OPFL_Chain,
+ MVT::i64, 1, 1,
+ 12, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::IOCSRRD_B), 0|OPFL_Chain,
+ MVT::i32, 1, 1,
+ 0,
+ 32, TARGET_VAL(LoongArchISD::IOCSRRD_H),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::IOCSRRD_H), 0|OPFL_Chain,
+ MVT::i64, 1, 1,
+ 12, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::IOCSRRD_H), 0|OPFL_Chain,
+ MVT::i32, 1, 1,
+ 0,
+ 32, TARGET_VAL(LoongArchISD::IOCSRRD_W),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::IOCSRRD_W), 0|OPFL_Chain,
+ MVT::i64, 1, 1,
+ 12, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::IOCSRRD_W), 0|OPFL_Chain,
+ MVT::i32, 1, 1,
+ 0,
+ 32, TARGET_VAL(LoongArchISD::IOCSRWR_B),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 13,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::IOCSRWR_B), 0|OPFL_Chain,
+ 2, 1, 2,
+ 13,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::IOCSRWR_B), 0|OPFL_Chain,
+ 2, 1, 2,
+ 0,
+ 32, TARGET_VAL(LoongArchISD::IOCSRWR_H),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 13,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::IOCSRWR_H), 0|OPFL_Chain,
+ 2, 1, 2,
+ 13,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::IOCSRWR_H), 0|OPFL_Chain,
+ 2, 1, 2,
+ 0,
+ 32, TARGET_VAL(LoongArchISD::IOCSRWR_W),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 13,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::IOCSRWR_W), 0|OPFL_Chain,
+ 2, 1, 2,
+ 13,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::IOCSRWR_W), 0|OPFL_Chain,
+ 2, 1, 2,
+ 0,
+ 32, TARGET_VAL(LoongArchISD::CPUCFG),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CPUCFG), 0|OPFL_Chain,
+ MVT::i64, 1, 1,
+ 12, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::CPUCFG), 0|OPFL_Chain,
+ MVT::i32, 1, 1,
+ 0,
+ 32, TARGET_VAL(LoongArchISD::IOCSRRD_D),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 12, MVT::i64,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::IOCSRRD_D), 0|OPFL_Chain,
+ MVT::i64, 1, 1,
+ 12, MVT::i32,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::IOCSRRD_D), 0|OPFL_Chain,
+ MVT::i32, 1, 1,
+ 0,
+ 32, TARGET_VAL(LoongArchISD::IOCSRWR_D),
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 13,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::IOCSRWR_D), 0|OPFL_Chain,
+ 2, 1, 2,
+ 13,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains1_0,
+ OPC_MorphNodeTo0, TARGET_VAL(LoongArch::IOCSRWR_D), 0|OPFL_Chain,
+ 2, 1, 2,
+ 0,
+ 23|128,10, TARGET_VAL(ISD::SELECT),
+ OPC_Scope, 67,
+ OPC_RecordChild0,
+ OPC_SwitchType , 30, MVT::i64,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MASKEQZ), 0,
+ MVT::i64, 2, 1, 0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MASKNEZ), 0,
+ MVT::i64, 2, 2, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::OR), 0,
+ MVT::i64, 2, 3, 4,
+ 30, MVT::i32,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MASKEQZ), 0,
+ MVT::i32, 2, 1, 0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MASKNEZ), 0,
+ MVT::i32, 2, 2, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::OR), 0,
+ MVT::i32, 2, 3, 4,
+ 0,
+ 9|128,9,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
+ OPC_RecordChild0,
+ OPC_Scope, 63|128,4,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_RecordChild1,
+ OPC_Scope, 56,
+ OPC_CheckChild2CondCode, ISD::SETOEQ,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CEQ_S), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETOLT,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_S), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETOLE,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLE_S), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETONE,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CNE_S), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CNE_S), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETO,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_COR_S), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_COR_S), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETUEQ,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUEQ_S), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUEQ_S), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULT_S), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULT_S), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETULE,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULE_S), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULE_S), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETUNE,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUNE_S), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUNE_S), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETUO,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUN_S), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUN_S), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 3, 2, 4,
+ 0,
+ 0,
+ 63|128,4,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_RecordChild1,
+ OPC_Scope, 56,
+ OPC_CheckChild2CondCode, ISD::SETOEQ,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CEQ_D), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETOLT,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLT_D), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETOLE,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CLE_D), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETONE,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CNE_D), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CNE_D), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETO,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_COR_D), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_COR_D), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETUEQ,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUEQ_D), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUEQ_D), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETULT,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULT_D), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULT_D), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETULE,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULE_D), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CULE_D), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETUNE,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUNE_D), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUNE_D), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 0,
+ 56,
+ OPC_CheckChild2CondCode, ISD::SETUO,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUN_D), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 24, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCMP_CUN_D), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 3, 2, 4,
+ 0,
+ 0,
+ 0,
+ 69,
+ OPC_RecordChild0,
+ OPC_Scope, 32,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 11, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 2, 1, 0,
+ 11, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 2, 1, 0,
+ 0,
+ 32,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 11, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_S), 0,
+ MVT::f32, 3, 2, 1, 0,
+ 11, MVT::f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSEL_D), 0,
+ MVT::f64, 3, 2, 1, 0,
+ 0,
+ 0,
+ 0,
+ 56, TARGET_VAL(ISD::SDIV),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::DIV_W), 0,
+ MVT::i64, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::DIV_D), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 24, MVT::i32,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::DIV_W), 0,
+ MVT::i32, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::DIV_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 56, TARGET_VAL(ISD::UDIV),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::DIV_WU), 0,
+ MVT::i64, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::DIV_DU), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 24, MVT::i32,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::DIV_WU), 0,
+ MVT::i32, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::DIV_DU), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 56, TARGET_VAL(ISD::SREM),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOD_W), 0,
+ MVT::i64, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOD_D), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 24, MVT::i32,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOD_W), 0,
+ MVT::i32, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOD_D), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 56, TARGET_VAL(ISD::UREM),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 24, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOD_WU), 0,
+ MVT::i64, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOD_DU), 0,
+ MVT::i64, 2, 0, 1,
+ 0,
+ 24, MVT::i32,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOD_WU), 0,
+ MVT::i32, 2, 0, 1,
+ 10,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOD_DU), 0,
+ MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 98, TARGET_VAL(ISD::FDIV),
+ OPC_Scope, 66,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::ConstantFP),
+ OPC_CheckPredicate, 34,
+ OPC_MoveParent,
+ OPC_Scope, 30,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::FSQRT),
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FRSQRT_S), 0,
+ MVT::f32, 1, 0,
+ 9, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FRSQRT_D), 0,
+ MVT::f64, 1, 0,
+ 0,
+ 25,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FRECIP_S), 0,
+ MVT::f32, 1, 0,
+ 9, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FRECIP_D), 0,
+ MVT::f64, 1, 0,
+ 0,
+ 0,
+ 28,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FDIV_S), 0,
+ MVT::f32, 2, 0, 1,
+ 10, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FDIV_D), 0,
+ MVT::f64, 2, 0, 1,
+ 0,
+ 0,
+ 123|128,1, TARGET_VAL(ISD::FMA),
+ OPC_Scope, 43,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 35,
+ OPC_SwitchType , 11, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNMADD_S), 0,
+ MVT::f32, 3, 0, 1, 2,
+ 11, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNMADD_D), 0,
+ MVT::f64, 3, 0, 1, 2,
+ 0,
+ 67,
+ OPC_RecordChild0,
+ OPC_Scope, 42,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 35,
+ OPC_SwitchType , 11, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNMADD_S), 0,
+ MVT::f32, 3, 1, 0, 2,
+ 11, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNMADD_D), 0,
+ MVT::f64, 3, 1, 0, 2,
+ 0,
+ 20,
+ OPC_RecordChild1,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FMSUB_S), 0,
+ MVT::f32, 3, 0, 1, 2,
+ 0,
+ 21,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNMSUB_S), 0,
+ MVT::f32, 3, 0, 1, 2,
+ 21,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild2,
+ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FMSUB_D), 0,
+ MVT::f64, 3, 0, 1, 2,
+ 21,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNMSUB_D), 0,
+ MVT::f64, 3, 0, 1, 2,
+ 70,
+ OPC_RecordChild0,
+ OPC_Scope, 35,
+ OPC_MoveChild1,
+ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_SwitchType , 11, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNMSUB_S), 0,
+ MVT::f32, 3, 1, 0, 2,
+ 11, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNMSUB_D), 0,
+ MVT::f64, 3, 1, 0, 2,
+ 0,
+ 30,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 11, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FMADD_S), 0,
+ MVT::f32, 3, 0, 1, 2,
+ 11, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FMADD_D), 0,
+ MVT::f64, 3, 0, 1, 2,
+ 0,
+ 0,
+ 0,
+ 41|128,1, TARGET_VAL(ISD::SINT_TO_FP),
+ OPC_RecordChild0,
+ OPC_Scope, 84,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_SwitchType , 39, MVT::f32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 10,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FFINT_S_W), 0,
+ MVT::f32, 1, 2,
+ 16,
+ OPC_CheckPatternPredicate, 12,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_D), 0,
+ MVT::f64, 1, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FFINT_S_L), 0,
+ MVT::f32, 1, 1,
+ 0,
+ 37, MVT::f64,
+ OPC_CheckPatternPredicate, 12,
+ OPC_Scope, 17,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FFINT_D_W), 0,
+ MVT::f64, 1, 2,
+ 14,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_D), 0,
+ MVT::f64, 1, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FFINT_D_L), 0,
+ MVT::f64, 1, 1,
+ 0,
+ 0,
+ 80,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_SwitchType , 36, MVT::f32,
+ OPC_Scope, 16,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FFINT_S_W), 0,
+ MVT::f32, 1, 1,
+ 16,
+ OPC_CheckPatternPredicate, 13,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_D), 0,
+ MVT::f64, 1, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FFINT_S_L), 0,
+ MVT::f32, 1, 1,
+ 0,
+ 36, MVT::f64,
+ OPC_Scope, 16,
+ OPC_CheckPatternPredicate, 13,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_D), 0,
+ MVT::f64, 1, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FFINT_D_L), 0,
+ MVT::f64, 1, 1,
+ 16,
+ OPC_CheckPatternPredicate, 16,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FFINT_D_W), 0,
+ MVT::f64, 1, 1,
+ 0,
+ 0,
+ 0,
+ 24, TARGET_VAL(ISD::UINT_TO_FP),
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 10,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FFINT_S_W), 0,
+ MVT::f32, 1, 2,
+ 65, TARGET_VAL(ISD::FNEG),
+ OPC_Scope, 36,
+ OPC_MoveChild0,
+ OPC_CheckOpcode, TARGET_VAL(ISD::FMA),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNMADD_S), 0,
+ MVT::f32, 3, 0, 1, 2,
+ 11, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNMADD_D), 0,
+ MVT::f64, 3, 0, 1, 2,
+ 0,
+ 25,
+ OPC_RecordChild0,
+ OPC_SwitchType , 9, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNEG_S), 0,
+ MVT::f32, 1, 0,
+ 9, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNEG_D), 0,
+ MVT::f64, 1, 0,
+ 0,
+ 0,
+ 121|128,3, TARGET_VAL(ISD::ConstantFP),
+ OPC_Scope, 64,
+ OPC_CheckPredicate, 36,
+ OPC_SwitchType , 28, MVT::f32,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 0,
+ 12,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 0,
+ 0,
+ 28, MVT::f64,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 12,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVGR2FR_D), 0,
+ MVT::f64, 1, 0,
+ 12,
+ OPC_CheckPatternPredicate, 13,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVGR2FR_D), 0,
+ MVT::f64, 1, 0,
+ 0,
+ 0,
+ 92,
+ OPC_CheckPredicate, 37,
+ OPC_SwitchType , 42, MVT::f32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNEG_S), 0,
+ MVT::f32, 1, 1,
+ 19,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNEG_S), 0,
+ MVT::f32, 1, 1,
+ 0,
+ 42, MVT::f64,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 12,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_D), 0,
+ MVT::f64, 1, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNEG_D), 0,
+ MVT::f64, 1, 1,
+ 19,
+ OPC_CheckPatternPredicate, 13,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_D), 0,
+ MVT::f64, 1, 0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNEG_D), 0,
+ MVT::f64, 1, 1,
+ 0,
+ 0,
+ 54,
+ OPC_CheckPredicate, 36,
+ OPC_CheckType, MVT::f64,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 17,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W_64), 0,
+ MVT::f64, 1, 0,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVGR2FRH_W), 0,
+ MVT::f64, 2, 1, 2,
+ 23,
+ OPC_CheckPatternPredicate, 16,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W_64), 0,
+ MVT::f64, 1, 0,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVGR2FRH_W), 0,
+ MVT::f64, 2, 1, 2,
+ 0,
+ 8|128,1,
+ OPC_CheckPredicate, 34,
+ OPC_SwitchType , 64, MVT::f32,
+ OPC_Scope, 30,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_EmitInteger, MVT::i64, 2,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FFINT_S_W), 0,
+ MVT::f32, 1, 3,
+ 30,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FFINT_S_W), 0,
+ MVT::f32, 1, 3,
+ 0,
+ 64, MVT::f64,
+ OPC_Scope, 30,
+ OPC_CheckPatternPredicate, 12,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_EmitInteger, MVT::i64, 2,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_D), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_D), 0,
+ MVT::f64, 1, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FFINT_D_L), 0,
+ MVT::f64, 1, 3,
+ 30,
+ OPC_CheckPatternPredicate, 13,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_D), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_D), 0,
+ MVT::f64, 1, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FFINT_D_L), 0,
+ MVT::f64, 1, 3,
+ 0,
+ 0,
+ 68,
+ OPC_CheckPredicate, 37,
+ OPC_CheckType, MVT::f64,
+ OPC_Scope, 30,
+ OPC_CheckPatternPredicate, 17,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W_64), 0,
+ MVT::f64, 1, 0,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FRH_W), 0,
+ MVT::f64, 2, 1, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNEG_D), 0,
+ MVT::f64, 1, 3,
+ 30,
+ OPC_CheckPatternPredicate, 16,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W_64), 0,
+ MVT::f64, 1, 0,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FRH_W), 0,
+ MVT::f64, 2, 1, 2,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FNEG_D), 0,
+ MVT::f64, 1, 3,
+ 0,
+ 82,
+ OPC_CheckPredicate, 34,
+ OPC_CheckType, MVT::f64,
+ OPC_Scope, 37,
+ OPC_CheckPatternPredicate, 17,
+ OPC_EmitRegister, MVT::i64, LoongArch::R0,
+ OPC_EmitInteger, MVT::i64, 2,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i64, 2, 0, 1,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 2,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FFINT_S_W), 0,
+ MVT::f32, 1, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCVT_D_S), 0,
+ MVT::f64, 1, 4,
+ 37,
+ OPC_CheckPatternPredicate, 16,
+ OPC_EmitRegister, MVT::i32, LoongArch::R0,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::ADDI_W), 0,
+ MVT::i32, 2, 0, 1,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 2,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FFINT_S_W), 0,
+ MVT::f32, 1, 3,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCVT_D_S), 0,
+ MVT::f64, 1, 4,
+ 0,
+ 0,
+ 28, TARGET_VAL(ISD::FADD),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FADD_S), 0,
+ MVT::f32, 2, 0, 1,
+ 10, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FADD_D), 0,
+ MVT::f64, 2, 0, 1,
+ 0,
+ 28, TARGET_VAL(ISD::FSUB),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSUB_S), 0,
+ MVT::f32, 2, 0, 1,
+ 10, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSUB_D), 0,
+ MVT::f64, 2, 0, 1,
+ 0,
+ 28, TARGET_VAL(ISD::FMUL),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FMUL_S), 0,
+ MVT::f32, 2, 0, 1,
+ 10, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FMUL_D), 0,
+ MVT::f64, 2, 0, 1,
+ 0,
+ 76, TARGET_VAL(ISD::FCOPYSIGN),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 35,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCOPYSIGN_S), 0,
+ MVT::f32, 2, 0, 1,
+ 17, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCVT_D_S), 0,
+ MVT::f64, 1, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCOPYSIGN_D), 0,
+ MVT::f64, 2, 0, 2,
+ 0,
+ 35,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_SwitchType , 10, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCOPYSIGN_D), 0,
+ MVT::f64, 2, 0, 1,
+ 17, MVT::f32,
+ OPC_CheckPatternPredicate, 15,
+ OPC_EmitNode1, TARGET_VAL(LoongArch::FCVT_S_D), 0,
+ MVT::f32, 1, 1,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCOPYSIGN_S), 0,
+ MVT::f32, 2, 0, 2,
+ 0,
+ 0,
+ 28, TARGET_VAL(ISD::FMAXNUM_IEEE),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FMAX_S), 0,
+ MVT::f32, 2, 0, 1,
+ 10, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FMAX_D), 0,
+ MVT::f64, 2, 0, 1,
+ 0,
+ 28, TARGET_VAL(ISD::FMINNUM_IEEE),
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FMIN_S), 0,
+ MVT::f32, 2, 0, 1,
+ 10, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FMIN_D), 0,
+ MVT::f64, 2, 0, 1,
+ 0,
+ 25, TARGET_VAL(ISD::FABS),
+ OPC_RecordChild0,
+ OPC_SwitchType , 9, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FABS_S), 0,
+ MVT::f32, 1, 0,
+ 9, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FABS_D), 0,
+ MVT::f64, 1, 0,
+ 0,
+ 25, TARGET_VAL(ISD::FSQRT),
+ OPC_RecordChild0,
+ OPC_SwitchType , 9, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSQRT_S), 0,
+ MVT::f32, 1, 0,
+ 9, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FSQRT_D), 0,
+ MVT::f64, 1, 0,
+ 0,
+ 27, TARGET_VAL(ISD::FCANONICALIZE),
+ OPC_RecordChild0,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FMAX_S), 0,
+ MVT::f32, 2, 0, 0,
+ 10, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FMAX_D), 0,
+ MVT::f64, 2, 0, 0,
+ 0,
+ 57, TARGET_VAL(LoongArchISD::FTINT),
+ OPC_RecordChild0,
+ OPC_Scope, 26,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_SwitchType , 9, MVT::f32,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FTINTRZ_W_S), 0,
+ MVT::f32, 1, 0,
+ 9, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FTINTRZ_L_S), 0,
+ MVT::f64, 1, 0,
+ 0,
+ 26,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_SwitchType , 9, MVT::f32,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FTINTRZ_W_D), 0,
+ MVT::f32, 1, 0,
+ 9, MVT::f64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FTINTRZ_L_D), 0,
+ MVT::f64, 1, 0,
+ 0,
+ 0,
+ 25, TARGET_VAL(ISD::FRINT),
+ OPC_RecordChild0,
+ OPC_SwitchType , 9, MVT::f32,
+ OPC_CheckPatternPredicate, 18,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FRINT_S), 0,
+ MVT::f32, 1, 0,
+ 9, MVT::f64,
+ OPC_CheckPatternPredicate, 19,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FRINT_D), 0,
+ MVT::f64, 1, 0,
+ 0,
+ 10, TARGET_VAL(ISD::FP_ROUND),
+ OPC_RecordChild0,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCVT_S_D), 0,
+ MVT::f32, 1, 0,
+ 10, TARGET_VAL(ISD::FP_EXTEND),
+ OPC_RecordChild0,
+ OPC_CheckPatternPredicate, 15,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::FCVT_D_S), 0,
+ MVT::f64, 1, 0,
+ 10, TARGET_VAL(LoongArchISD::MOVGR2FR_W_LA64),
+ OPC_RecordChild0,
+ OPC_CheckPatternPredicate, 10,
+ OPC_MorphNodeTo1, TARGET_VAL(LoongArch::MOVGR2FR_W), 0,
+ MVT::f32, 1, 0,
+ 0,
+ 0
+ }; // Total Array size is 22169 bytes
+
+ #undef TARGET_VAL
+ SelectCodeCommon(N, MatcherTable,sizeof(MatcherTable));
+}
+#endif // GET_DAGISEL_BODY
+
+#ifdef GET_DAGISEL_DECL
+bool CheckPatternPredicate(unsigned PredNo) const override;
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+bool DAGISEL_CLASS_COLONCOLON CheckPatternPredicate(unsigned PredNo) const
+#if DAGISEL_INLINE
+ override
+#endif
+{
+ switch (PredNo) {
+ default: llvm_unreachable("Invalid predicate in table?");
+ case 0: return (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 1: return (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 2: return (!Subtarget->is64Bit()) && (!(MF->getSubtarget().checkFeatures("+64bit")));
+ case 3: return (Subtarget->is64Bit()) && (!(MF->getSubtarget().checkFeatures("+64bit")));
+ case 4: return (MF->getSubtarget().checkFeatures("+64bit"));
+ case 5: return (!(MF->getSubtarget().checkFeatures("+64bit")));
+ case 6: return (Subtarget->hasBasicF()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 7: return (Subtarget->hasBasicD()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 8: return (Subtarget->hasBasicF()) && (!(MF->getSubtarget().checkFeatures("+64bit")));
+ case 9: return (Subtarget->hasBasicD()) && (!(MF->getSubtarget().checkFeatures("+64bit")));
+ case 10: return (Subtarget->hasBasicF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 11: return (Subtarget->hasBasicF()) && (!Subtarget->is64Bit()) && (!(MF->getSubtarget().checkFeatures("+64bit")));
+ case 12: return (Subtarget->hasBasicD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 13: return (Subtarget->hasBasicD()) && (Subtarget->is64Bit()) && (!(MF->getSubtarget().checkFeatures("+64bit")));
+ case 14: return (Subtarget->hasBasicF());
+ case 15: return (Subtarget->hasBasicD());
+ case 16: return (Subtarget->hasBasicD()) && (!Subtarget->is64Bit()) && (!(MF->getSubtarget().checkFeatures("+64bit")));
+ case 17: return (Subtarget->hasBasicD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 18: return (Subtarget->hasBasicF()) && (Subtarget->is64Bit());
+ case 19: return (Subtarget->hasBasicD()) && (Subtarget->is64Bit());
+ }
+}
+#endif // GET_DAGISEL_BODY
+
+#ifdef GET_DAGISEL_DECL
+bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const override;
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+bool DAGISEL_CLASS_COLONCOLON CheckNodePredicate(SDNode *Node, unsigned PredNo) const
+#if DAGISEL_INLINE
+ override
+#endif
+{
+ switch (PredNo) {
+ default: llvm_unreachable("Invalid predicate in table?");
+ case 0: {
+ // Predicate_uimm2_plus1
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<2>(Imm - 1);
+ }
+ case 1: {
+ // Predicate_uimm5
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<5>(Imm);
+ }
+ case 2: {
+ // Predicate_uimm6
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<6>(Imm);
+ }
+ case 3: {
+ // Predicate_simm12
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isInt<12>(Imm);
+ }
+ case 4: {
+ // Predicate_AddLike
+ SDNode *N = Node;
+ (void)N;
+
+ return N->getOpcode() == ISD::ADD || isOrEquivalentToAdd(N);
+
+ }
+ case 5: {
+ // Predicate_unindexedload
+ SDNode *N = Node;
+ (void)N;
+if (cast<LoadSDNode>(N)->getAddressingMode() != ISD::UNINDEXED) return false;
+return true;
+
+ }
+ case 6: {
+ // Predicate_sextload
+ SDNode *N = Node;
+ (void)N;
+if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
+return true;
+
+ }
+ case 7: {
+ // Predicate_sextloadi8
+ // Predicate_extloadi8
+ // Predicate_zextloadi8
+ // Predicate_atomic_load_8
+ // Predicate_atomic_store_8
+ SDNode *N = Node;
+ (void)N;
+if (cast<MemSDNode>(N)->getMemoryVT() != MVT::i8) return false;
+return true;
+
+ }
+ case 8: {
+ // Predicate_extload
+ SDNode *N = Node;
+ (void)N;
+if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
+return true;
+
+ }
+ case 9: {
+ // Predicate_sextloadi16
+ // Predicate_extloadi16
+ // Predicate_zextloadi16
+ // Predicate_atomic_load_16
+ // Predicate_atomic_store_16
+ SDNode *N = Node;
+ (void)N;
+if (cast<MemSDNode>(N)->getMemoryVT() != MVT::i16) return false;
+return true;
+
+ }
+ case 10: {
+ // Predicate_load
+ SDNode *N = Node;
+ (void)N;
+if (cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD) return false;
+return true;
+
+ }
+ case 11: {
+ // Predicate_zextload
+ SDNode *N = Node;
+ (void)N;
+if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
+return true;
+
+ }
+ case 12: {
+ // Predicate_sextloadi32
+ // Predicate_extloadi32
+ // Predicate_zextloadi32
+ // Predicate_atomic_load_32
+ // Predicate_atomic_store_32
+ // Predicate_atomic_load_nand_32
+ // Predicate_atomic_swap_32
+ // Predicate_atomic_load_add_32
+ // Predicate_atomic_load_and_32
+ // Predicate_atomic_load_or_32
+ // Predicate_atomic_load_xor_32
+ // Predicate_atomic_load_umin_32
+ // Predicate_atomic_load_umax_32
+ // Predicate_atomic_load_min_32
+ // Predicate_atomic_load_max_32
+ // Predicate_atomic_cmp_swap_32
+ // Predicate_atomic_load_sub_32
+ SDNode *N = Node;
+ (void)N;
+if (cast<MemSDNode>(N)->getMemoryVT() != MVT::i32) return false;
+return true;
+
+ }
+ case 13: {
+ // Predicate_simm14_lsl2
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isShiftedInt<14,2>(Imm);
+ }
+ case 14: {
+ // Predicate_unindexedstore
+ SDNode *N = Node;
+ (void)N;
+if (cast<StoreSDNode>(N)->getAddressingMode() != ISD::UNINDEXED) return false;
+return true;
+
+ }
+ case 15: {
+ // Predicate_truncstore
+ SDNode *N = Node;
+ (void)N;
+ if (!cast<StoreSDNode>(N)->isTruncatingStore()) return false;
+return true;
+
+ }
+ case 16: {
+ // Predicate_truncstorei8
+ SDNode *N = Node;
+ (void)N;
+if (cast<MemSDNode>(N)->getMemoryVT() != MVT::i8) return false;
+ if (!cast<StoreSDNode>(N)->isTruncatingStore()) return false;
+return true;
+
+ }
+ case 17: {
+ // Predicate_truncstorei16
+ SDNode *N = Node;
+ (void)N;
+if (cast<MemSDNode>(N)->getMemoryVT() != MVT::i16) return false;
+ if (!cast<StoreSDNode>(N)->isTruncatingStore()) return false;
+return true;
+
+ }
+ case 18: {
+ // Predicate_truncstorei32
+ SDNode *N = Node;
+ (void)N;
+if (cast<MemSDNode>(N)->getMemoryVT() != MVT::i32) return false;
+ if (!cast<StoreSDNode>(N)->isTruncatingStore()) return false;
+return true;
+
+ }
+ case 19: {
+ // Predicate_store
+ SDNode *N = Node;
+ (void)N;
+ if (cast<StoreSDNode>(N)->isTruncatingStore()) return false;
+return true;
+
+ }
+ case 20: {
+ // Predicate_atomic_load_64
+ // Predicate_atomic_store_64
+ // Predicate_atomic_load_nand_64
+ // Predicate_atomic_swap_64
+ // Predicate_atomic_load_add_64
+ // Predicate_atomic_load_and_64
+ // Predicate_atomic_load_or_64
+ // Predicate_atomic_load_xor_64
+ // Predicate_atomic_load_umin_64
+ // Predicate_atomic_load_umax_64
+ // Predicate_atomic_load_min_64
+ // Predicate_atomic_load_max_64
+ // Predicate_atomic_cmp_swap_64
+ // Predicate_atomic_load_sub_64
+ SDNode *N = Node;
+ (void)N;
+if (cast<MemSDNode>(N)->getMemoryVT() != MVT::i64) return false;
+return true;
+
+ }
+ case 21: {
+ // Predicate_atomic_store_unordered_monotonic_32
+ // Predicate_atomic_store_unordered_monotonic_64
+ SDNode *N = Node;
+ (void)N;
+
+ AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getSuccessOrdering();
+ return !isReleaseOrStronger(Ordering);
+
+ }
+ case 22: {
+ // Predicate_atomic_store_release_seqcst_32
+ // Predicate_atomic_store_release_seqcst_64
+ SDNode *N = Node;
+ (void)N;
+
+ AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getSuccessOrdering();
+ return isReleaseOrStronger(Ordering);
+
+ }
+ case 23: {
+ // Predicate_uimm12
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<12>(Imm);
+ }
+ case 24: {
+ // Predicate_simm16_lsl2
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isInt<16>(Imm>>2);
+ }
+ case 25: {
+ // Predicate_simm12_plus1
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;
+ }
+ case 26: {
+ // Predicate_uimm15
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<15>(Imm);
+ }
+ case 27: {
+ // Predicate_uimm14
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<14>(Imm);
+ }
+ case 28: {
+ // Predicate_uimm2
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<2>(Imm);
+ }
+ case 29: {
+ // Predicate_atomic_load_nand_64_monotonic
+ // Predicate_atomic_load_nand_32_monotonic
+ // Predicate_atomic_swap_32_monotonic
+ // Predicate_atomic_load_add_32_monotonic
+ // Predicate_atomic_load_and_32_monotonic
+ // Predicate_atomic_load_or_32_monotonic
+ // Predicate_atomic_load_xor_32_monotonic
+ // Predicate_atomic_load_sub_32_monotonic
+ SDNode *N = Node;
+ (void)N;
+if (cast<AtomicSDNode>(N)->getMergedOrdering() != AtomicOrdering::Monotonic) return false;
+return true;
+
+ }
+ case 30: {
+ // Predicate_atomic_load_nand_64_acquire
+ // Predicate_atomic_load_nand_32_acquire
+ // Predicate_atomic_swap_32_acquire
+ // Predicate_atomic_load_add_32_acquire
+ // Predicate_atomic_load_and_32_acquire
+ // Predicate_atomic_load_or_32_acquire
+ // Predicate_atomic_load_xor_32_acquire
+ // Predicate_atomic_load_sub_32_acquire
+ SDNode *N = Node;
+ (void)N;
+if (cast<AtomicSDNode>(N)->getMergedOrdering() != AtomicOrdering::Acquire) return false;
+return true;
+
+ }
+ case 31: {
+ // Predicate_atomic_load_nand_64_release
+ // Predicate_atomic_load_nand_32_release
+ // Predicate_atomic_swap_32_release
+ // Predicate_atomic_load_add_32_release
+ // Predicate_atomic_load_and_32_release
+ // Predicate_atomic_load_or_32_release
+ // Predicate_atomic_load_xor_32_release
+ // Predicate_atomic_load_sub_32_release
+ SDNode *N = Node;
+ (void)N;
+if (cast<AtomicSDNode>(N)->getMergedOrdering() != AtomicOrdering::Release) return false;
+return true;
+
+ }
+ case 32: {
+ // Predicate_atomic_load_nand_64_acq_rel
+ // Predicate_atomic_load_nand_32_acq_rel
+ // Predicate_atomic_swap_32_acq_rel
+ // Predicate_atomic_load_add_32_acq_rel
+ // Predicate_atomic_load_and_32_acq_rel
+ // Predicate_atomic_load_or_32_acq_rel
+ // Predicate_atomic_load_xor_32_acq_rel
+ // Predicate_atomic_load_sub_32_acq_rel
+ SDNode *N = Node;
+ (void)N;
+if (cast<AtomicSDNode>(N)->getMergedOrdering() != AtomicOrdering::AcquireRelease) return false;
+return true;
+
+ }
+ case 33: {
+ // Predicate_atomic_load_nand_64_seq_cst
+ // Predicate_atomic_load_nand_32_seq_cst
+ // Predicate_atomic_swap_32_seq_cst
+ // Predicate_atomic_load_add_32_seq_cst
+ // Predicate_atomic_load_and_32_seq_cst
+ // Predicate_atomic_load_or_32_seq_cst
+ // Predicate_atomic_load_xor_32_seq_cst
+ // Predicate_atomic_load_sub_32_seq_cst
+ SDNode *N = Node;
+ (void)N;
+if (cast<AtomicSDNode>(N)->getMergedOrdering() != AtomicOrdering::SequentiallyConsistent) return false;
+return true;
+
+ }
+ case 34: {
+ // Predicate_fpimm1
+ auto *N = cast<ConstantFPSDNode>(Node);
+ (void)N;
+return N->isExactlyValue(+1.0);
+ }
+ case 35: {
+ // Predicate_fma_nsz
+ SDNode *N = Node;
+ (void)N;
+
+ return N->getFlags().hasNoSignedZeros();
+
+ }
+ case 36: {
+ // Predicate_fpimm0
+ auto *N = cast<ConstantFPSDNode>(Node);
+ (void)N;
+return N->isExactlyValue(+0.0);
+ }
+ case 37: {
+ // Predicate_fpimm0neg
+ auto *N = cast<ConstantFPSDNode>(Node);
+ (void)N;
+return N->isExactlyValue(-0.0);
+ }
+ }
+}
+#endif // GET_DAGISEL_BODY
+
+#ifdef GET_DAGISEL_DECL
+bool CheckComplexPattern(SDNode *Root, SDNode *Parent,
+ SDValue N, unsigned PatternNo,
+ SmallVectorImpl<std::pair<SDValue, SDNode *>> &Result) override;
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+bool DAGISEL_CLASS_COLONCOLON CheckComplexPattern(SDNode *Root, SDNode *Parent,
+ SDValue N, unsigned PatternNo,
+ SmallVectorImpl<std::pair<SDValue, SDNode *>> &Result)
+#if DAGISEL_INLINE
+ override
+#endif
+{
+ unsigned NextRes = Result.size();
+ switch (PatternNo) {
+ default: llvm_unreachable("Invalid pattern # in table?");
+ case 0:
+ Result.resize(NextRes+1);
+ return SelectBaseAddr(N, Result[NextRes+0].first);
+ case 1:
+ Result.resize(NextRes+1);
+ return selectNonFIBaseAddr(N, Result[NextRes+0].first);
+ case 2:
+ Result.resize(NextRes+1);
+ return selectShiftMaskGRLen(N, Result[NextRes+0].first);
+ case 3:
+ Result.resize(NextRes+1);
+ return selectShiftMask32(N, Result[NextRes+0].first);
+ case 4:
+ Result.resize(NextRes+1);
+ return selectSExti32(N, Result[NextRes+0].first);
+ }
+}
+#endif // GET_DAGISEL_BODY
+
+#ifdef GET_DAGISEL_DECL
+SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) override;
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+SDValue DAGISEL_CLASS_COLONCOLON RunSDNodeXForm(SDValue V, unsigned XFormNo)
+#if DAGISEL_INLINE
+ override
+#endif
+{
+ switch (XFormNo) {
+ default: llvm_unreachable("Invalid xform # in table?");
+ case 0: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
+
+ return CurDAG->getTargetConstant(32 - N->getZExtValue(), SDLoc(N),
+ N->getValueType(0));
+
+ }
+ case 1: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
+
+ return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N),
+ N->getValueType(0));
+
+ }
+ }
+}
+#endif // GET_DAGISEL_BODY
+
+
+#ifdef DAGISEL_INLINE
+#undef DAGISEL_INLINE
+#endif
+#ifdef DAGISEL_CLASS_COLONCOLON
+#undef DAGISEL_CLASS_COLONCOLON
+#endif
+#ifdef GET_DAGISEL_DECL
+#undef GET_DAGISEL_DECL
+#endif
+#ifdef GET_DAGISEL_BODY
+#undef GET_DAGISEL_BODY
+#endif
diff --git a/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenDisassemblerTables.inc b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenDisassemblerTables.inc
new file mode 100644
index 0000000..b1fe9f5
--- /dev/null
+++ b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenDisassemblerTables.inc
@@ -0,0 +1,1911 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* * LoongArch Disassembler *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/SubtargetFeature.h"
+#include "llvm/Support/DataTypes.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/LEB128.h"
+#include "llvm/Support/raw_ostream.h"
+#include <assert.h>
+
+namespace llvm {
+
+// Helper functions for extracting fields from encoded instructions.
+// InsnType must either be integral or an APInt-like object that must:
+// * be default-constructible and copy-constructible
+// * be constructible from an APInt (this can be private)
+// * Support insertBits(bits, startBit, numBits)
+// * Support extractBitsAsZExtValue(numBits, startBit)
+// * Support the ~, &, ==, and != operators with other objects of the same type
+// * Support the != and bitwise & with uint64_t
+// * Support put (<<) to raw_ostream&
+template <typename InsnType>
+#if defined(_MSC_VER) && !defined(__clang__)
+__declspec(noinline)
+#endif
+static std::enable_if_t<std::is_integral<InsnType>::value, InsnType>
+fieldFromInstruction(const InsnType &insn, unsigned startBit,
+ unsigned numBits) {
+ assert(startBit + numBits <= 64 && "Cannot support >64-bit extractions!");
+ assert(startBit + numBits <= (sizeof(InsnType) * 8) &&
+ "Instruction field out of bounds!");
+ InsnType fieldMask;
+ if (numBits == sizeof(InsnType) * 8)
+ fieldMask = (InsnType)(-1LL);
+ else
+ fieldMask = (((InsnType)1 << numBits) - 1) << startBit;
+ return (insn & fieldMask) >> startBit;
+}
+
+template <typename InsnType>
+static std::enable_if_t<!std::is_integral<InsnType>::value, uint64_t>
+fieldFromInstruction(const InsnType &insn, unsigned startBit,
+ unsigned numBits) {
+ return insn.extractBitsAsZExtValue(numBits, startBit);
+}
+
+// Helper function for inserting bits extracted from an encoded instruction into
+// a field.
+template <typename InsnType>
+static std::enable_if_t<std::is_integral<InsnType>::value>
+insertBits(InsnType &field, InsnType bits, unsigned startBit, unsigned numBits) {
+ assert(startBit + numBits <= sizeof field * 8);
+ field |= (InsnType)bits << startBit;
+}
+
+template <typename InsnType>
+static std::enable_if_t<!std::is_integral<InsnType>::value>
+insertBits(InsnType &field, uint64_t bits, unsigned startBit, unsigned numBits) {
+ field.insertBits(bits, startBit, numBits);
+}
+
+static bool Check(DecodeStatus &Out, DecodeStatus In) {
+ Out = static_cast<DecodeStatus>(Out & In);
+ return Out != MCDisassembler::Fail;
+}
+
+static const uint8_t DecoderTable32[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 0, 143, 9, 0, // Skip to: 2455
+/* 8 */ MCD::OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 11 */ MCD::OPC_FilterValue, 0, 7, 4, 0, // Skip to: 1047
+/* 16 */ MCD::OPC_ExtractField, 18, 4, // Inst{21-18} ...
+/* 19 */ MCD::OPC_FilterValue, 0, 73, 1, 0, // Skip to: 353
+/* 24 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 27 */ MCD::OPC_FilterValue, 0, 23, 1, 0, // Skip to: 311
+/* 32 */ MCD::OPC_ExtractField, 10, 5, // Inst{14-10} ...
+/* 35 */ MCD::OPC_FilterValue, 4, 4, 0, 0, // Skip to: 44
+/* 40 */ MCD::OPC_Decode, 250, 2, 0, // Opcode: CLO_W
+/* 44 */ MCD::OPC_FilterValue, 5, 4, 0, 0, // Skip to: 53
+/* 49 */ MCD::OPC_Decode, 252, 2, 0, // Opcode: CLZ_W
+/* 53 */ MCD::OPC_FilterValue, 6, 4, 0, 0, // Skip to: 62
+/* 58 */ MCD::OPC_Decode, 138, 3, 0, // Opcode: CTO_W
+/* 62 */ MCD::OPC_FilterValue, 7, 4, 0, 0, // Skip to: 71
+/* 67 */ MCD::OPC_Decode, 140, 3, 0, // Opcode: CTZ_W
+/* 71 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 85
+/* 76 */ MCD::OPC_CheckPredicate, 0, 138, 21, 0, // Skip to: 5595
+/* 81 */ MCD::OPC_Decode, 249, 2, 0, // Opcode: CLO_D
+/* 85 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 99
+/* 90 */ MCD::OPC_CheckPredicate, 0, 124, 21, 0, // Skip to: 5595
+/* 95 */ MCD::OPC_Decode, 251, 2, 0, // Opcode: CLZ_D
+/* 99 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 113
+/* 104 */ MCD::OPC_CheckPredicate, 0, 110, 21, 0, // Skip to: 5595
+/* 109 */ MCD::OPC_Decode, 137, 3, 0, // Opcode: CTO_D
+/* 113 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 127
+/* 118 */ MCD::OPC_CheckPredicate, 0, 96, 21, 0, // Skip to: 5595
+/* 123 */ MCD::OPC_Decode, 139, 3, 0, // Opcode: CTZ_D
+/* 127 */ MCD::OPC_FilterValue, 12, 4, 0, 0, // Skip to: 136
+/* 132 */ MCD::OPC_Decode, 240, 4, 0, // Opcode: REVB_2H
+/* 136 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 150
+/* 141 */ MCD::OPC_CheckPredicate, 0, 73, 21, 0, // Skip to: 5595
+/* 146 */ MCD::OPC_Decode, 242, 4, 0, // Opcode: REVB_4H
+/* 150 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 164
+/* 155 */ MCD::OPC_CheckPredicate, 0, 59, 21, 0, // Skip to: 5595
+/* 160 */ MCD::OPC_Decode, 241, 4, 0, // Opcode: REVB_2W
+/* 164 */ MCD::OPC_FilterValue, 15, 9, 0, 0, // Skip to: 178
+/* 169 */ MCD::OPC_CheckPredicate, 0, 45, 21, 0, // Skip to: 5595
+/* 174 */ MCD::OPC_Decode, 243, 4, 0, // Opcode: REVB_D
+/* 178 */ MCD::OPC_FilterValue, 16, 9, 0, 0, // Skip to: 192
+/* 183 */ MCD::OPC_CheckPredicate, 0, 31, 21, 0, // Skip to: 5595
+/* 188 */ MCD::OPC_Decode, 244, 4, 0, // Opcode: REVH_2W
+/* 192 */ MCD::OPC_FilterValue, 17, 9, 0, 0, // Skip to: 206
+/* 197 */ MCD::OPC_CheckPredicate, 0, 17, 21, 0, // Skip to: 5595
+/* 202 */ MCD::OPC_Decode, 245, 4, 0, // Opcode: REVH_D
+/* 206 */ MCD::OPC_FilterValue, 18, 4, 0, 0, // Skip to: 215
+/* 211 */ MCD::OPC_Decode, 232, 2, 0, // Opcode: BITREV_4B
+/* 215 */ MCD::OPC_FilterValue, 19, 9, 0, 0, // Skip to: 229
+/* 220 */ MCD::OPC_CheckPredicate, 0, 250, 20, 0, // Skip to: 5595
+/* 225 */ MCD::OPC_Decode, 233, 2, 0, // Opcode: BITREV_8B
+/* 229 */ MCD::OPC_FilterValue, 20, 4, 0, 0, // Skip to: 238
+/* 234 */ MCD::OPC_Decode, 235, 2, 0, // Opcode: BITREV_W
+/* 238 */ MCD::OPC_FilterValue, 21, 9, 0, 0, // Skip to: 252
+/* 243 */ MCD::OPC_CheckPredicate, 0, 227, 20, 0, // Skip to: 5595
+/* 248 */ MCD::OPC_Decode, 234, 2, 0, // Opcode: BITREV_D
+/* 252 */ MCD::OPC_FilterValue, 22, 4, 0, 0, // Skip to: 261
+/* 257 */ MCD::OPC_Decode, 149, 3, 0, // Opcode: EXT_W_H
+/* 261 */ MCD::OPC_FilterValue, 23, 4, 0, 0, // Skip to: 270
+/* 266 */ MCD::OPC_Decode, 148, 3, 0, // Opcode: EXT_W_B
+/* 270 */ MCD::OPC_FilterValue, 24, 4, 0, 0, // Skip to: 279
+/* 275 */ MCD::OPC_Decode, 238, 4, 0, // Opcode: RDTIMEL_W
+/* 279 */ MCD::OPC_FilterValue, 25, 4, 0, 0, // Skip to: 288
+/* 284 */ MCD::OPC_Decode, 237, 4, 0, // Opcode: RDTIMEH_W
+/* 288 */ MCD::OPC_FilterValue, 26, 9, 0, 0, // Skip to: 302
+/* 293 */ MCD::OPC_CheckPredicate, 0, 177, 20, 0, // Skip to: 5595
+/* 298 */ MCD::OPC_Decode, 239, 4, 0, // Opcode: RDTIME_D
+/* 302 */ MCD::OPC_FilterValue, 27, 168, 20, 0, // Skip to: 5595
+/* 307 */ MCD::OPC_Decode, 253, 2, 0, // Opcode: CPUCFG
+/* 311 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 332
+/* 316 */ MCD::OPC_CheckPredicate, 0, 154, 20, 0, // Skip to: 5595
+/* 321 */ MCD::OPC_CheckField, 0, 5, 0, 147, 20, 0, // Skip to: 5595
+/* 328 */ MCD::OPC_Decode, 224, 2, 1, // Opcode: ASRTLE_D
+/* 332 */ MCD::OPC_FilterValue, 3, 138, 20, 0, // Skip to: 5595
+/* 337 */ MCD::OPC_CheckPredicate, 0, 133, 20, 0, // Skip to: 5595
+/* 342 */ MCD::OPC_CheckField, 0, 5, 0, 126, 20, 0, // Skip to: 5595
+/* 349 */ MCD::OPC_Decode, 223, 2, 1, // Opcode: ASRTGT_D
+/* 353 */ MCD::OPC_FilterValue, 1, 26, 0, 0, // Skip to: 384
+/* 358 */ MCD::OPC_ExtractField, 17, 1, // Inst{17} ...
+/* 361 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 370
+/* 366 */ MCD::OPC_Decode, 182, 2, 2, // Opcode: ALSL_W
+/* 370 */ MCD::OPC_FilterValue, 1, 100, 20, 0, // Skip to: 5595
+/* 375 */ MCD::OPC_CheckPredicate, 0, 95, 20, 0, // Skip to: 5595
+/* 380 */ MCD::OPC_Decode, 183, 2, 2, // Opcode: ALSL_WU
+/* 384 */ MCD::OPC_FilterValue, 2, 11, 0, 0, // Skip to: 400
+/* 389 */ MCD::OPC_CheckField, 17, 1, 0, 79, 20, 0, // Skip to: 5595
+/* 396 */ MCD::OPC_Decode, 247, 2, 3, // Opcode: BYTEPICK_W
+/* 400 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 414
+/* 405 */ MCD::OPC_CheckPredicate, 0, 65, 20, 0, // Skip to: 5595
+/* 410 */ MCD::OPC_Decode, 246, 2, 4, // Opcode: BYTEPICK_D
+/* 414 */ MCD::OPC_FilterValue, 4, 85, 0, 0, // Skip to: 504
+/* 419 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 422 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 431
+/* 427 */ MCD::OPC_Decode, 180, 2, 5, // Opcode: ADD_W
+/* 431 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 445
+/* 436 */ MCD::OPC_CheckPredicate, 0, 34, 20, 0, // Skip to: 5595
+/* 441 */ MCD::OPC_Decode, 179, 2, 5, // Opcode: ADD_D
+/* 445 */ MCD::OPC_FilterValue, 2, 4, 0, 0, // Skip to: 454
+/* 450 */ MCD::OPC_Decode, 159, 5, 5, // Opcode: SUB_W
+/* 454 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 468
+/* 459 */ MCD::OPC_CheckPredicate, 0, 11, 20, 0, // Skip to: 5595
+/* 464 */ MCD::OPC_Decode, 158, 5, 5, // Opcode: SUB_D
+/* 468 */ MCD::OPC_FilterValue, 4, 4, 0, 0, // Skip to: 477
+/* 473 */ MCD::OPC_Decode, 128, 5, 5, // Opcode: SLT
+/* 477 */ MCD::OPC_FilterValue, 5, 4, 0, 0, // Skip to: 486
+/* 482 */ MCD::OPC_Decode, 130, 5, 5, // Opcode: SLTU
+/* 486 */ MCD::OPC_FilterValue, 6, 4, 0, 0, // Skip to: 495
+/* 491 */ MCD::OPC_Decode, 199, 4, 5, // Opcode: MASKEQZ
+/* 495 */ MCD::OPC_FilterValue, 7, 231, 19, 0, // Skip to: 5595
+/* 500 */ MCD::OPC_Decode, 200, 4, 5, // Opcode: MASKNEZ
+/* 504 */ MCD::OPC_FilterValue, 5, 75, 0, 0, // Skip to: 584
+/* 509 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 512 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 521
+/* 517 */ MCD::OPC_Decode, 227, 4, 5, // Opcode: NOR
+/* 521 */ MCD::OPC_FilterValue, 1, 4, 0, 0, // Skip to: 530
+/* 526 */ MCD::OPC_Decode, 220, 2, 5, // Opcode: AND
+/* 530 */ MCD::OPC_FilterValue, 2, 4, 0, 0, // Skip to: 539
+/* 535 */ MCD::OPC_Decode, 228, 4, 5, // Opcode: OR
+/* 539 */ MCD::OPC_FilterValue, 3, 4, 0, 0, // Skip to: 548
+/* 544 */ MCD::OPC_Decode, 167, 5, 5, // Opcode: XOR
+/* 548 */ MCD::OPC_FilterValue, 4, 4, 0, 0, // Skip to: 557
+/* 553 */ MCD::OPC_Decode, 230, 4, 5, // Opcode: ORN
+/* 557 */ MCD::OPC_FilterValue, 5, 4, 0, 0, // Skip to: 566
+/* 562 */ MCD::OPC_Decode, 222, 2, 5, // Opcode: ANDN
+/* 566 */ MCD::OPC_FilterValue, 6, 4, 0, 0, // Skip to: 575
+/* 571 */ MCD::OPC_Decode, 255, 4, 5, // Opcode: SLL_W
+/* 575 */ MCD::OPC_FilterValue, 7, 151, 19, 0, // Skip to: 5595
+/* 580 */ MCD::OPC_Decode, 139, 5, 5, // Opcode: SRL_W
+/* 584 */ MCD::OPC_FilterValue, 6, 77, 0, 0, // Skip to: 666
+/* 589 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 592 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 601
+/* 597 */ MCD::OPC_Decode, 135, 5, 5, // Opcode: SRA_W
+/* 601 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 615
+/* 606 */ MCD::OPC_CheckPredicate, 0, 120, 19, 0, // Skip to: 5595
+/* 611 */ MCD::OPC_Decode, 254, 4, 5, // Opcode: SLL_D
+/* 615 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 629
+/* 620 */ MCD::OPC_CheckPredicate, 0, 106, 19, 0, // Skip to: 5595
+/* 625 */ MCD::OPC_Decode, 138, 5, 5, // Opcode: SRL_D
+/* 629 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 643
+/* 634 */ MCD::OPC_CheckPredicate, 0, 92, 19, 0, // Skip to: 5595
+/* 639 */ MCD::OPC_Decode, 134, 5, 5, // Opcode: SRA_D
+/* 643 */ MCD::OPC_FilterValue, 6, 4, 0, 0, // Skip to: 652
+/* 648 */ MCD::OPC_Decode, 249, 4, 5, // Opcode: ROTR_W
+/* 652 */ MCD::OPC_FilterValue, 7, 74, 19, 0, // Skip to: 5595
+/* 657 */ MCD::OPC_CheckPredicate, 0, 69, 19, 0, // Skip to: 5595
+/* 662 */ MCD::OPC_Decode, 248, 4, 5, // Opcode: ROTR_D
+/* 666 */ MCD::OPC_FilterValue, 7, 100, 0, 0, // Skip to: 771
+/* 671 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 674 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 683
+/* 679 */ MCD::OPC_Decode, 226, 4, 5, // Opcode: MUL_W
+/* 683 */ MCD::OPC_FilterValue, 1, 4, 0, 0, // Skip to: 692
+/* 688 */ MCD::OPC_Decode, 221, 4, 5, // Opcode: MULH_W
+/* 692 */ MCD::OPC_FilterValue, 2, 4, 0, 0, // Skip to: 701
+/* 697 */ MCD::OPC_Decode, 222, 4, 5, // Opcode: MULH_WU
+/* 701 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 715
+/* 706 */ MCD::OPC_CheckPredicate, 0, 20, 19, 0, // Skip to: 5595
+/* 711 */ MCD::OPC_Decode, 225, 4, 5, // Opcode: MUL_D
+/* 715 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 729
+/* 720 */ MCD::OPC_CheckPredicate, 0, 6, 19, 0, // Skip to: 5595
+/* 725 */ MCD::OPC_Decode, 219, 4, 5, // Opcode: MULH_D
+/* 729 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 743
+/* 734 */ MCD::OPC_CheckPredicate, 0, 248, 18, 0, // Skip to: 5595
+/* 739 */ MCD::OPC_Decode, 220, 4, 5, // Opcode: MULH_DU
+/* 743 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 757
+/* 748 */ MCD::OPC_CheckPredicate, 0, 234, 18, 0, // Skip to: 5595
+/* 753 */ MCD::OPC_Decode, 223, 4, 5, // Opcode: MULW_D_W
+/* 757 */ MCD::OPC_FilterValue, 7, 225, 18, 0, // Skip to: 5595
+/* 762 */ MCD::OPC_CheckPredicate, 0, 220, 18, 0, // Skip to: 5595
+/* 767 */ MCD::OPC_Decode, 224, 4, 5, // Opcode: MULW_D_WU
+/* 771 */ MCD::OPC_FilterValue, 8, 95, 0, 0, // Skip to: 871
+/* 776 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 779 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 788
+/* 784 */ MCD::OPC_Decode, 145, 3, 5, // Opcode: DIV_W
+/* 788 */ MCD::OPC_FilterValue, 1, 4, 0, 0, // Skip to: 797
+/* 793 */ MCD::OPC_Decode, 203, 4, 5, // Opcode: MOD_W
+/* 797 */ MCD::OPC_FilterValue, 2, 4, 0, 0, // Skip to: 806
+/* 802 */ MCD::OPC_Decode, 146, 3, 5, // Opcode: DIV_WU
+/* 806 */ MCD::OPC_FilterValue, 3, 4, 0, 0, // Skip to: 815
+/* 811 */ MCD::OPC_Decode, 204, 4, 5, // Opcode: MOD_WU
+/* 815 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 829
+/* 820 */ MCD::OPC_CheckPredicate, 0, 162, 18, 0, // Skip to: 5595
+/* 825 */ MCD::OPC_Decode, 143, 3, 5, // Opcode: DIV_D
+/* 829 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 843
+/* 834 */ MCD::OPC_CheckPredicate, 0, 148, 18, 0, // Skip to: 5595
+/* 839 */ MCD::OPC_Decode, 201, 4, 5, // Opcode: MOD_D
+/* 843 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 857
+/* 848 */ MCD::OPC_CheckPredicate, 0, 134, 18, 0, // Skip to: 5595
+/* 853 */ MCD::OPC_Decode, 144, 3, 5, // Opcode: DIV_DU
+/* 857 */ MCD::OPC_FilterValue, 7, 125, 18, 0, // Skip to: 5595
+/* 862 */ MCD::OPC_CheckPredicate, 0, 120, 18, 0, // Skip to: 5595
+/* 867 */ MCD::OPC_Decode, 202, 4, 5, // Opcode: MOD_DU
+/* 871 */ MCD::OPC_FilterValue, 9, 115, 0, 0, // Skip to: 991
+/* 876 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 879 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 893
+/* 884 */ MCD::OPC_CheckPredicate, 0, 98, 18, 0, // Skip to: 5595
+/* 889 */ MCD::OPC_Decode, 130, 3, 5, // Opcode: CRC_W_B_W
+/* 893 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 907
+/* 898 */ MCD::OPC_CheckPredicate, 0, 84, 18, 0, // Skip to: 5595
+/* 903 */ MCD::OPC_Decode, 132, 3, 5, // Opcode: CRC_W_H_W
+/* 907 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 921
+/* 912 */ MCD::OPC_CheckPredicate, 0, 70, 18, 0, // Skip to: 5595
+/* 917 */ MCD::OPC_Decode, 133, 3, 5, // Opcode: CRC_W_W_W
+/* 921 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 935
+/* 926 */ MCD::OPC_CheckPredicate, 0, 56, 18, 0, // Skip to: 5595
+/* 931 */ MCD::OPC_Decode, 131, 3, 5, // Opcode: CRC_W_D_W
+/* 935 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 949
+/* 940 */ MCD::OPC_CheckPredicate, 0, 42, 18, 0, // Skip to: 5595
+/* 945 */ MCD::OPC_Decode, 254, 2, 5, // Opcode: CRCC_W_B_W
+/* 949 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 963
+/* 954 */ MCD::OPC_CheckPredicate, 0, 28, 18, 0, // Skip to: 5595
+/* 959 */ MCD::OPC_Decode, 128, 3, 5, // Opcode: CRCC_W_H_W
+/* 963 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 977
+/* 968 */ MCD::OPC_CheckPredicate, 0, 14, 18, 0, // Skip to: 5595
+/* 973 */ MCD::OPC_Decode, 129, 3, 5, // Opcode: CRCC_W_W_W
+/* 977 */ MCD::OPC_FilterValue, 7, 5, 18, 0, // Skip to: 5595
+/* 982 */ MCD::OPC_CheckPredicate, 0, 0, 18, 0, // Skip to: 5595
+/* 987 */ MCD::OPC_Decode, 255, 2, 5, // Opcode: CRCC_W_D_W
+/* 991 */ MCD::OPC_FilterValue, 10, 30, 0, 0, // Skip to: 1026
+/* 996 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 999 */ MCD::OPC_FilterValue, 4, 4, 0, 0, // Skip to: 1008
+/* 1004 */ MCD::OPC_Decode, 241, 2, 6, // Opcode: BREAK
+/* 1008 */ MCD::OPC_FilterValue, 5, 4, 0, 0, // Skip to: 1017
+/* 1013 */ MCD::OPC_Decode, 142, 3, 6, // Opcode: DBCL
+/* 1017 */ MCD::OPC_FilterValue, 6, 221, 17, 0, // Skip to: 5595
+/* 1022 */ MCD::OPC_Decode, 160, 5, 6, // Opcode: SYSCALL
+/* 1026 */ MCD::OPC_FilterValue, 11, 212, 17, 0, // Skip to: 5595
+/* 1031 */ MCD::OPC_CheckPredicate, 0, 207, 17, 0, // Skip to: 5595
+/* 1036 */ MCD::OPC_CheckField, 17, 1, 0, 200, 17, 0, // Skip to: 5595
+/* 1043 */ MCD::OPC_Decode, 181, 2, 2, // Opcode: ALSL_D
+/* 1047 */ MCD::OPC_FilterValue, 1, 157, 0, 0, // Skip to: 1209
+/* 1052 */ MCD::OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1055 */ MCD::OPC_FilterValue, 0, 123, 0, 0, // Skip to: 1183
+/* 1060 */ MCD::OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 1063 */ MCD::OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1079
+/* 1068 */ MCD::OPC_CheckField, 15, 1, 1, 168, 17, 0, // Skip to: 5595
+/* 1075 */ MCD::OPC_Decode, 253, 4, 7, // Opcode: SLLI_W
+/* 1079 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1093
+/* 1084 */ MCD::OPC_CheckPredicate, 0, 154, 17, 0, // Skip to: 5595
+/* 1089 */ MCD::OPC_Decode, 252, 4, 8, // Opcode: SLLI_D
+/* 1093 */ MCD::OPC_FilterValue, 4, 11, 0, 0, // Skip to: 1109
+/* 1098 */ MCD::OPC_CheckField, 15, 1, 1, 138, 17, 0, // Skip to: 5595
+/* 1105 */ MCD::OPC_Decode, 137, 5, 7, // Opcode: SRLI_W
+/* 1109 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1123
+/* 1114 */ MCD::OPC_CheckPredicate, 0, 124, 17, 0, // Skip to: 5595
+/* 1119 */ MCD::OPC_Decode, 136, 5, 8, // Opcode: SRLI_D
+/* 1123 */ MCD::OPC_FilterValue, 8, 11, 0, 0, // Skip to: 1139
+/* 1128 */ MCD::OPC_CheckField, 15, 1, 1, 108, 17, 0, // Skip to: 5595
+/* 1135 */ MCD::OPC_Decode, 133, 5, 7, // Opcode: SRAI_W
+/* 1139 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 1153
+/* 1144 */ MCD::OPC_CheckPredicate, 0, 94, 17, 0, // Skip to: 5595
+/* 1149 */ MCD::OPC_Decode, 132, 5, 8, // Opcode: SRAI_D
+/* 1153 */ MCD::OPC_FilterValue, 12, 11, 0, 0, // Skip to: 1169
+/* 1158 */ MCD::OPC_CheckField, 15, 1, 1, 78, 17, 0, // Skip to: 5595
+/* 1165 */ MCD::OPC_Decode, 247, 4, 7, // Opcode: ROTRI_W
+/* 1169 */ MCD::OPC_FilterValue, 13, 69, 17, 0, // Skip to: 5595
+/* 1174 */ MCD::OPC_CheckPredicate, 0, 64, 17, 0, // Skip to: 5595
+/* 1179 */ MCD::OPC_Decode, 246, 4, 8, // Opcode: ROTRI_D
+/* 1183 */ MCD::OPC_FilterValue, 1, 55, 17, 0, // Skip to: 5595
+/* 1188 */ MCD::OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 1191 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1200
+/* 1196 */ MCD::OPC_Decode, 243, 2, 9, // Opcode: BSTRINS_W
+/* 1200 */ MCD::OPC_FilterValue, 1, 38, 17, 0, // Skip to: 5595
+/* 1205 */ MCD::OPC_Decode, 245, 2, 10, // Opcode: BSTRPICK_W
+/* 1209 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1223
+/* 1214 */ MCD::OPC_CheckPredicate, 0, 24, 17, 0, // Skip to: 5595
+/* 1219 */ MCD::OPC_Decode, 242, 2, 11, // Opcode: BSTRINS_D
+/* 1223 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 1237
+/* 1228 */ MCD::OPC_CheckPredicate, 0, 10, 17, 0, // Skip to: 5595
+/* 1233 */ MCD::OPC_Decode, 244, 2, 12, // Opcode: BSTRPICK_D
+/* 1237 */ MCD::OPC_FilterValue, 4, 107, 4, 0, // Skip to: 2373
+/* 1242 */ MCD::OPC_ExtractField, 15, 7, // Inst{21-15} ...
+/* 1245 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1259
+/* 1250 */ MCD::OPC_CheckPredicate, 1, 244, 16, 0, // Skip to: 5595
+/* 1255 */ MCD::OPC_Decode, 153, 3, 13, // Opcode: FADD_S
+/* 1259 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1273
+/* 1264 */ MCD::OPC_CheckPredicate, 2, 230, 16, 0, // Skip to: 5595
+/* 1269 */ MCD::OPC_Decode, 152, 3, 14, // Opcode: FADD_D
+/* 1273 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1287
+/* 1278 */ MCD::OPC_CheckPredicate, 1, 216, 16, 0, // Skip to: 5595
+/* 1283 */ MCD::OPC_Decode, 135, 4, 13, // Opcode: FSUB_S
+/* 1287 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1301
+/* 1292 */ MCD::OPC_CheckPredicate, 2, 202, 16, 0, // Skip to: 5595
+/* 1297 */ MCD::OPC_Decode, 134, 4, 14, // Opcode: FSUB_D
+/* 1301 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 1315
+/* 1306 */ MCD::OPC_CheckPredicate, 1, 188, 16, 0, // Skip to: 5595
+/* 1311 */ MCD::OPC_Decode, 235, 3, 13, // Opcode: FMUL_S
+/* 1315 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 1329
+/* 1320 */ MCD::OPC_CheckPredicate, 2, 174, 16, 0, // Skip to: 5595
+/* 1325 */ MCD::OPC_Decode, 234, 3, 14, // Opcode: FMUL_D
+/* 1329 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 1343
+/* 1334 */ MCD::OPC_CheckPredicate, 1, 160, 16, 0, // Skip to: 5595
+/* 1339 */ MCD::OPC_Decode, 205, 3, 13, // Opcode: FDIV_S
+/* 1343 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 1357
+/* 1348 */ MCD::OPC_CheckPredicate, 2, 146, 16, 0, // Skip to: 5595
+/* 1353 */ MCD::OPC_Decode, 204, 3, 14, // Opcode: FDIV_D
+/* 1357 */ MCD::OPC_FilterValue, 17, 9, 0, 0, // Skip to: 1371
+/* 1362 */ MCD::OPC_CheckPredicate, 1, 132, 16, 0, // Skip to: 5595
+/* 1367 */ MCD::OPC_Decode, 225, 3, 13, // Opcode: FMAX_S
+/* 1371 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 1385
+/* 1376 */ MCD::OPC_CheckPredicate, 2, 118, 16, 0, // Skip to: 5595
+/* 1381 */ MCD::OPC_Decode, 224, 3, 14, // Opcode: FMAX_D
+/* 1385 */ MCD::OPC_FilterValue, 21, 9, 0, 0, // Skip to: 1399
+/* 1390 */ MCD::OPC_CheckPredicate, 1, 104, 16, 0, // Skip to: 5595
+/* 1395 */ MCD::OPC_Decode, 229, 3, 13, // Opcode: FMIN_S
+/* 1399 */ MCD::OPC_FilterValue, 22, 9, 0, 0, // Skip to: 1413
+/* 1404 */ MCD::OPC_CheckPredicate, 2, 90, 16, 0, // Skip to: 5595
+/* 1409 */ MCD::OPC_Decode, 228, 3, 14, // Opcode: FMIN_D
+/* 1413 */ MCD::OPC_FilterValue, 25, 9, 0, 0, // Skip to: 1427
+/* 1418 */ MCD::OPC_CheckPredicate, 1, 76, 16, 0, // Skip to: 5595
+/* 1423 */ MCD::OPC_Decode, 223, 3, 13, // Opcode: FMAXA_S
+/* 1427 */ MCD::OPC_FilterValue, 26, 9, 0, 0, // Skip to: 1441
+/* 1432 */ MCD::OPC_CheckPredicate, 2, 62, 16, 0, // Skip to: 5595
+/* 1437 */ MCD::OPC_Decode, 222, 3, 14, // Opcode: FMAXA_D
+/* 1441 */ MCD::OPC_FilterValue, 29, 9, 0, 0, // Skip to: 1455
+/* 1446 */ MCD::OPC_CheckPredicate, 1, 48, 16, 0, // Skip to: 5595
+/* 1451 */ MCD::OPC_Decode, 227, 3, 13, // Opcode: FMINA_S
+/* 1455 */ MCD::OPC_FilterValue, 30, 9, 0, 0, // Skip to: 1469
+/* 1460 */ MCD::OPC_CheckPredicate, 2, 34, 16, 0, // Skip to: 5595
+/* 1465 */ MCD::OPC_Decode, 226, 3, 14, // Opcode: FMINA_D
+/* 1469 */ MCD::OPC_FilterValue, 33, 9, 0, 0, // Skip to: 1483
+/* 1474 */ MCD::OPC_CheckPredicate, 1, 20, 16, 0, // Skip to: 5595
+/* 1479 */ MCD::OPC_Decode, 249, 3, 13, // Opcode: FSCALEB_S
+/* 1483 */ MCD::OPC_FilterValue, 34, 9, 0, 0, // Skip to: 1497
+/* 1488 */ MCD::OPC_CheckPredicate, 2, 6, 16, 0, // Skip to: 5595
+/* 1493 */ MCD::OPC_Decode, 248, 3, 14, // Opcode: FSCALEB_D
+/* 1497 */ MCD::OPC_FilterValue, 37, 9, 0, 0, // Skip to: 1511
+/* 1502 */ MCD::OPC_CheckPredicate, 1, 248, 15, 0, // Skip to: 5595
+/* 1507 */ MCD::OPC_Decode, 201, 3, 13, // Opcode: FCOPYSIGN_S
+/* 1511 */ MCD::OPC_FilterValue, 38, 9, 0, 0, // Skip to: 1525
+/* 1516 */ MCD::OPC_CheckPredicate, 2, 234, 15, 0, // Skip to: 5595
+/* 1521 */ MCD::OPC_Decode, 200, 3, 14, // Opcode: FCOPYSIGN_D
+/* 1525 */ MCD::OPC_FilterValue, 40, 199, 0, 0, // Skip to: 1729
+/* 1530 */ MCD::OPC_ExtractField, 10, 5, // Inst{14-10} ...
+/* 1533 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1547
+/* 1538 */ MCD::OPC_CheckPredicate, 1, 212, 15, 0, // Skip to: 5595
+/* 1543 */ MCD::OPC_Decode, 151, 3, 15, // Opcode: FABS_S
+/* 1547 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1561
+/* 1552 */ MCD::OPC_CheckPredicate, 2, 198, 15, 0, // Skip to: 5595
+/* 1557 */ MCD::OPC_Decode, 150, 3, 16, // Opcode: FABS_D
+/* 1561 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1575
+/* 1566 */ MCD::OPC_CheckPredicate, 1, 184, 15, 0, // Skip to: 5595
+/* 1571 */ MCD::OPC_Decode, 237, 3, 15, // Opcode: FNEG_S
+/* 1575 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1589
+/* 1580 */ MCD::OPC_CheckPredicate, 2, 170, 15, 0, // Skip to: 5595
+/* 1585 */ MCD::OPC_Decode, 236, 3, 16, // Opcode: FNEG_D
+/* 1589 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 1603
+/* 1594 */ MCD::OPC_CheckPredicate, 1, 156, 15, 0, // Skip to: 5595
+/* 1599 */ MCD::OPC_Decode, 219, 3, 15, // Opcode: FLOGB_S
+/* 1603 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 1617
+/* 1608 */ MCD::OPC_CheckPredicate, 2, 142, 15, 0, // Skip to: 5595
+/* 1613 */ MCD::OPC_Decode, 218, 3, 16, // Opcode: FLOGB_D
+/* 1617 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 1631
+/* 1622 */ MCD::OPC_CheckPredicate, 1, 128, 15, 0, // Skip to: 5595
+/* 1627 */ MCD::OPC_Decode, 155, 3, 15, // Opcode: FCLASS_S
+/* 1631 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 1645
+/* 1636 */ MCD::OPC_CheckPredicate, 2, 114, 15, 0, // Skip to: 5595
+/* 1641 */ MCD::OPC_Decode, 154, 3, 16, // Opcode: FCLASS_D
+/* 1645 */ MCD::OPC_FilterValue, 17, 9, 0, 0, // Skip to: 1659
+/* 1650 */ MCD::OPC_CheckPredicate, 1, 100, 15, 0, // Skip to: 5595
+/* 1655 */ MCD::OPC_Decode, 253, 3, 15, // Opcode: FSQRT_S
+/* 1659 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 1673
+/* 1664 */ MCD::OPC_CheckPredicate, 2, 86, 15, 0, // Skip to: 5595
+/* 1669 */ MCD::OPC_Decode, 252, 3, 16, // Opcode: FSQRT_D
+/* 1673 */ MCD::OPC_FilterValue, 21, 9, 0, 0, // Skip to: 1687
+/* 1678 */ MCD::OPC_CheckPredicate, 1, 72, 15, 0, // Skip to: 5595
+/* 1683 */ MCD::OPC_Decode, 243, 3, 15, // Opcode: FRECIP_S
+/* 1687 */ MCD::OPC_FilterValue, 22, 9, 0, 0, // Skip to: 1701
+/* 1692 */ MCD::OPC_CheckPredicate, 2, 58, 15, 0, // Skip to: 5595
+/* 1697 */ MCD::OPC_Decode, 242, 3, 16, // Opcode: FRECIP_D
+/* 1701 */ MCD::OPC_FilterValue, 25, 9, 0, 0, // Skip to: 1715
+/* 1706 */ MCD::OPC_CheckPredicate, 1, 44, 15, 0, // Skip to: 5595
+/* 1711 */ MCD::OPC_Decode, 247, 3, 15, // Opcode: FRSQRT_S
+/* 1715 */ MCD::OPC_FilterValue, 26, 35, 15, 0, // Skip to: 5595
+/* 1720 */ MCD::OPC_CheckPredicate, 2, 30, 15, 0, // Skip to: 5595
+/* 1725 */ MCD::OPC_Decode, 246, 3, 16, // Opcode: FRSQRT_D
+/* 1729 */ MCD::OPC_FilterValue, 41, 199, 0, 0, // Skip to: 1933
+/* 1734 */ MCD::OPC_ExtractField, 10, 5, // Inst{14-10} ...
+/* 1737 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1751
+/* 1742 */ MCD::OPC_CheckPredicate, 1, 8, 15, 0, // Skip to: 5595
+/* 1747 */ MCD::OPC_Decode, 231, 3, 15, // Opcode: FMOV_S
+/* 1751 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1765
+/* 1756 */ MCD::OPC_CheckPredicate, 2, 250, 14, 0, // Skip to: 5595
+/* 1761 */ MCD::OPC_Decode, 230, 3, 16, // Opcode: FMOV_D
+/* 1765 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 1779
+/* 1770 */ MCD::OPC_CheckPredicate, 1, 236, 14, 0, // Skip to: 5595
+/* 1775 */ MCD::OPC_Decode, 217, 4, 17, // Opcode: MOVGR2FR_W
+/* 1779 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 1793
+/* 1784 */ MCD::OPC_CheckPredicate, 3, 222, 14, 0, // Skip to: 5595
+/* 1789 */ MCD::OPC_Decode, 216, 4, 18, // Opcode: MOVGR2FR_D
+/* 1793 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 1807
+/* 1798 */ MCD::OPC_CheckPredicate, 2, 208, 14, 0, // Skip to: 5595
+/* 1803 */ MCD::OPC_Decode, 215, 4, 19, // Opcode: MOVGR2FRH_W
+/* 1807 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 1821
+/* 1812 */ MCD::OPC_CheckPredicate, 1, 194, 14, 0, // Skip to: 5595
+/* 1817 */ MCD::OPC_Decode, 210, 4, 20, // Opcode: MOVFR2GR_S
+/* 1821 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 1835
+/* 1826 */ MCD::OPC_CheckPredicate, 3, 180, 14, 0, // Skip to: 5595
+/* 1831 */ MCD::OPC_Decode, 209, 4, 21, // Opcode: MOVFR2GR_D
+/* 1835 */ MCD::OPC_FilterValue, 15, 9, 0, 0, // Skip to: 1849
+/* 1840 */ MCD::OPC_CheckPredicate, 2, 166, 14, 0, // Skip to: 5595
+/* 1845 */ MCD::OPC_Decode, 212, 4, 21, // Opcode: MOVFRH2GR_S
+/* 1849 */ MCD::OPC_FilterValue, 16, 9, 0, 0, // Skip to: 1863
+/* 1854 */ MCD::OPC_CheckPredicate, 1, 152, 14, 0, // Skip to: 5595
+/* 1859 */ MCD::OPC_Decode, 214, 4, 22, // Opcode: MOVGR2FCSR
+/* 1863 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 1877
+/* 1868 */ MCD::OPC_CheckPredicate, 1, 138, 14, 0, // Skip to: 5595
+/* 1873 */ MCD::OPC_Decode, 207, 4, 23, // Opcode: MOVFCSR2GR
+/* 1877 */ MCD::OPC_FilterValue, 20, 9, 0, 0, // Skip to: 1891
+/* 1882 */ MCD::OPC_CheckPredicate, 1, 124, 14, 0, // Skip to: 5595
+/* 1887 */ MCD::OPC_Decode, 208, 4, 24, // Opcode: MOVFR2CF_S
+/* 1891 */ MCD::OPC_FilterValue, 21, 9, 0, 0, // Skip to: 1905
+/* 1896 */ MCD::OPC_CheckPredicate, 1, 110, 14, 0, // Skip to: 5595
+/* 1901 */ MCD::OPC_Decode, 205, 4, 25, // Opcode: MOVCF2FR_S
+/* 1905 */ MCD::OPC_FilterValue, 22, 9, 0, 0, // Skip to: 1919
+/* 1910 */ MCD::OPC_CheckPredicate, 1, 96, 14, 0, // Skip to: 5595
+/* 1915 */ MCD::OPC_Decode, 213, 4, 26, // Opcode: MOVGR2CF
+/* 1919 */ MCD::OPC_FilterValue, 23, 87, 14, 0, // Skip to: 5595
+/* 1924 */ MCD::OPC_CheckPredicate, 1, 82, 14, 0, // Skip to: 5595
+/* 1929 */ MCD::OPC_Decode, 206, 4, 27, // Opcode: MOVCF2GR
+/* 1933 */ MCD::OPC_FilterValue, 50, 31, 0, 0, // Skip to: 1969
+/* 1938 */ MCD::OPC_ExtractField, 10, 5, // Inst{14-10} ...
+/* 1941 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1955
+/* 1946 */ MCD::OPC_CheckPredicate, 2, 60, 14, 0, // Skip to: 5595
+/* 1951 */ MCD::OPC_Decode, 203, 3, 28, // Opcode: FCVT_S_D
+/* 1955 */ MCD::OPC_FilterValue, 9, 51, 14, 0, // Skip to: 5595
+/* 1960 */ MCD::OPC_CheckPredicate, 2, 46, 14, 0, // Skip to: 5595
+/* 1965 */ MCD::OPC_Decode, 202, 3, 29, // Opcode: FCVT_D_S
+/* 1969 */ MCD::OPC_FilterValue, 52, 115, 0, 0, // Skip to: 2089
+/* 1974 */ MCD::OPC_ExtractField, 10, 5, // Inst{14-10} ...
+/* 1977 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1991
+/* 1982 */ MCD::OPC_CheckPredicate, 1, 24, 14, 0, // Skip to: 5595
+/* 1987 */ MCD::OPC_Decode, 139, 4, 15, // Opcode: FTINTRM_W_S
+/* 1991 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2005
+/* 1996 */ MCD::OPC_CheckPredicate, 2, 10, 14, 0, // Skip to: 5595
+/* 2001 */ MCD::OPC_Decode, 138, 4, 28, // Opcode: FTINTRM_W_D
+/* 2005 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2019
+/* 2010 */ MCD::OPC_CheckPredicate, 2, 252, 13, 0, // Skip to: 5595
+/* 2015 */ MCD::OPC_Decode, 137, 4, 29, // Opcode: FTINTRM_L_S
+/* 2019 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 2033
+/* 2024 */ MCD::OPC_CheckPredicate, 2, 238, 13, 0, // Skip to: 5595
+/* 2029 */ MCD::OPC_Decode, 136, 4, 16, // Opcode: FTINTRM_L_D
+/* 2033 */ MCD::OPC_FilterValue, 17, 9, 0, 0, // Skip to: 2047
+/* 2038 */ MCD::OPC_CheckPredicate, 1, 224, 13, 0, // Skip to: 5595
+/* 2043 */ MCD::OPC_Decode, 147, 4, 15, // Opcode: FTINTRP_W_S
+/* 2047 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 2061
+/* 2052 */ MCD::OPC_CheckPredicate, 2, 210, 13, 0, // Skip to: 5595
+/* 2057 */ MCD::OPC_Decode, 146, 4, 28, // Opcode: FTINTRP_W_D
+/* 2061 */ MCD::OPC_FilterValue, 25, 9, 0, 0, // Skip to: 2075
+/* 2066 */ MCD::OPC_CheckPredicate, 2, 196, 13, 0, // Skip to: 5595
+/* 2071 */ MCD::OPC_Decode, 145, 4, 29, // Opcode: FTINTRP_L_S
+/* 2075 */ MCD::OPC_FilterValue, 26, 187, 13, 0, // Skip to: 5595
+/* 2080 */ MCD::OPC_CheckPredicate, 2, 182, 13, 0, // Skip to: 5595
+/* 2085 */ MCD::OPC_Decode, 144, 4, 16, // Opcode: FTINTRP_L_D
+/* 2089 */ MCD::OPC_FilterValue, 53, 115, 0, 0, // Skip to: 2209
+/* 2094 */ MCD::OPC_ExtractField, 10, 5, // Inst{14-10} ...
+/* 2097 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2111
+/* 2102 */ MCD::OPC_CheckPredicate, 1, 160, 13, 0, // Skip to: 5595
+/* 2107 */ MCD::OPC_Decode, 151, 4, 15, // Opcode: FTINTRZ_W_S
+/* 2111 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2125
+/* 2116 */ MCD::OPC_CheckPredicate, 2, 146, 13, 0, // Skip to: 5595
+/* 2121 */ MCD::OPC_Decode, 150, 4, 28, // Opcode: FTINTRZ_W_D
+/* 2125 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2139
+/* 2130 */ MCD::OPC_CheckPredicate, 2, 132, 13, 0, // Skip to: 5595
+/* 2135 */ MCD::OPC_Decode, 149, 4, 29, // Opcode: FTINTRZ_L_S
+/* 2139 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 2153
+/* 2144 */ MCD::OPC_CheckPredicate, 2, 118, 13, 0, // Skip to: 5595
+/* 2149 */ MCD::OPC_Decode, 148, 4, 16, // Opcode: FTINTRZ_L_D
+/* 2153 */ MCD::OPC_FilterValue, 17, 9, 0, 0, // Skip to: 2167
+/* 2158 */ MCD::OPC_CheckPredicate, 1, 104, 13, 0, // Skip to: 5595
+/* 2163 */ MCD::OPC_Decode, 143, 4, 15, // Opcode: FTINTRNE_W_S
+/* 2167 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 2181
+/* 2172 */ MCD::OPC_CheckPredicate, 2, 90, 13, 0, // Skip to: 5595
+/* 2177 */ MCD::OPC_Decode, 142, 4, 28, // Opcode: FTINTRNE_W_D
+/* 2181 */ MCD::OPC_FilterValue, 25, 9, 0, 0, // Skip to: 2195
+/* 2186 */ MCD::OPC_CheckPredicate, 2, 76, 13, 0, // Skip to: 5595
+/* 2191 */ MCD::OPC_Decode, 141, 4, 29, // Opcode: FTINTRNE_L_S
+/* 2195 */ MCD::OPC_FilterValue, 26, 67, 13, 0, // Skip to: 5595
+/* 2200 */ MCD::OPC_CheckPredicate, 2, 62, 13, 0, // Skip to: 5595
+/* 2205 */ MCD::OPC_Decode, 140, 4, 16, // Opcode: FTINTRNE_L_D
+/* 2209 */ MCD::OPC_FilterValue, 54, 59, 0, 0, // Skip to: 2273
+/* 2214 */ MCD::OPC_ExtractField, 10, 5, // Inst{14-10} ...
+/* 2217 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2231
+/* 2222 */ MCD::OPC_CheckPredicate, 1, 40, 13, 0, // Skip to: 5595
+/* 2227 */ MCD::OPC_Decode, 155, 4, 15, // Opcode: FTINT_W_S
+/* 2231 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2245
+/* 2236 */ MCD::OPC_CheckPredicate, 2, 26, 13, 0, // Skip to: 5595
+/* 2241 */ MCD::OPC_Decode, 154, 4, 28, // Opcode: FTINT_W_D
+/* 2245 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2259
+/* 2250 */ MCD::OPC_CheckPredicate, 2, 12, 13, 0, // Skip to: 5595
+/* 2255 */ MCD::OPC_Decode, 153, 4, 29, // Opcode: FTINT_L_S
+/* 2259 */ MCD::OPC_FilterValue, 10, 3, 13, 0, // Skip to: 5595
+/* 2264 */ MCD::OPC_CheckPredicate, 2, 254, 12, 0, // Skip to: 5595
+/* 2269 */ MCD::OPC_Decode, 152, 4, 16, // Opcode: FTINT_L_D
+/* 2273 */ MCD::OPC_FilterValue, 58, 59, 0, 0, // Skip to: 2337
+/* 2278 */ MCD::OPC_ExtractField, 10, 5, // Inst{14-10} ...
+/* 2281 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2295
+/* 2286 */ MCD::OPC_CheckPredicate, 1, 232, 12, 0, // Skip to: 5595
+/* 2291 */ MCD::OPC_Decode, 209, 3, 15, // Opcode: FFINT_S_W
+/* 2295 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2309
+/* 2300 */ MCD::OPC_CheckPredicate, 2, 218, 12, 0, // Skip to: 5595
+/* 2305 */ MCD::OPC_Decode, 208, 3, 28, // Opcode: FFINT_S_L
+/* 2309 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2323
+/* 2314 */ MCD::OPC_CheckPredicate, 2, 204, 12, 0, // Skip to: 5595
+/* 2319 */ MCD::OPC_Decode, 207, 3, 29, // Opcode: FFINT_D_W
+/* 2323 */ MCD::OPC_FilterValue, 10, 195, 12, 0, // Skip to: 5595
+/* 2328 */ MCD::OPC_CheckPredicate, 2, 190, 12, 0, // Skip to: 5595
+/* 2333 */ MCD::OPC_Decode, 206, 3, 16, // Opcode: FFINT_D_L
+/* 2337 */ MCD::OPC_FilterValue, 60, 181, 12, 0, // Skip to: 5595
+/* 2342 */ MCD::OPC_ExtractField, 10, 5, // Inst{14-10} ...
+/* 2345 */ MCD::OPC_FilterValue, 17, 9, 0, 0, // Skip to: 2359
+/* 2350 */ MCD::OPC_CheckPredicate, 1, 168, 12, 0, // Skip to: 5595
+/* 2355 */ MCD::OPC_Decode, 245, 3, 15, // Opcode: FRINT_S
+/* 2359 */ MCD::OPC_FilterValue, 18, 159, 12, 0, // Skip to: 5595
+/* 2364 */ MCD::OPC_CheckPredicate, 2, 154, 12, 0, // Skip to: 5595
+/* 2369 */ MCD::OPC_Decode, 244, 3, 16, // Opcode: FRINT_D
+/* 2373 */ MCD::OPC_FilterValue, 8, 4, 0, 0, // Skip to: 2382
+/* 2378 */ MCD::OPC_Decode, 129, 5, 30, // Opcode: SLTI
+/* 2382 */ MCD::OPC_FilterValue, 9, 4, 0, 0, // Skip to: 2391
+/* 2387 */ MCD::OPC_Decode, 131, 5, 30, // Opcode: SLTUI
+/* 2391 */ MCD::OPC_FilterValue, 10, 4, 0, 0, // Skip to: 2400
+/* 2396 */ MCD::OPC_Decode, 177, 2, 30, // Opcode: ADDI_W
+/* 2400 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 2414
+/* 2405 */ MCD::OPC_CheckPredicate, 0, 113, 12, 0, // Skip to: 5595
+/* 2410 */ MCD::OPC_Decode, 176, 2, 30, // Opcode: ADDI_D
+/* 2414 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 2428
+/* 2419 */ MCD::OPC_CheckPredicate, 0, 99, 12, 0, // Skip to: 5595
+/* 2424 */ MCD::OPC_Decode, 198, 4, 30, // Opcode: LU52I_D
+/* 2428 */ MCD::OPC_FilterValue, 13, 4, 0, 0, // Skip to: 2437
+/* 2433 */ MCD::OPC_Decode, 221, 2, 31, // Opcode: ANDI
+/* 2437 */ MCD::OPC_FilterValue, 14, 4, 0, 0, // Skip to: 2446
+/* 2442 */ MCD::OPC_Decode, 229, 4, 31, // Opcode: ORI
+/* 2446 */ MCD::OPC_FilterValue, 15, 72, 12, 0, // Skip to: 5595
+/* 2451 */ MCD::OPC_Decode, 168, 5, 31, // Opcode: XORI
+/* 2455 */ MCD::OPC_FilterValue, 1, 55, 1, 0, // Skip to: 2771
+/* 2460 */ MCD::OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 2463 */ MCD::OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2493
+/* 2468 */ MCD::OPC_ExtractField, 5, 5, // Inst{9-5} ...
+/* 2471 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2480
+/* 2476 */ MCD::OPC_Decode, 134, 3, 32, // Opcode: CSRRD
+/* 2480 */ MCD::OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2489
+/* 2485 */ MCD::OPC_Decode, 135, 3, 33, // Opcode: CSRWR
+/* 2489 */ MCD::OPC_Decode, 136, 3, 34, // Opcode: CSRXCHG
+/* 2493 */ MCD::OPC_FilterValue, 2, 25, 12, 0, // Skip to: 5595
+/* 2498 */ MCD::OPC_ExtractField, 22, 2, // Inst{23-22} ...
+/* 2501 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2510
+/* 2506 */ MCD::OPC_Decode, 248, 2, 35, // Opcode: CACOP
+/* 2510 */ MCD::OPC_FilterValue, 1, 8, 12, 0, // Skip to: 5595
+/* 2515 */ MCD::OPC_ExtractField, 18, 4, // Inst{21-18} ...
+/* 2518 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2527
+/* 2523 */ MCD::OPC_Decode, 168, 4, 36, // Opcode: LDDIR
+/* 2527 */ MCD::OPC_FilterValue, 1, 11, 0, 0, // Skip to: 2543
+/* 2532 */ MCD::OPC_CheckField, 0, 5, 0, 240, 11, 0, // Skip to: 5595
+/* 2539 */ MCD::OPC_Decode, 177, 4, 37, // Opcode: LDPTE
+/* 2543 */ MCD::OPC_FilterValue, 2, 231, 11, 0, // Skip to: 5595
+/* 2548 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 2551 */ MCD::OPC_FilterValue, 0, 197, 0, 0, // Skip to: 2753
+/* 2556 */ MCD::OPC_ExtractField, 10, 5, // Inst{14-10} ...
+/* 2559 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2568
+/* 2564 */ MCD::OPC_Decode, 159, 4, 0, // Opcode: IOCSRRD_B
+/* 2568 */ MCD::OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2577
+/* 2573 */ MCD::OPC_Decode, 161, 4, 0, // Opcode: IOCSRRD_H
+/* 2577 */ MCD::OPC_FilterValue, 2, 4, 0, 0, // Skip to: 2586
+/* 2582 */ MCD::OPC_Decode, 162, 4, 0, // Opcode: IOCSRRD_W
+/* 2586 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2600
+/* 2591 */ MCD::OPC_CheckPredicate, 0, 183, 11, 0, // Skip to: 5595
+/* 2596 */ MCD::OPC_Decode, 160, 4, 0, // Opcode: IOCSRRD_D
+/* 2600 */ MCD::OPC_FilterValue, 4, 4, 0, 0, // Skip to: 2609
+/* 2605 */ MCD::OPC_Decode, 163, 4, 0, // Opcode: IOCSRWR_B
+/* 2609 */ MCD::OPC_FilterValue, 5, 4, 0, 0, // Skip to: 2618
+/* 2614 */ MCD::OPC_Decode, 165, 4, 0, // Opcode: IOCSRWR_H
+/* 2618 */ MCD::OPC_FilterValue, 6, 4, 0, 0, // Skip to: 2627
+/* 2623 */ MCD::OPC_Decode, 166, 4, 0, // Opcode: IOCSRWR_W
+/* 2627 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 2641
+/* 2632 */ MCD::OPC_CheckPredicate, 0, 142, 11, 0, // Skip to: 5595
+/* 2637 */ MCD::OPC_Decode, 164, 4, 0, // Opcode: IOCSRWR_D
+/* 2641 */ MCD::OPC_FilterValue, 8, 11, 0, 0, // Skip to: 2657
+/* 2646 */ MCD::OPC_CheckField, 0, 10, 0, 126, 11, 0, // Skip to: 5595
+/* 2653 */ MCD::OPC_Decode, 161, 5, 38, // Opcode: TLBCLR
+/* 2657 */ MCD::OPC_FilterValue, 9, 11, 0, 0, // Skip to: 2673
+/* 2662 */ MCD::OPC_CheckField, 0, 10, 0, 110, 11, 0, // Skip to: 5595
+/* 2669 */ MCD::OPC_Decode, 163, 5, 38, // Opcode: TLBFLUSH
+/* 2673 */ MCD::OPC_FilterValue, 10, 11, 0, 0, // Skip to: 2689
+/* 2678 */ MCD::OPC_CheckField, 0, 10, 0, 94, 11, 0, // Skip to: 5595
+/* 2685 */ MCD::OPC_Decode, 165, 5, 38, // Opcode: TLBSRCH
+/* 2689 */ MCD::OPC_FilterValue, 11, 11, 0, 0, // Skip to: 2705
+/* 2694 */ MCD::OPC_CheckField, 0, 10, 0, 78, 11, 0, // Skip to: 5595
+/* 2701 */ MCD::OPC_Decode, 164, 5, 38, // Opcode: TLBRD
+/* 2705 */ MCD::OPC_FilterValue, 12, 11, 0, 0, // Skip to: 2721
+/* 2710 */ MCD::OPC_CheckField, 0, 10, 0, 62, 11, 0, // Skip to: 5595
+/* 2717 */ MCD::OPC_Decode, 166, 5, 38, // Opcode: TLBWR
+/* 2721 */ MCD::OPC_FilterValue, 13, 11, 0, 0, // Skip to: 2737
+/* 2726 */ MCD::OPC_CheckField, 0, 10, 0, 46, 11, 0, // Skip to: 5595
+/* 2733 */ MCD::OPC_Decode, 162, 5, 38, // Opcode: TLBFILL
+/* 2737 */ MCD::OPC_FilterValue, 14, 37, 11, 0, // Skip to: 5595
+/* 2742 */ MCD::OPC_CheckField, 0, 10, 0, 30, 11, 0, // Skip to: 5595
+/* 2749 */ MCD::OPC_Decode, 147, 3, 38, // Opcode: ERTN
+/* 2753 */ MCD::OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2762
+/* 2758 */ MCD::OPC_Decode, 157, 4, 6, // Opcode: IDLE
+/* 2762 */ MCD::OPC_FilterValue, 3, 12, 11, 0, // Skip to: 5595
+/* 2767 */ MCD::OPC_Decode, 158, 4, 39, // Opcode: INVTLB
+/* 2771 */ MCD::OPC_FilterValue, 2, 115, 0, 0, // Skip to: 2891
+/* 2776 */ MCD::OPC_ExtractField, 20, 6, // Inst{25-20} ...
+/* 2779 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2793
+/* 2784 */ MCD::OPC_CheckPredicate, 1, 246, 10, 0, // Skip to: 5595
+/* 2789 */ MCD::OPC_Decode, 221, 3, 40, // Opcode: FMADD_S
+/* 2793 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2807
+/* 2798 */ MCD::OPC_CheckPredicate, 2, 232, 10, 0, // Skip to: 5595
+/* 2803 */ MCD::OPC_Decode, 220, 3, 41, // Opcode: FMADD_D
+/* 2807 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2821
+/* 2812 */ MCD::OPC_CheckPredicate, 1, 218, 10, 0, // Skip to: 5595
+/* 2817 */ MCD::OPC_Decode, 233, 3, 40, // Opcode: FMSUB_S
+/* 2821 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2835
+/* 2826 */ MCD::OPC_CheckPredicate, 2, 204, 10, 0, // Skip to: 5595
+/* 2831 */ MCD::OPC_Decode, 232, 3, 41, // Opcode: FMSUB_D
+/* 2835 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2849
+/* 2840 */ MCD::OPC_CheckPredicate, 1, 190, 10, 0, // Skip to: 5595
+/* 2845 */ MCD::OPC_Decode, 239, 3, 40, // Opcode: FNMADD_S
+/* 2849 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 2863
+/* 2854 */ MCD::OPC_CheckPredicate, 2, 176, 10, 0, // Skip to: 5595
+/* 2859 */ MCD::OPC_Decode, 238, 3, 41, // Opcode: FNMADD_D
+/* 2863 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 2877
+/* 2868 */ MCD::OPC_CheckPredicate, 1, 162, 10, 0, // Skip to: 5595
+/* 2873 */ MCD::OPC_Decode, 241, 3, 40, // Opcode: FNMSUB_S
+/* 2877 */ MCD::OPC_FilterValue, 14, 153, 10, 0, // Skip to: 5595
+/* 2882 */ MCD::OPC_CheckPredicate, 2, 148, 10, 0, // Skip to: 5595
+/* 2887 */ MCD::OPC_Decode, 240, 3, 41, // Opcode: FNMSUB_D
+/* 2891 */ MCD::OPC_FilterValue, 3, 237, 3, 0, // Skip to: 3901
+/* 2896 */ MCD::OPC_ExtractField, 18, 8, // Inst{25-18} ...
+/* 2899 */ MCD::OPC_FilterValue, 4, 171, 0, 0, // Skip to: 3075
+/* 2904 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 2907 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2928
+/* 2912 */ MCD::OPC_CheckPredicate, 1, 118, 10, 0, // Skip to: 5595
+/* 2917 */ MCD::OPC_CheckField, 3, 2, 0, 111, 10, 0, // Skip to: 5595
+/* 2924 */ MCD::OPC_Decode, 157, 3, 42, // Opcode: FCMP_CAF_S
+/* 2928 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 2949
+/* 2933 */ MCD::OPC_CheckPredicate, 1, 97, 10, 0, // Skip to: 5595
+/* 2938 */ MCD::OPC_CheckField, 3, 2, 0, 90, 10, 0, // Skip to: 5595
+/* 2945 */ MCD::OPC_Decode, 179, 3, 42, // Opcode: FCMP_SAF_S
+/* 2949 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2970
+/* 2954 */ MCD::OPC_CheckPredicate, 1, 76, 10, 0, // Skip to: 5595
+/* 2959 */ MCD::OPC_CheckField, 3, 2, 0, 69, 10, 0, // Skip to: 5595
+/* 2966 */ MCD::OPC_Decode, 163, 3, 42, // Opcode: FCMP_CLT_S
+/* 2970 */ MCD::OPC_FilterValue, 3, 16, 0, 0, // Skip to: 2991
+/* 2975 */ MCD::OPC_CheckPredicate, 1, 55, 10, 0, // Skip to: 5595
+/* 2980 */ MCD::OPC_CheckField, 3, 2, 0, 48, 10, 0, // Skip to: 5595
+/* 2987 */ MCD::OPC_Decode, 185, 3, 42, // Opcode: FCMP_SLT_S
+/* 2991 */ MCD::OPC_FilterValue, 4, 16, 0, 0, // Skip to: 3012
+/* 2996 */ MCD::OPC_CheckPredicate, 1, 34, 10, 0, // Skip to: 5595
+/* 3001 */ MCD::OPC_CheckField, 3, 2, 0, 27, 10, 0, // Skip to: 5595
+/* 3008 */ MCD::OPC_Decode, 159, 3, 42, // Opcode: FCMP_CEQ_S
+/* 3012 */ MCD::OPC_FilterValue, 5, 16, 0, 0, // Skip to: 3033
+/* 3017 */ MCD::OPC_CheckPredicate, 1, 13, 10, 0, // Skip to: 5595
+/* 3022 */ MCD::OPC_CheckField, 3, 2, 0, 6, 10, 0, // Skip to: 5595
+/* 3029 */ MCD::OPC_Decode, 181, 3, 42, // Opcode: FCMP_SEQ_S
+/* 3033 */ MCD::OPC_FilterValue, 6, 16, 0, 0, // Skip to: 3054
+/* 3038 */ MCD::OPC_CheckPredicate, 1, 248, 9, 0, // Skip to: 5595
+/* 3043 */ MCD::OPC_CheckField, 3, 2, 0, 241, 9, 0, // Skip to: 5595
+/* 3050 */ MCD::OPC_Decode, 161, 3, 42, // Opcode: FCMP_CLE_S
+/* 3054 */ MCD::OPC_FilterValue, 7, 232, 9, 0, // Skip to: 5595
+/* 3059 */ MCD::OPC_CheckPredicate, 1, 227, 9, 0, // Skip to: 5595
+/* 3064 */ MCD::OPC_CheckField, 3, 2, 0, 220, 9, 0, // Skip to: 5595
+/* 3071 */ MCD::OPC_Decode, 183, 3, 42, // Opcode: FCMP_SLE_S
+/* 3075 */ MCD::OPC_FilterValue, 5, 171, 0, 0, // Skip to: 3251
+/* 3080 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 3083 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3104
+/* 3088 */ MCD::OPC_CheckPredicate, 1, 198, 9, 0, // Skip to: 5595
+/* 3093 */ MCD::OPC_CheckField, 3, 2, 0, 191, 9, 0, // Skip to: 5595
+/* 3100 */ MCD::OPC_Decode, 177, 3, 42, // Opcode: FCMP_CUN_S
+/* 3104 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3125
+/* 3109 */ MCD::OPC_CheckPredicate, 1, 177, 9, 0, // Skip to: 5595
+/* 3114 */ MCD::OPC_CheckField, 3, 2, 0, 170, 9, 0, // Skip to: 5595
+/* 3121 */ MCD::OPC_Decode, 199, 3, 42, // Opcode: FCMP_SUN_S
+/* 3125 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 3146
+/* 3130 */ MCD::OPC_CheckPredicate, 1, 156, 9, 0, // Skip to: 5595
+/* 3135 */ MCD::OPC_CheckField, 3, 2, 0, 149, 9, 0, // Skip to: 5595
+/* 3142 */ MCD::OPC_Decode, 173, 3, 42, // Opcode: FCMP_CULT_S
+/* 3146 */ MCD::OPC_FilterValue, 3, 16, 0, 0, // Skip to: 3167
+/* 3151 */ MCD::OPC_CheckPredicate, 1, 135, 9, 0, // Skip to: 5595
+/* 3156 */ MCD::OPC_CheckField, 3, 2, 0, 128, 9, 0, // Skip to: 5595
+/* 3163 */ MCD::OPC_Decode, 195, 3, 42, // Opcode: FCMP_SULT_S
+/* 3167 */ MCD::OPC_FilterValue, 4, 16, 0, 0, // Skip to: 3188
+/* 3172 */ MCD::OPC_CheckPredicate, 1, 114, 9, 0, // Skip to: 5595
+/* 3177 */ MCD::OPC_CheckField, 3, 2, 0, 107, 9, 0, // Skip to: 5595
+/* 3184 */ MCD::OPC_Decode, 169, 3, 42, // Opcode: FCMP_CUEQ_S
+/* 3188 */ MCD::OPC_FilterValue, 5, 16, 0, 0, // Skip to: 3209
+/* 3193 */ MCD::OPC_CheckPredicate, 1, 93, 9, 0, // Skip to: 5595
+/* 3198 */ MCD::OPC_CheckField, 3, 2, 0, 86, 9, 0, // Skip to: 5595
+/* 3205 */ MCD::OPC_Decode, 191, 3, 42, // Opcode: FCMP_SUEQ_S
+/* 3209 */ MCD::OPC_FilterValue, 6, 16, 0, 0, // Skip to: 3230
+/* 3214 */ MCD::OPC_CheckPredicate, 1, 72, 9, 0, // Skip to: 5595
+/* 3219 */ MCD::OPC_CheckField, 3, 2, 0, 65, 9, 0, // Skip to: 5595
+/* 3226 */ MCD::OPC_Decode, 171, 3, 42, // Opcode: FCMP_CULE_S
+/* 3230 */ MCD::OPC_FilterValue, 7, 56, 9, 0, // Skip to: 5595
+/* 3235 */ MCD::OPC_CheckPredicate, 1, 51, 9, 0, // Skip to: 5595
+/* 3240 */ MCD::OPC_CheckField, 3, 2, 0, 44, 9, 0, // Skip to: 5595
+/* 3247 */ MCD::OPC_Decode, 193, 3, 42, // Opcode: FCMP_SULE_S
+/* 3251 */ MCD::OPC_FilterValue, 6, 87, 0, 0, // Skip to: 3343
+/* 3256 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 3259 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3280
+/* 3264 */ MCD::OPC_CheckPredicate, 1, 22, 9, 0, // Skip to: 5595
+/* 3269 */ MCD::OPC_CheckField, 3, 2, 0, 15, 9, 0, // Skip to: 5595
+/* 3276 */ MCD::OPC_Decode, 165, 3, 42, // Opcode: FCMP_CNE_S
+/* 3280 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3301
+/* 3285 */ MCD::OPC_CheckPredicate, 1, 1, 9, 0, // Skip to: 5595
+/* 3290 */ MCD::OPC_CheckField, 3, 2, 0, 250, 8, 0, // Skip to: 5595
+/* 3297 */ MCD::OPC_Decode, 187, 3, 42, // Opcode: FCMP_SNE_S
+/* 3301 */ MCD::OPC_FilterValue, 4, 16, 0, 0, // Skip to: 3322
+/* 3306 */ MCD::OPC_CheckPredicate, 1, 236, 8, 0, // Skip to: 5595
+/* 3311 */ MCD::OPC_CheckField, 3, 2, 0, 229, 8, 0, // Skip to: 5595
+/* 3318 */ MCD::OPC_Decode, 167, 3, 42, // Opcode: FCMP_COR_S
+/* 3322 */ MCD::OPC_FilterValue, 5, 220, 8, 0, // Skip to: 5595
+/* 3327 */ MCD::OPC_CheckPredicate, 1, 215, 8, 0, // Skip to: 5595
+/* 3332 */ MCD::OPC_CheckField, 3, 2, 0, 208, 8, 0, // Skip to: 5595
+/* 3339 */ MCD::OPC_Decode, 189, 3, 42, // Opcode: FCMP_SOR_S
+/* 3343 */ MCD::OPC_FilterValue, 7, 45, 0, 0, // Skip to: 3393
+/* 3348 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 3351 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3372
+/* 3356 */ MCD::OPC_CheckPredicate, 1, 186, 8, 0, // Skip to: 5595
+/* 3361 */ MCD::OPC_CheckField, 3, 2, 0, 179, 8, 0, // Skip to: 5595
+/* 3368 */ MCD::OPC_Decode, 175, 3, 42, // Opcode: FCMP_CUNE_S
+/* 3372 */ MCD::OPC_FilterValue, 1, 170, 8, 0, // Skip to: 5595
+/* 3377 */ MCD::OPC_CheckPredicate, 1, 165, 8, 0, // Skip to: 5595
+/* 3382 */ MCD::OPC_CheckField, 3, 2, 0, 158, 8, 0, // Skip to: 5595
+/* 3389 */ MCD::OPC_Decode, 197, 3, 42, // Opcode: FCMP_SUNE_S
+/* 3393 */ MCD::OPC_FilterValue, 8, 171, 0, 0, // Skip to: 3569
+/* 3398 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 3401 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3422
+/* 3406 */ MCD::OPC_CheckPredicate, 2, 136, 8, 0, // Skip to: 5595
+/* 3411 */ MCD::OPC_CheckField, 3, 2, 0, 129, 8, 0, // Skip to: 5595
+/* 3418 */ MCD::OPC_Decode, 156, 3, 43, // Opcode: FCMP_CAF_D
+/* 3422 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3443
+/* 3427 */ MCD::OPC_CheckPredicate, 2, 115, 8, 0, // Skip to: 5595
+/* 3432 */ MCD::OPC_CheckField, 3, 2, 0, 108, 8, 0, // Skip to: 5595
+/* 3439 */ MCD::OPC_Decode, 178, 3, 43, // Opcode: FCMP_SAF_D
+/* 3443 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 3464
+/* 3448 */ MCD::OPC_CheckPredicate, 2, 94, 8, 0, // Skip to: 5595
+/* 3453 */ MCD::OPC_CheckField, 3, 2, 0, 87, 8, 0, // Skip to: 5595
+/* 3460 */ MCD::OPC_Decode, 162, 3, 43, // Opcode: FCMP_CLT_D
+/* 3464 */ MCD::OPC_FilterValue, 3, 16, 0, 0, // Skip to: 3485
+/* 3469 */ MCD::OPC_CheckPredicate, 2, 73, 8, 0, // Skip to: 5595
+/* 3474 */ MCD::OPC_CheckField, 3, 2, 0, 66, 8, 0, // Skip to: 5595
+/* 3481 */ MCD::OPC_Decode, 184, 3, 43, // Opcode: FCMP_SLT_D
+/* 3485 */ MCD::OPC_FilterValue, 4, 16, 0, 0, // Skip to: 3506
+/* 3490 */ MCD::OPC_CheckPredicate, 2, 52, 8, 0, // Skip to: 5595
+/* 3495 */ MCD::OPC_CheckField, 3, 2, 0, 45, 8, 0, // Skip to: 5595
+/* 3502 */ MCD::OPC_Decode, 158, 3, 43, // Opcode: FCMP_CEQ_D
+/* 3506 */ MCD::OPC_FilterValue, 5, 16, 0, 0, // Skip to: 3527
+/* 3511 */ MCD::OPC_CheckPredicate, 2, 31, 8, 0, // Skip to: 5595
+/* 3516 */ MCD::OPC_CheckField, 3, 2, 0, 24, 8, 0, // Skip to: 5595
+/* 3523 */ MCD::OPC_Decode, 180, 3, 43, // Opcode: FCMP_SEQ_D
+/* 3527 */ MCD::OPC_FilterValue, 6, 16, 0, 0, // Skip to: 3548
+/* 3532 */ MCD::OPC_CheckPredicate, 2, 10, 8, 0, // Skip to: 5595
+/* 3537 */ MCD::OPC_CheckField, 3, 2, 0, 3, 8, 0, // Skip to: 5595
+/* 3544 */ MCD::OPC_Decode, 160, 3, 43, // Opcode: FCMP_CLE_D
+/* 3548 */ MCD::OPC_FilterValue, 7, 250, 7, 0, // Skip to: 5595
+/* 3553 */ MCD::OPC_CheckPredicate, 2, 245, 7, 0, // Skip to: 5595
+/* 3558 */ MCD::OPC_CheckField, 3, 2, 0, 238, 7, 0, // Skip to: 5595
+/* 3565 */ MCD::OPC_Decode, 182, 3, 43, // Opcode: FCMP_SLE_D
+/* 3569 */ MCD::OPC_FilterValue, 9, 171, 0, 0, // Skip to: 3745
+/* 3574 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 3577 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3598
+/* 3582 */ MCD::OPC_CheckPredicate, 2, 216, 7, 0, // Skip to: 5595
+/* 3587 */ MCD::OPC_CheckField, 3, 2, 0, 209, 7, 0, // Skip to: 5595
+/* 3594 */ MCD::OPC_Decode, 176, 3, 43, // Opcode: FCMP_CUN_D
+/* 3598 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3619
+/* 3603 */ MCD::OPC_CheckPredicate, 2, 195, 7, 0, // Skip to: 5595
+/* 3608 */ MCD::OPC_CheckField, 3, 2, 0, 188, 7, 0, // Skip to: 5595
+/* 3615 */ MCD::OPC_Decode, 198, 3, 43, // Opcode: FCMP_SUN_D
+/* 3619 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 3640
+/* 3624 */ MCD::OPC_CheckPredicate, 2, 174, 7, 0, // Skip to: 5595
+/* 3629 */ MCD::OPC_CheckField, 3, 2, 0, 167, 7, 0, // Skip to: 5595
+/* 3636 */ MCD::OPC_Decode, 172, 3, 43, // Opcode: FCMP_CULT_D
+/* 3640 */ MCD::OPC_FilterValue, 3, 16, 0, 0, // Skip to: 3661
+/* 3645 */ MCD::OPC_CheckPredicate, 2, 153, 7, 0, // Skip to: 5595
+/* 3650 */ MCD::OPC_CheckField, 3, 2, 0, 146, 7, 0, // Skip to: 5595
+/* 3657 */ MCD::OPC_Decode, 194, 3, 43, // Opcode: FCMP_SULT_D
+/* 3661 */ MCD::OPC_FilterValue, 4, 16, 0, 0, // Skip to: 3682
+/* 3666 */ MCD::OPC_CheckPredicate, 2, 132, 7, 0, // Skip to: 5595
+/* 3671 */ MCD::OPC_CheckField, 3, 2, 0, 125, 7, 0, // Skip to: 5595
+/* 3678 */ MCD::OPC_Decode, 168, 3, 43, // Opcode: FCMP_CUEQ_D
+/* 3682 */ MCD::OPC_FilterValue, 5, 16, 0, 0, // Skip to: 3703
+/* 3687 */ MCD::OPC_CheckPredicate, 2, 111, 7, 0, // Skip to: 5595
+/* 3692 */ MCD::OPC_CheckField, 3, 2, 0, 104, 7, 0, // Skip to: 5595
+/* 3699 */ MCD::OPC_Decode, 190, 3, 43, // Opcode: FCMP_SUEQ_D
+/* 3703 */ MCD::OPC_FilterValue, 6, 16, 0, 0, // Skip to: 3724
+/* 3708 */ MCD::OPC_CheckPredicate, 2, 90, 7, 0, // Skip to: 5595
+/* 3713 */ MCD::OPC_CheckField, 3, 2, 0, 83, 7, 0, // Skip to: 5595
+/* 3720 */ MCD::OPC_Decode, 170, 3, 43, // Opcode: FCMP_CULE_D
+/* 3724 */ MCD::OPC_FilterValue, 7, 74, 7, 0, // Skip to: 5595
+/* 3729 */ MCD::OPC_CheckPredicate, 2, 69, 7, 0, // Skip to: 5595
+/* 3734 */ MCD::OPC_CheckField, 3, 2, 0, 62, 7, 0, // Skip to: 5595
+/* 3741 */ MCD::OPC_Decode, 192, 3, 43, // Opcode: FCMP_SULE_D
+/* 3745 */ MCD::OPC_FilterValue, 10, 87, 0, 0, // Skip to: 3837
+/* 3750 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 3753 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3774
+/* 3758 */ MCD::OPC_CheckPredicate, 2, 40, 7, 0, // Skip to: 5595
+/* 3763 */ MCD::OPC_CheckField, 3, 2, 0, 33, 7, 0, // Skip to: 5595
+/* 3770 */ MCD::OPC_Decode, 164, 3, 43, // Opcode: FCMP_CNE_D
+/* 3774 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3795
+/* 3779 */ MCD::OPC_CheckPredicate, 2, 19, 7, 0, // Skip to: 5595
+/* 3784 */ MCD::OPC_CheckField, 3, 2, 0, 12, 7, 0, // Skip to: 5595
+/* 3791 */ MCD::OPC_Decode, 186, 3, 43, // Opcode: FCMP_SNE_D
+/* 3795 */ MCD::OPC_FilterValue, 4, 16, 0, 0, // Skip to: 3816
+/* 3800 */ MCD::OPC_CheckPredicate, 2, 254, 6, 0, // Skip to: 5595
+/* 3805 */ MCD::OPC_CheckField, 3, 2, 0, 247, 6, 0, // Skip to: 5595
+/* 3812 */ MCD::OPC_Decode, 166, 3, 43, // Opcode: FCMP_COR_D
+/* 3816 */ MCD::OPC_FilterValue, 5, 238, 6, 0, // Skip to: 5595
+/* 3821 */ MCD::OPC_CheckPredicate, 2, 233, 6, 0, // Skip to: 5595
+/* 3826 */ MCD::OPC_CheckField, 3, 2, 0, 226, 6, 0, // Skip to: 5595
+/* 3833 */ MCD::OPC_Decode, 188, 3, 43, // Opcode: FCMP_SOR_D
+/* 3837 */ MCD::OPC_FilterValue, 11, 45, 0, 0, // Skip to: 3887
+/* 3842 */ MCD::OPC_ExtractField, 15, 3, // Inst{17-15} ...
+/* 3845 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3866
+/* 3850 */ MCD::OPC_CheckPredicate, 2, 204, 6, 0, // Skip to: 5595
+/* 3855 */ MCD::OPC_CheckField, 3, 2, 0, 197, 6, 0, // Skip to: 5595
+/* 3862 */ MCD::OPC_Decode, 174, 3, 43, // Opcode: FCMP_CUNE_D
+/* 3866 */ MCD::OPC_FilterValue, 1, 188, 6, 0, // Skip to: 5595
+/* 3871 */ MCD::OPC_CheckPredicate, 2, 183, 6, 0, // Skip to: 5595
+/* 3876 */ MCD::OPC_CheckField, 3, 2, 0, 176, 6, 0, // Skip to: 5595
+/* 3883 */ MCD::OPC_Decode, 196, 3, 43, // Opcode: FCMP_SUNE_D
+/* 3887 */ MCD::OPC_FilterValue, 64, 167, 6, 0, // Skip to: 5595
+/* 3892 */ MCD::OPC_CheckPredicate, 1, 162, 6, 0, // Skip to: 5595
+/* 3897 */ MCD::OPC_Decode, 251, 3, 44, // Opcode: FSEL_S
+/* 3901 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3915
+/* 3906 */ MCD::OPC_CheckPredicate, 0, 148, 6, 0, // Skip to: 5595
+/* 3911 */ MCD::OPC_Decode, 178, 2, 45, // Opcode: ADDU16I_D
+/* 3915 */ MCD::OPC_FilterValue, 5, 26, 0, 0, // Skip to: 3946
+/* 3920 */ MCD::OPC_ExtractField, 25, 1, // Inst{25} ...
+/* 3923 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3932
+/* 3928 */ MCD::OPC_Decode, 196, 4, 46, // Opcode: LU12I_W
+/* 3932 */ MCD::OPC_FilterValue, 1, 122, 6, 0, // Skip to: 5595
+/* 3937 */ MCD::OPC_CheckPredicate, 0, 117, 6, 0, // Skip to: 5595
+/* 3942 */ MCD::OPC_Decode, 197, 4, 47, // Opcode: LU32I_D
+/* 3946 */ MCD::OPC_FilterValue, 6, 21, 0, 0, // Skip to: 3972
+/* 3951 */ MCD::OPC_ExtractField, 25, 1, // Inst{25} ...
+/* 3954 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3963
+/* 3959 */ MCD::OPC_Decode, 231, 4, 46, // Opcode: PCADDI
+/* 3963 */ MCD::OPC_FilterValue, 1, 91, 6, 0, // Skip to: 5595
+/* 3968 */ MCD::OPC_Decode, 234, 4, 46, // Opcode: PCALAU12I
+/* 3972 */ MCD::OPC_FilterValue, 7, 26, 0, 0, // Skip to: 4003
+/* 3977 */ MCD::OPC_ExtractField, 25, 1, // Inst{25} ...
+/* 3980 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3989
+/* 3985 */ MCD::OPC_Decode, 232, 4, 46, // Opcode: PCADDU12I
+/* 3989 */ MCD::OPC_FilterValue, 1, 65, 6, 0, // Skip to: 5595
+/* 3994 */ MCD::OPC_CheckPredicate, 0, 60, 6, 0, // Skip to: 5595
+/* 3999 */ MCD::OPC_Decode, 233, 4, 46, // Opcode: PCADDU18I
+/* 4003 */ MCD::OPC_FilterValue, 8, 49, 0, 0, // Skip to: 4057
+/* 4008 */ MCD::OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 4011 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4020
+/* 4016 */ MCD::OPC_Decode, 195, 4, 48, // Opcode: LL_W
+/* 4020 */ MCD::OPC_FilterValue, 1, 4, 0, 0, // Skip to: 4029
+/* 4025 */ MCD::OPC_Decode, 251, 4, 49, // Opcode: SC_W
+/* 4029 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 4043
+/* 4034 */ MCD::OPC_CheckPredicate, 0, 20, 6, 0, // Skip to: 5595
+/* 4039 */ MCD::OPC_Decode, 194, 4, 48, // Opcode: LL_D
+/* 4043 */ MCD::OPC_FilterValue, 3, 11, 6, 0, // Skip to: 5595
+/* 4048 */ MCD::OPC_CheckPredicate, 0, 6, 6, 0, // Skip to: 5595
+/* 4053 */ MCD::OPC_Decode, 250, 4, 49, // Opcode: SC_D
+/* 4057 */ MCD::OPC_FilterValue, 9, 59, 0, 0, // Skip to: 4121
+/* 4062 */ MCD::OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 4065 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4079
+/* 4070 */ MCD::OPC_CheckPredicate, 0, 240, 5, 0, // Skip to: 5595
+/* 4075 */ MCD::OPC_Decode, 179, 4, 48, // Opcode: LDPTR_W
+/* 4079 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4093
+/* 4084 */ MCD::OPC_CheckPredicate, 0, 226, 5, 0, // Skip to: 5595
+/* 4089 */ MCD::OPC_Decode, 149, 5, 48, // Opcode: STPTR_W
+/* 4093 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 4107
+/* 4098 */ MCD::OPC_CheckPredicate, 0, 212, 5, 0, // Skip to: 5595
+/* 4103 */ MCD::OPC_Decode, 178, 4, 48, // Opcode: LDPTR_D
+/* 4107 */ MCD::OPC_FilterValue, 3, 203, 5, 0, // Skip to: 5595
+/* 4112 */ MCD::OPC_CheckPredicate, 0, 198, 5, 0, // Skip to: 5595
+/* 4117 */ MCD::OPC_Decode, 148, 5, 48, // Opcode: STPTR_D
+/* 4121 */ MCD::OPC_FilterValue, 10, 182, 0, 0, // Skip to: 4308
+/* 4126 */ MCD::OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 4129 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4138
+/* 4134 */ MCD::OPC_Decode, 187, 4, 30, // Opcode: LD_B
+/* 4138 */ MCD::OPC_FilterValue, 1, 4, 0, 0, // Skip to: 4147
+/* 4143 */ MCD::OPC_Decode, 190, 4, 30, // Opcode: LD_H
+/* 4147 */ MCD::OPC_FilterValue, 2, 4, 0, 0, // Skip to: 4156
+/* 4152 */ MCD::OPC_Decode, 192, 4, 30, // Opcode: LD_W
+/* 4156 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 4170
+/* 4161 */ MCD::OPC_CheckPredicate, 0, 149, 5, 0, // Skip to: 5595
+/* 4166 */ MCD::OPC_Decode, 189, 4, 30, // Opcode: LD_D
+/* 4170 */ MCD::OPC_FilterValue, 4, 4, 0, 0, // Skip to: 4179
+/* 4175 */ MCD::OPC_Decode, 154, 5, 30, // Opcode: ST_B
+/* 4179 */ MCD::OPC_FilterValue, 5, 4, 0, 0, // Skip to: 4188
+/* 4184 */ MCD::OPC_Decode, 156, 5, 30, // Opcode: ST_H
+/* 4188 */ MCD::OPC_FilterValue, 6, 4, 0, 0, // Skip to: 4197
+/* 4193 */ MCD::OPC_Decode, 157, 5, 30, // Opcode: ST_W
+/* 4197 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 4211
+/* 4202 */ MCD::OPC_CheckPredicate, 0, 108, 5, 0, // Skip to: 5595
+/* 4207 */ MCD::OPC_Decode, 155, 5, 30, // Opcode: ST_D
+/* 4211 */ MCD::OPC_FilterValue, 8, 4, 0, 0, // Skip to: 4220
+/* 4216 */ MCD::OPC_Decode, 188, 4, 30, // Opcode: LD_BU
+/* 4220 */ MCD::OPC_FilterValue, 9, 4, 0, 0, // Skip to: 4229
+/* 4225 */ MCD::OPC_Decode, 191, 4, 30, // Opcode: LD_HU
+/* 4229 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 4243
+/* 4234 */ MCD::OPC_CheckPredicate, 0, 76, 5, 0, // Skip to: 5595
+/* 4239 */ MCD::OPC_Decode, 193, 4, 30, // Opcode: LD_WU
+/* 4243 */ MCD::OPC_FilterValue, 11, 4, 0, 0, // Skip to: 4252
+/* 4248 */ MCD::OPC_Decode, 235, 4, 35, // Opcode: PRELD
+/* 4252 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 4266
+/* 4257 */ MCD::OPC_CheckPredicate, 1, 53, 5, 0, // Skip to: 5595
+/* 4262 */ MCD::OPC_Decode, 217, 3, 50, // Opcode: FLD_S
+/* 4266 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 4280
+/* 4271 */ MCD::OPC_CheckPredicate, 1, 39, 5, 0, // Skip to: 5595
+/* 4276 */ MCD::OPC_Decode, 133, 4, 50, // Opcode: FST_S
+/* 4280 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 4294
+/* 4285 */ MCD::OPC_CheckPredicate, 2, 25, 5, 0, // Skip to: 5595
+/* 4290 */ MCD::OPC_Decode, 216, 3, 51, // Opcode: FLD_D
+/* 4294 */ MCD::OPC_FilterValue, 15, 16, 5, 0, // Skip to: 5595
+/* 4299 */ MCD::OPC_CheckPredicate, 2, 11, 5, 0, // Skip to: 5595
+/* 4304 */ MCD::OPC_Decode, 132, 4, 51, // Opcode: FST_D
+/* 4308 */ MCD::OPC_FilterValue, 14, 123, 4, 0, // Skip to: 5460
+/* 4313 */ MCD::OPC_ExtractField, 15, 11, // Inst{25-15} ...
+/* 4316 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4330
+/* 4321 */ MCD::OPC_CheckPredicate, 0, 245, 4, 0, // Skip to: 5595
+/* 4326 */ MCD::OPC_Decode, 180, 4, 5, // Opcode: LDX_B
+/* 4330 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 4344
+/* 4335 */ MCD::OPC_CheckPredicate, 0, 231, 4, 0, // Skip to: 5595
+/* 4340 */ MCD::OPC_Decode, 183, 4, 5, // Opcode: LDX_H
+/* 4344 */ MCD::OPC_FilterValue, 16, 9, 0, 0, // Skip to: 4358
+/* 4349 */ MCD::OPC_CheckPredicate, 0, 217, 4, 0, // Skip to: 5595
+/* 4354 */ MCD::OPC_Decode, 185, 4, 5, // Opcode: LDX_W
+/* 4358 */ MCD::OPC_FilterValue, 24, 9, 0, 0, // Skip to: 4372
+/* 4363 */ MCD::OPC_CheckPredicate, 0, 203, 4, 0, // Skip to: 5595
+/* 4368 */ MCD::OPC_Decode, 182, 4, 5, // Opcode: LDX_D
+/* 4372 */ MCD::OPC_FilterValue, 32, 9, 0, 0, // Skip to: 4386
+/* 4377 */ MCD::OPC_CheckPredicate, 0, 189, 4, 0, // Skip to: 5595
+/* 4382 */ MCD::OPC_Decode, 150, 5, 5, // Opcode: STX_B
+/* 4386 */ MCD::OPC_FilterValue, 40, 9, 0, 0, // Skip to: 4400
+/* 4391 */ MCD::OPC_CheckPredicate, 0, 175, 4, 0, // Skip to: 5595
+/* 4396 */ MCD::OPC_Decode, 152, 5, 5, // Opcode: STX_H
+/* 4400 */ MCD::OPC_FilterValue, 48, 9, 0, 0, // Skip to: 4414
+/* 4405 */ MCD::OPC_CheckPredicate, 0, 161, 4, 0, // Skip to: 5595
+/* 4410 */ MCD::OPC_Decode, 153, 5, 5, // Opcode: STX_W
+/* 4414 */ MCD::OPC_FilterValue, 56, 9, 0, 0, // Skip to: 4428
+/* 4419 */ MCD::OPC_CheckPredicate, 0, 147, 4, 0, // Skip to: 5595
+/* 4424 */ MCD::OPC_Decode, 151, 5, 5, // Opcode: STX_D
+/* 4428 */ MCD::OPC_FilterValue, 64, 9, 0, 0, // Skip to: 4442
+/* 4433 */ MCD::OPC_CheckPredicate, 0, 133, 4, 0, // Skip to: 5595
+/* 4438 */ MCD::OPC_Decode, 181, 4, 5, // Opcode: LDX_BU
+/* 4442 */ MCD::OPC_FilterValue, 72, 9, 0, 0, // Skip to: 4456
+/* 4447 */ MCD::OPC_CheckPredicate, 0, 119, 4, 0, // Skip to: 5595
+/* 4452 */ MCD::OPC_Decode, 184, 4, 5, // Opcode: LDX_HU
+/* 4456 */ MCD::OPC_FilterValue, 80, 9, 0, 0, // Skip to: 4470
+/* 4461 */ MCD::OPC_CheckPredicate, 0, 105, 4, 0, // Skip to: 5595
+/* 4466 */ MCD::OPC_Decode, 186, 4, 5, // Opcode: LDX_WU
+/* 4470 */ MCD::OPC_FilterValue, 88, 9, 0, 0, // Skip to: 4484
+/* 4475 */ MCD::OPC_CheckPredicate, 0, 91, 4, 0, // Skip to: 5595
+/* 4480 */ MCD::OPC_Decode, 236, 4, 52, // Opcode: PRELDX
+/* 4484 */ MCD::OPC_FilterValue, 96, 9, 0, 0, // Skip to: 4498
+/* 4489 */ MCD::OPC_CheckPredicate, 1, 77, 4, 0, // Skip to: 5595
+/* 4494 */ MCD::OPC_Decode, 215, 3, 53, // Opcode: FLDX_S
+/* 4498 */ MCD::OPC_FilterValue, 104, 9, 0, 0, // Skip to: 4512
+/* 4503 */ MCD::OPC_CheckPredicate, 2, 63, 4, 0, // Skip to: 5595
+/* 4508 */ MCD::OPC_Decode, 214, 3, 54, // Opcode: FLDX_D
+/* 4512 */ MCD::OPC_FilterValue, 112, 9, 0, 0, // Skip to: 4526
+/* 4517 */ MCD::OPC_CheckPredicate, 1, 49, 4, 0, // Skip to: 5595
+/* 4522 */ MCD::OPC_Decode, 131, 4, 53, // Opcode: FSTX_S
+/* 4526 */ MCD::OPC_FilterValue, 120, 9, 0, 0, // Skip to: 4540
+/* 4531 */ MCD::OPC_CheckPredicate, 2, 35, 4, 0, // Skip to: 5595
+/* 4536 */ MCD::OPC_Decode, 130, 4, 54, // Opcode: FSTX_D
+/* 4540 */ MCD::OPC_FilterValue, 192, 1, 9, 0, 0, // Skip to: 4555
+/* 4546 */ MCD::OPC_CheckPredicate, 0, 20, 4, 0, // Skip to: 5595
+/* 4551 */ MCD::OPC_Decode, 215, 2, 55, // Opcode: AMSWAP_W
+/* 4555 */ MCD::OPC_FilterValue, 193, 1, 9, 0, 0, // Skip to: 4570
+/* 4561 */ MCD::OPC_CheckPredicate, 0, 5, 4, 0, // Skip to: 5595
+/* 4566 */ MCD::OPC_Decode, 212, 2, 55, // Opcode: AMSWAP_D
+/* 4570 */ MCD::OPC_FilterValue, 194, 1, 9, 0, 0, // Skip to: 4585
+/* 4576 */ MCD::OPC_CheckPredicate, 0, 246, 3, 0, // Skip to: 5595
+/* 4581 */ MCD::OPC_Decode, 187, 2, 55, // Opcode: AMADD_W
+/* 4585 */ MCD::OPC_FilterValue, 195, 1, 9, 0, 0, // Skip to: 4600
+/* 4591 */ MCD::OPC_CheckPredicate, 0, 231, 3, 0, // Skip to: 5595
+/* 4596 */ MCD::OPC_Decode, 184, 2, 55, // Opcode: AMADD_D
+/* 4600 */ MCD::OPC_FilterValue, 196, 1, 9, 0, 0, // Skip to: 4615
+/* 4606 */ MCD::OPC_CheckPredicate, 0, 216, 3, 0, // Skip to: 5595
+/* 4611 */ MCD::OPC_Decode, 191, 2, 55, // Opcode: AMAND_W
+/* 4615 */ MCD::OPC_FilterValue, 197, 1, 9, 0, 0, // Skip to: 4630
+/* 4621 */ MCD::OPC_CheckPredicate, 0, 201, 3, 0, // Skip to: 5595
+/* 4626 */ MCD::OPC_Decode, 188, 2, 55, // Opcode: AMAND_D
+/* 4630 */ MCD::OPC_FilterValue, 198, 1, 9, 0, 0, // Skip to: 4645
+/* 4636 */ MCD::OPC_CheckPredicate, 0, 186, 3, 0, // Skip to: 5595
+/* 4641 */ MCD::OPC_Decode, 211, 2, 55, // Opcode: AMOR_W
+/* 4645 */ MCD::OPC_FilterValue, 199, 1, 9, 0, 0, // Skip to: 4660
+/* 4651 */ MCD::OPC_CheckPredicate, 0, 171, 3, 0, // Skip to: 5595
+/* 4656 */ MCD::OPC_Decode, 208, 2, 55, // Opcode: AMOR_D
+/* 4660 */ MCD::OPC_FilterValue, 200, 1, 9, 0, 0, // Skip to: 4675
+/* 4666 */ MCD::OPC_CheckPredicate, 0, 156, 3, 0, // Skip to: 5595
+/* 4671 */ MCD::OPC_Decode, 219, 2, 55, // Opcode: AMXOR_W
+/* 4675 */ MCD::OPC_FilterValue, 201, 1, 9, 0, 0, // Skip to: 4690
+/* 4681 */ MCD::OPC_CheckPredicate, 0, 141, 3, 0, // Skip to: 5595
+/* 4686 */ MCD::OPC_Decode, 216, 2, 55, // Opcode: AMXOR_D
+/* 4690 */ MCD::OPC_FilterValue, 202, 1, 9, 0, 0, // Skip to: 4705
+/* 4696 */ MCD::OPC_CheckPredicate, 0, 126, 3, 0, // Skip to: 5595
+/* 4701 */ MCD::OPC_Decode, 198, 2, 55, // Opcode: AMMAX_W
+/* 4705 */ MCD::OPC_FilterValue, 203, 1, 9, 0, 0, // Skip to: 4720
+/* 4711 */ MCD::OPC_CheckPredicate, 0, 111, 3, 0, // Skip to: 5595
+/* 4716 */ MCD::OPC_Decode, 192, 2, 55, // Opcode: AMMAX_D
+/* 4720 */ MCD::OPC_FilterValue, 204, 1, 9, 0, 0, // Skip to: 4735
+/* 4726 */ MCD::OPC_CheckPredicate, 0, 96, 3, 0, // Skip to: 5595
+/* 4731 */ MCD::OPC_Decode, 206, 2, 55, // Opcode: AMMIN_W
+/* 4735 */ MCD::OPC_FilterValue, 205, 1, 9, 0, 0, // Skip to: 4750
+/* 4741 */ MCD::OPC_CheckPredicate, 0, 81, 3, 0, // Skip to: 5595
+/* 4746 */ MCD::OPC_Decode, 200, 2, 55, // Opcode: AMMIN_D
+/* 4750 */ MCD::OPC_FilterValue, 206, 1, 9, 0, 0, // Skip to: 4765
+/* 4756 */ MCD::OPC_CheckPredicate, 0, 66, 3, 0, // Skip to: 5595
+/* 4761 */ MCD::OPC_Decode, 199, 2, 55, // Opcode: AMMAX_WU
+/* 4765 */ MCD::OPC_FilterValue, 207, 1, 9, 0, 0, // Skip to: 4780
+/* 4771 */ MCD::OPC_CheckPredicate, 0, 51, 3, 0, // Skip to: 5595
+/* 4776 */ MCD::OPC_Decode, 197, 2, 55, // Opcode: AMMAX_DU
+/* 4780 */ MCD::OPC_FilterValue, 208, 1, 9, 0, 0, // Skip to: 4795
+/* 4786 */ MCD::OPC_CheckPredicate, 0, 36, 3, 0, // Skip to: 5595
+/* 4791 */ MCD::OPC_Decode, 207, 2, 55, // Opcode: AMMIN_WU
+/* 4795 */ MCD::OPC_FilterValue, 209, 1, 9, 0, 0, // Skip to: 4810
+/* 4801 */ MCD::OPC_CheckPredicate, 0, 21, 3, 0, // Skip to: 5595
+/* 4806 */ MCD::OPC_Decode, 205, 2, 55, // Opcode: AMMIN_DU
+/* 4810 */ MCD::OPC_FilterValue, 210, 1, 9, 0, 0, // Skip to: 4825
+/* 4816 */ MCD::OPC_CheckPredicate, 0, 6, 3, 0, // Skip to: 5595
+/* 4821 */ MCD::OPC_Decode, 214, 2, 55, // Opcode: AMSWAP_DB_W
+/* 4825 */ MCD::OPC_FilterValue, 211, 1, 9, 0, 0, // Skip to: 4840
+/* 4831 */ MCD::OPC_CheckPredicate, 0, 247, 2, 0, // Skip to: 5595
+/* 4836 */ MCD::OPC_Decode, 213, 2, 55, // Opcode: AMSWAP_DB_D
+/* 4840 */ MCD::OPC_FilterValue, 212, 1, 9, 0, 0, // Skip to: 4855
+/* 4846 */ MCD::OPC_CheckPredicate, 0, 232, 2, 0, // Skip to: 5595
+/* 4851 */ MCD::OPC_Decode, 186, 2, 55, // Opcode: AMADD_DB_W
+/* 4855 */ MCD::OPC_FilterValue, 213, 1, 9, 0, 0, // Skip to: 4870
+/* 4861 */ MCD::OPC_CheckPredicate, 0, 217, 2, 0, // Skip to: 5595
+/* 4866 */ MCD::OPC_Decode, 185, 2, 55, // Opcode: AMADD_DB_D
+/* 4870 */ MCD::OPC_FilterValue, 214, 1, 9, 0, 0, // Skip to: 4885
+/* 4876 */ MCD::OPC_CheckPredicate, 0, 202, 2, 0, // Skip to: 5595
+/* 4881 */ MCD::OPC_Decode, 190, 2, 55, // Opcode: AMAND_DB_W
+/* 4885 */ MCD::OPC_FilterValue, 215, 1, 9, 0, 0, // Skip to: 4900
+/* 4891 */ MCD::OPC_CheckPredicate, 0, 187, 2, 0, // Skip to: 5595
+/* 4896 */ MCD::OPC_Decode, 189, 2, 55, // Opcode: AMAND_DB_D
+/* 4900 */ MCD::OPC_FilterValue, 216, 1, 9, 0, 0, // Skip to: 4915
+/* 4906 */ MCD::OPC_CheckPredicate, 0, 172, 2, 0, // Skip to: 5595
+/* 4911 */ MCD::OPC_Decode, 210, 2, 55, // Opcode: AMOR_DB_W
+/* 4915 */ MCD::OPC_FilterValue, 217, 1, 9, 0, 0, // Skip to: 4930
+/* 4921 */ MCD::OPC_CheckPredicate, 0, 157, 2, 0, // Skip to: 5595
+/* 4926 */ MCD::OPC_Decode, 209, 2, 55, // Opcode: AMOR_DB_D
+/* 4930 */ MCD::OPC_FilterValue, 218, 1, 9, 0, 0, // Skip to: 4945
+/* 4936 */ MCD::OPC_CheckPredicate, 0, 142, 2, 0, // Skip to: 5595
+/* 4941 */ MCD::OPC_Decode, 218, 2, 55, // Opcode: AMXOR_DB_W
+/* 4945 */ MCD::OPC_FilterValue, 219, 1, 9, 0, 0, // Skip to: 4960
+/* 4951 */ MCD::OPC_CheckPredicate, 0, 127, 2, 0, // Skip to: 5595
+/* 4956 */ MCD::OPC_Decode, 217, 2, 55, // Opcode: AMXOR_DB_D
+/* 4960 */ MCD::OPC_FilterValue, 220, 1, 9, 0, 0, // Skip to: 4975
+/* 4966 */ MCD::OPC_CheckPredicate, 0, 112, 2, 0, // Skip to: 5595
+/* 4971 */ MCD::OPC_Decode, 195, 2, 55, // Opcode: AMMAX_DB_W
+/* 4975 */ MCD::OPC_FilterValue, 221, 1, 9, 0, 0, // Skip to: 4990
+/* 4981 */ MCD::OPC_CheckPredicate, 0, 97, 2, 0, // Skip to: 5595
+/* 4986 */ MCD::OPC_Decode, 193, 2, 55, // Opcode: AMMAX_DB_D
+/* 4990 */ MCD::OPC_FilterValue, 222, 1, 9, 0, 0, // Skip to: 5005
+/* 4996 */ MCD::OPC_CheckPredicate, 0, 82, 2, 0, // Skip to: 5595
+/* 5001 */ MCD::OPC_Decode, 203, 2, 55, // Opcode: AMMIN_DB_W
+/* 5005 */ MCD::OPC_FilterValue, 223, 1, 9, 0, 0, // Skip to: 5020
+/* 5011 */ MCD::OPC_CheckPredicate, 0, 67, 2, 0, // Skip to: 5595
+/* 5016 */ MCD::OPC_Decode, 201, 2, 55, // Opcode: AMMIN_DB_D
+/* 5020 */ MCD::OPC_FilterValue, 224, 1, 9, 0, 0, // Skip to: 5035
+/* 5026 */ MCD::OPC_CheckPredicate, 0, 52, 2, 0, // Skip to: 5595
+/* 5031 */ MCD::OPC_Decode, 196, 2, 55, // Opcode: AMMAX_DB_WU
+/* 5035 */ MCD::OPC_FilterValue, 225, 1, 9, 0, 0, // Skip to: 5050
+/* 5041 */ MCD::OPC_CheckPredicate, 0, 37, 2, 0, // Skip to: 5595
+/* 5046 */ MCD::OPC_Decode, 194, 2, 55, // Opcode: AMMAX_DB_DU
+/* 5050 */ MCD::OPC_FilterValue, 226, 1, 9, 0, 0, // Skip to: 5065
+/* 5056 */ MCD::OPC_CheckPredicate, 0, 22, 2, 0, // Skip to: 5595
+/* 5061 */ MCD::OPC_Decode, 204, 2, 55, // Opcode: AMMIN_DB_WU
+/* 5065 */ MCD::OPC_FilterValue, 227, 1, 9, 0, 0, // Skip to: 5080
+/* 5071 */ MCD::OPC_CheckPredicate, 0, 7, 2, 0, // Skip to: 5595
+/* 5076 */ MCD::OPC_Decode, 202, 2, 55, // Opcode: AMMIN_DB_DU
+/* 5080 */ MCD::OPC_FilterValue, 228, 1, 4, 0, 0, // Skip to: 5090
+/* 5086 */ MCD::OPC_Decode, 141, 3, 6, // Opcode: DBAR
+/* 5090 */ MCD::OPC_FilterValue, 229, 1, 4, 0, 0, // Skip to: 5100
+/* 5096 */ MCD::OPC_Decode, 156, 4, 6, // Opcode: IBAR
+/* 5100 */ MCD::OPC_FilterValue, 232, 1, 9, 0, 0, // Skip to: 5115
+/* 5106 */ MCD::OPC_CheckPredicate, 1, 228, 1, 0, // Skip to: 5595
+/* 5111 */ MCD::OPC_Decode, 211, 3, 53, // Opcode: FLDGT_S
+/* 5115 */ MCD::OPC_FilterValue, 233, 1, 9, 0, 0, // Skip to: 5130
+/* 5121 */ MCD::OPC_CheckPredicate, 2, 213, 1, 0, // Skip to: 5595
+/* 5126 */ MCD::OPC_Decode, 210, 3, 54, // Opcode: FLDGT_D
+/* 5130 */ MCD::OPC_FilterValue, 234, 1, 9, 0, 0, // Skip to: 5145
+/* 5136 */ MCD::OPC_CheckPredicate, 1, 198, 1, 0, // Skip to: 5595
+/* 5141 */ MCD::OPC_Decode, 213, 3, 53, // Opcode: FLDLE_S
+/* 5145 */ MCD::OPC_FilterValue, 235, 1, 9, 0, 0, // Skip to: 5160
+/* 5151 */ MCD::OPC_CheckPredicate, 2, 183, 1, 0, // Skip to: 5595
+/* 5156 */ MCD::OPC_Decode, 212, 3, 54, // Opcode: FLDLE_D
+/* 5160 */ MCD::OPC_FilterValue, 236, 1, 9, 0, 0, // Skip to: 5175
+/* 5166 */ MCD::OPC_CheckPredicate, 1, 168, 1, 0, // Skip to: 5595
+/* 5171 */ MCD::OPC_Decode, 255, 3, 53, // Opcode: FSTGT_S
+/* 5175 */ MCD::OPC_FilterValue, 237, 1, 9, 0, 0, // Skip to: 5190
+/* 5181 */ MCD::OPC_CheckPredicate, 2, 153, 1, 0, // Skip to: 5595
+/* 5186 */ MCD::OPC_Decode, 254, 3, 54, // Opcode: FSTGT_D
+/* 5190 */ MCD::OPC_FilterValue, 238, 1, 9, 0, 0, // Skip to: 5205
+/* 5196 */ MCD::OPC_CheckPredicate, 1, 138, 1, 0, // Skip to: 5595
+/* 5201 */ MCD::OPC_Decode, 129, 4, 53, // Opcode: FSTLE_S
+/* 5205 */ MCD::OPC_FilterValue, 239, 1, 9, 0, 0, // Skip to: 5220
+/* 5211 */ MCD::OPC_CheckPredicate, 2, 123, 1, 0, // Skip to: 5595
+/* 5216 */ MCD::OPC_Decode, 128, 4, 54, // Opcode: FSTLE_D
+/* 5220 */ MCD::OPC_FilterValue, 240, 1, 9, 0, 0, // Skip to: 5235
+/* 5226 */ MCD::OPC_CheckPredicate, 0, 108, 1, 0, // Skip to: 5595
+/* 5231 */ MCD::OPC_Decode, 169, 4, 5, // Opcode: LDGT_B
+/* 5235 */ MCD::OPC_FilterValue, 241, 1, 9, 0, 0, // Skip to: 5250
+/* 5241 */ MCD::OPC_CheckPredicate, 0, 93, 1, 0, // Skip to: 5595
+/* 5246 */ MCD::OPC_Decode, 171, 4, 5, // Opcode: LDGT_H
+/* 5250 */ MCD::OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 5265
+/* 5256 */ MCD::OPC_CheckPredicate, 0, 78, 1, 0, // Skip to: 5595
+/* 5261 */ MCD::OPC_Decode, 172, 4, 5, // Opcode: LDGT_W
+/* 5265 */ MCD::OPC_FilterValue, 243, 1, 9, 0, 0, // Skip to: 5280
+/* 5271 */ MCD::OPC_CheckPredicate, 0, 63, 1, 0, // Skip to: 5595
+/* 5276 */ MCD::OPC_Decode, 170, 4, 5, // Opcode: LDGT_D
+/* 5280 */ MCD::OPC_FilterValue, 244, 1, 9, 0, 0, // Skip to: 5295
+/* 5286 */ MCD::OPC_CheckPredicate, 0, 48, 1, 0, // Skip to: 5595
+/* 5291 */ MCD::OPC_Decode, 173, 4, 5, // Opcode: LDLE_B
+/* 5295 */ MCD::OPC_FilterValue, 245, 1, 9, 0, 0, // Skip to: 5310
+/* 5301 */ MCD::OPC_CheckPredicate, 0, 33, 1, 0, // Skip to: 5595
+/* 5306 */ MCD::OPC_Decode, 175, 4, 5, // Opcode: LDLE_H
+/* 5310 */ MCD::OPC_FilterValue, 246, 1, 9, 0, 0, // Skip to: 5325
+/* 5316 */ MCD::OPC_CheckPredicate, 0, 18, 1, 0, // Skip to: 5595
+/* 5321 */ MCD::OPC_Decode, 176, 4, 5, // Opcode: LDLE_W
+/* 5325 */ MCD::OPC_FilterValue, 247, 1, 9, 0, 0, // Skip to: 5340
+/* 5331 */ MCD::OPC_CheckPredicate, 0, 3, 1, 0, // Skip to: 5595
+/* 5336 */ MCD::OPC_Decode, 174, 4, 5, // Opcode: LDLE_D
+/* 5340 */ MCD::OPC_FilterValue, 248, 1, 9, 0, 0, // Skip to: 5355
+/* 5346 */ MCD::OPC_CheckPredicate, 0, 244, 0, 0, // Skip to: 5595
+/* 5351 */ MCD::OPC_Decode, 140, 5, 5, // Opcode: STGT_B
+/* 5355 */ MCD::OPC_FilterValue, 249, 1, 9, 0, 0, // Skip to: 5370
+/* 5361 */ MCD::OPC_CheckPredicate, 0, 229, 0, 0, // Skip to: 5595
+/* 5366 */ MCD::OPC_Decode, 142, 5, 5, // Opcode: STGT_H
+/* 5370 */ MCD::OPC_FilterValue, 250, 1, 9, 0, 0, // Skip to: 5385
+/* 5376 */ MCD::OPC_CheckPredicate, 0, 214, 0, 0, // Skip to: 5595
+/* 5381 */ MCD::OPC_Decode, 143, 5, 5, // Opcode: STGT_W
+/* 5385 */ MCD::OPC_FilterValue, 251, 1, 9, 0, 0, // Skip to: 5400
+/* 5391 */ MCD::OPC_CheckPredicate, 0, 199, 0, 0, // Skip to: 5595
+/* 5396 */ MCD::OPC_Decode, 141, 5, 5, // Opcode: STGT_D
+/* 5400 */ MCD::OPC_FilterValue, 252, 1, 9, 0, 0, // Skip to: 5415
+/* 5406 */ MCD::OPC_CheckPredicate, 0, 184, 0, 0, // Skip to: 5595
+/* 5411 */ MCD::OPC_Decode, 144, 5, 5, // Opcode: STLE_B
+/* 5415 */ MCD::OPC_FilterValue, 253, 1, 9, 0, 0, // Skip to: 5430
+/* 5421 */ MCD::OPC_CheckPredicate, 0, 169, 0, 0, // Skip to: 5595
+/* 5426 */ MCD::OPC_Decode, 146, 5, 5, // Opcode: STLE_H
+/* 5430 */ MCD::OPC_FilterValue, 254, 1, 9, 0, 0, // Skip to: 5445
+/* 5436 */ MCD::OPC_CheckPredicate, 0, 154, 0, 0, // Skip to: 5595
+/* 5441 */ MCD::OPC_Decode, 147, 5, 5, // Opcode: STLE_W
+/* 5445 */ MCD::OPC_FilterValue, 255, 1, 144, 0, 0, // Skip to: 5595
+/* 5451 */ MCD::OPC_CheckPredicate, 0, 139, 0, 0, // Skip to: 5595
+/* 5456 */ MCD::OPC_Decode, 145, 5, 5, // Opcode: STLE_D
+/* 5460 */ MCD::OPC_FilterValue, 16, 4, 0, 0, // Skip to: 5469
+/* 5465 */ MCD::OPC_Decode, 229, 2, 56, // Opcode: BEQZ
+/* 5469 */ MCD::OPC_FilterValue, 17, 4, 0, 0, // Skip to: 5478
+/* 5474 */ MCD::OPC_Decode, 240, 2, 56, // Opcode: BNEZ
+/* 5478 */ MCD::OPC_FilterValue, 18, 31, 0, 0, // Skip to: 5514
+/* 5483 */ MCD::OPC_ExtractField, 8, 2, // Inst{9-8} ...
+/* 5486 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5500
+/* 5491 */ MCD::OPC_CheckPredicate, 1, 99, 0, 0, // Skip to: 5595
+/* 5496 */ MCD::OPC_Decode, 226, 2, 57, // Opcode: BCEQZ
+/* 5500 */ MCD::OPC_FilterValue, 1, 90, 0, 0, // Skip to: 5595
+/* 5505 */ MCD::OPC_CheckPredicate, 1, 85, 0, 0, // Skip to: 5595
+/* 5510 */ MCD::OPC_Decode, 227, 2, 57, // Opcode: BCNEZ
+/* 5514 */ MCD::OPC_FilterValue, 19, 4, 0, 0, // Skip to: 5523
+/* 5519 */ MCD::OPC_Decode, 167, 4, 58, // Opcode: JIRL
+/* 5523 */ MCD::OPC_FilterValue, 20, 4, 0, 0, // Skip to: 5532
+/* 5528 */ MCD::OPC_Decode, 225, 2, 59, // Opcode: B
+/* 5532 */ MCD::OPC_FilterValue, 21, 4, 0, 0, // Skip to: 5541
+/* 5537 */ MCD::OPC_Decode, 236, 2, 59, // Opcode: BL
+/* 5541 */ MCD::OPC_FilterValue, 22, 4, 0, 0, // Skip to: 5550
+/* 5546 */ MCD::OPC_Decode, 228, 2, 60, // Opcode: BEQ
+/* 5550 */ MCD::OPC_FilterValue, 23, 4, 0, 0, // Skip to: 5559
+/* 5555 */ MCD::OPC_Decode, 239, 2, 60, // Opcode: BNE
+/* 5559 */ MCD::OPC_FilterValue, 24, 4, 0, 0, // Skip to: 5568
+/* 5564 */ MCD::OPC_Decode, 237, 2, 60, // Opcode: BLT
+/* 5568 */ MCD::OPC_FilterValue, 25, 4, 0, 0, // Skip to: 5577
+/* 5573 */ MCD::OPC_Decode, 230, 2, 60, // Opcode: BGE
+/* 5577 */ MCD::OPC_FilterValue, 26, 4, 0, 0, // Skip to: 5586
+/* 5582 */ MCD::OPC_Decode, 238, 2, 60, // Opcode: BLTU
+/* 5586 */ MCD::OPC_FilterValue, 27, 4, 0, 0, // Skip to: 5595
+/* 5591 */ MCD::OPC_Decode, 231, 2, 60, // Opcode: BGEU
+/* 5595 */ MCD::OPC_Fail,
+ 0
+};
+
+static bool checkDecoderPredicate(unsigned Idx, const FeatureBitset &Bits) {
+ switch (Idx) {
+ default: llvm_unreachable("Invalid index!");
+ case 0:
+ return (Bits[LoongArch::Feature64Bit]);
+ case 1:
+ return (Bits[LoongArch::FeatureBasicF]);
+ case 2:
+ return (Bits[LoongArch::FeatureBasicD]);
+ case 3:
+ return (Bits[LoongArch::FeatureBasicD] && Bits[LoongArch::Feature64Bit]);
+ }
+}
+
+template <typename InsnType>
+static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
+ uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) {
+ DecodeComplete = true;
+ using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>;
+ TmpType tmp;
+ switch (Idx) {
+ default: llvm_unreachable("Invalid index!");
+ case 0:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 1:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 2:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 2);
+ if (!Check(S, decodeUImmOperand<2, 1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 3:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 2);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 4:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 5:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 6:
+ tmp = fieldFromInstruction(insn, 0, 15);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 7:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 8:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 6);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 9:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 10, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 10:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 10, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 11:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 6);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 10, 6);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 12:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 6);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 10, 6);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 13:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 14:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 15:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 16:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 17:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 18:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 19:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 20:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 21:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 22:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFCSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 23:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFCSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 24:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 25:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 26:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 27:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 28:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 29:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 30:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 12);
+ if (!Check(S, decodeSImmOperand<12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 31:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 12);
+ if (!Check(S, decodeUImmOperand<12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 32:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 14);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 33:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 14);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 34:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 14);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 35:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 12);
+ if (!Check(S, decodeSImmOperand<12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 36:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 8);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 37:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 8);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 38:
+ return S;
+ case 39:
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 40:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 41:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 42:
+ tmp = fieldFromInstruction(insn, 0, 3);
+ if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 43:
+ tmp = fieldFromInstruction(insn, 0, 3);
+ if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 44:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 3);
+ if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 45:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 16);
+ if (!Check(S, decodeSImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 46:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 20);
+ if (!Check(S, decodeSImmOperand<20>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 47:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 20);
+ if (!Check(S, decodeSImmOperand<20>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 48:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 14);
+ if (!Check(S, decodeSImmOperand<14, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 49:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 14);
+ if (!Check(S, decodeSImmOperand<14, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 50:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 12);
+ if (!Check(S, decodeSImmOperand<12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 51:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 12);
+ if (!Check(S, decodeSImmOperand<12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 52:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 53:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 54:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 55:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 56:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ insertBits(tmp, fieldFromInstruction(insn, 0, 5), 16, 5);
+ insertBits(tmp, fieldFromInstruction(insn, 10, 16), 0, 16);
+ if (!Check(S, decodeSImmOperand<21, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 57:
+ tmp = fieldFromInstruction(insn, 5, 3);
+ if (!Check(S, DecodeCFRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ insertBits(tmp, fieldFromInstruction(insn, 0, 5), 16, 5);
+ insertBits(tmp, fieldFromInstruction(insn, 10, 16), 0, 16);
+ if (!Check(S, decodeSImmOperand<21, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 58:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 16);
+ if (!Check(S, decodeSImmOperand<16, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 59:
+ tmp = 0x0;
+ insertBits(tmp, fieldFromInstruction(insn, 0, 10), 16, 10);
+ insertBits(tmp, fieldFromInstruction(insn, 10, 16), 0, 16);
+ if (!Check(S, decodeSImmOperand<26, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ case 60:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 10, 16);
+ if (!Check(S, decodeSImmOperand<16, 2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
+ return S;
+ }
+}
+
+template <typename InsnType>
+static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
+ InsnType insn, uint64_t Address,
+ const MCDisassembler *DisAsm,
+ const MCSubtargetInfo &STI) {
+ const FeatureBitset &Bits = STI.getFeatureBits();
+
+ const uint8_t *Ptr = DecodeTable;
+ uint64_t CurFieldValue = 0;
+ DecodeStatus S = MCDisassembler::Success;
+ while (true) {
+ ptrdiff_t Loc = Ptr - DecodeTable;
+ switch (*Ptr) {
+ default:
+ errs() << Loc << ": Unexpected decode table opcode!\n";
+ return MCDisassembler::Fail;
+ case MCD::OPC_ExtractField: {
+ unsigned Start = *++Ptr;
+ unsigned Len = *++Ptr;
+ ++Ptr;
+ CurFieldValue = fieldFromInstruction(insn, Start, Len);
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_ExtractField(" << Start << ", "
+ << Len << "): " << CurFieldValue << "\n");
+ break;
+ }
+ case MCD::OPC_FilterValue: {
+ // Decode the field value.
+ unsigned Len;
+ uint64_t Val = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 24-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ NumToSkip |= (*Ptr++) << 16;
+
+ // Perform the filter operation.
+ if (Val != CurFieldValue)
+ Ptr += NumToSkip;
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_FilterValue(" << Val << ", " << NumToSkip
+ << "): " << ((Val != CurFieldValue) ? "FAIL:" : "PASS:")
+ << " continuing at " << (Ptr - DecodeTable) << "\n");
+
+ break;
+ }
+ case MCD::OPC_CheckField: {
+ unsigned Start = *++Ptr;
+ unsigned Len = *++Ptr;
+ uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
+ // Decode the field value.
+ unsigned PtrLen = 0;
+ uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen);
+ Ptr += PtrLen;
+ // NumToSkip is a plain 24-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ NumToSkip |= (*Ptr++) << 16;
+
+ // If the actual and expected values don't match, skip.
+ if (ExpectedValue != FieldValue)
+ Ptr += NumToSkip;
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", "
+ << Len << ", " << ExpectedValue << ", " << NumToSkip
+ << "): FieldValue = " << FieldValue << ", ExpectedValue = "
+ << ExpectedValue << ": "
+ << ((ExpectedValue == FieldValue) ? "PASS\n" : "FAIL\n"));
+ break;
+ }
+ case MCD::OPC_CheckPredicate: {
+ unsigned Len;
+ // Decode the Predicate Index value.
+ unsigned PIdx = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 24-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ NumToSkip |= (*Ptr++) << 16;
+ // Check the predicate.
+ bool Pred;
+ if (!(Pred = checkDecoderPredicate(PIdx, Bits)))
+ Ptr += NumToSkip;
+ (void)Pred;
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckPredicate(" << PIdx << "): "
+ << (Pred ? "PASS\n" : "FAIL\n"));
+
+ break;
+ }
+ case MCD::OPC_Decode: {
+ unsigned Len;
+ // Decode the Opcode value.
+ unsigned Opc = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ unsigned DecodeIdx = decodeULEB128(Ptr, &Len);
+ Ptr += Len;
+
+ MI.clear();
+ MI.setOpcode(Opc);
+ bool DecodeComplete;
+ S = decodeToMCInst(S, DecodeIdx, insn, MI, Address, DisAsm, DecodeComplete);
+ assert(DecodeComplete);
+
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc
+ << ", using decoder " << DecodeIdx << ": "
+ << (S != MCDisassembler::Fail ? "PASS" : "FAIL") << "\n");
+ return S;
+ }
+ case MCD::OPC_TryDecode: {
+ unsigned Len;
+ // Decode the Opcode value.
+ unsigned Opc = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ unsigned DecodeIdx = decodeULEB128(Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 24-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ NumToSkip |= (*Ptr++) << 16;
+
+ // Perform the decode operation.
+ MCInst TmpMI;
+ TmpMI.setOpcode(Opc);
+ bool DecodeComplete;
+ S = decodeToMCInst(S, DecodeIdx, insn, TmpMI, Address, DisAsm, DecodeComplete);
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_TryDecode: opcode " << Opc
+ << ", using decoder " << DecodeIdx << ": ");
+
+ if (DecodeComplete) {
+ // Decoding complete.
+ LLVM_DEBUG(dbgs() << (S != MCDisassembler::Fail ? "PASS" : "FAIL") << "\n");
+ MI = TmpMI;
+ return S;
+ } else {
+ assert(S == MCDisassembler::Fail);
+ // If the decoding was incomplete, skip.
+ Ptr += NumToSkip;
+ LLVM_DEBUG(dbgs() << "FAIL: continuing at " << (Ptr - DecodeTable) << "\n");
+ // Reset decode status. This also drops a SoftFail status that could be
+ // set before the decode attempt.
+ S = MCDisassembler::Success;
+ }
+ break;
+ }
+ case MCD::OPC_SoftFail: {
+ // Decode the mask values.
+ unsigned Len;
+ uint64_t PositiveMask = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ uint64_t NegativeMask = decodeULEB128(Ptr, &Len);
+ Ptr += Len;
+ bool Fail = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0;
+ if (Fail)
+ S = MCDisassembler::SoftFail;
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_SoftFail: " << (Fail ? "FAIL\n" : "PASS\n"));
+ break;
+ }
+ case MCD::OPC_Fail: {
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_Fail\n");
+ return MCDisassembler::Fail;
+ }
+ }
+ }
+ llvm_unreachable("bogosity detected in disassembler state machine!");
+}
+
+
+} // end namespace llvm
diff --git a/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenInstrInfo.inc b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenInstrInfo.inc
new file mode 100644
index 0000000..8cecf4c
--- /dev/null
+++ b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenInstrInfo.inc
@@ -0,0 +1,5980 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Target Instruction Enum Values and Descriptors *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+#ifdef GET_INSTRINFO_ENUM
+#undef GET_INSTRINFO_ENUM
+namespace llvm {
+
+namespace LoongArch {
+ enum {
+ PHI = 0,
+ INLINEASM = 1,
+ INLINEASM_BR = 2,
+ CFI_INSTRUCTION = 3,
+ EH_LABEL = 4,
+ GC_LABEL = 5,
+ ANNOTATION_LABEL = 6,
+ KILL = 7,
+ EXTRACT_SUBREG = 8,
+ INSERT_SUBREG = 9,
+ IMPLICIT_DEF = 10,
+ SUBREG_TO_REG = 11,
+ COPY_TO_REGCLASS = 12,
+ DBG_VALUE = 13,
+ DBG_VALUE_LIST = 14,
+ DBG_INSTR_REF = 15,
+ DBG_PHI = 16,
+ DBG_LABEL = 17,
+ REG_SEQUENCE = 18,
+ COPY = 19,
+ BUNDLE = 20,
+ LIFETIME_START = 21,
+ LIFETIME_END = 22,
+ PSEUDO_PROBE = 23,
+ ARITH_FENCE = 24,
+ STACKMAP = 25,
+ FENTRY_CALL = 26,
+ PATCHPOINT = 27,
+ LOAD_STACK_GUARD = 28,
+ PREALLOCATED_SETUP = 29,
+ PREALLOCATED_ARG = 30,
+ STATEPOINT = 31,
+ LOCAL_ESCAPE = 32,
+ FAULTING_OP = 33,
+ PATCHABLE_OP = 34,
+ PATCHABLE_FUNCTION_ENTER = 35,
+ PATCHABLE_RET = 36,
+ PATCHABLE_FUNCTION_EXIT = 37,
+ PATCHABLE_TAIL_CALL = 38,
+ PATCHABLE_EVENT_CALL = 39,
+ PATCHABLE_TYPED_EVENT_CALL = 40,
+ ICALL_BRANCH_FUNNEL = 41,
+ MEMBARRIER = 42,
+ G_ASSERT_SEXT = 43,
+ G_ASSERT_ZEXT = 44,
+ G_ASSERT_ALIGN = 45,
+ G_ADD = 46,
+ G_SUB = 47,
+ G_MUL = 48,
+ G_SDIV = 49,
+ G_UDIV = 50,
+ G_SREM = 51,
+ G_UREM = 52,
+ G_SDIVREM = 53,
+ G_UDIVREM = 54,
+ G_AND = 55,
+ G_OR = 56,
+ G_XOR = 57,
+ G_IMPLICIT_DEF = 58,
+ G_PHI = 59,
+ G_FRAME_INDEX = 60,
+ G_GLOBAL_VALUE = 61,
+ G_EXTRACT = 62,
+ G_UNMERGE_VALUES = 63,
+ G_INSERT = 64,
+ G_MERGE_VALUES = 65,
+ G_BUILD_VECTOR = 66,
+ G_BUILD_VECTOR_TRUNC = 67,
+ G_CONCAT_VECTORS = 68,
+ G_PTRTOINT = 69,
+ G_INTTOPTR = 70,
+ G_BITCAST = 71,
+ G_FREEZE = 72,
+ G_INTRINSIC_FPTRUNC_ROUND = 73,
+ G_INTRINSIC_TRUNC = 74,
+ G_INTRINSIC_ROUND = 75,
+ G_INTRINSIC_LRINT = 76,
+ G_INTRINSIC_ROUNDEVEN = 77,
+ G_READCYCLECOUNTER = 78,
+ G_LOAD = 79,
+ G_SEXTLOAD = 80,
+ G_ZEXTLOAD = 81,
+ G_INDEXED_LOAD = 82,
+ G_INDEXED_SEXTLOAD = 83,
+ G_INDEXED_ZEXTLOAD = 84,
+ G_STORE = 85,
+ G_INDEXED_STORE = 86,
+ G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87,
+ G_ATOMIC_CMPXCHG = 88,
+ G_ATOMICRMW_XCHG = 89,
+ G_ATOMICRMW_ADD = 90,
+ G_ATOMICRMW_SUB = 91,
+ G_ATOMICRMW_AND = 92,
+ G_ATOMICRMW_NAND = 93,
+ G_ATOMICRMW_OR = 94,
+ G_ATOMICRMW_XOR = 95,
+ G_ATOMICRMW_MAX = 96,
+ G_ATOMICRMW_MIN = 97,
+ G_ATOMICRMW_UMAX = 98,
+ G_ATOMICRMW_UMIN = 99,
+ G_ATOMICRMW_FADD = 100,
+ G_ATOMICRMW_FSUB = 101,
+ G_ATOMICRMW_FMAX = 102,
+ G_ATOMICRMW_FMIN = 103,
+ G_ATOMICRMW_UINC_WRAP = 104,
+ G_ATOMICRMW_UDEC_WRAP = 105,
+ G_FENCE = 106,
+ G_BRCOND = 107,
+ G_BRINDIRECT = 108,
+ G_INVOKE_REGION_START = 109,
+ G_INTRINSIC = 110,
+ G_INTRINSIC_W_SIDE_EFFECTS = 111,
+ G_ANYEXT = 112,
+ G_TRUNC = 113,
+ G_CONSTANT = 114,
+ G_FCONSTANT = 115,
+ G_VASTART = 116,
+ G_VAARG = 117,
+ G_SEXT = 118,
+ G_SEXT_INREG = 119,
+ G_ZEXT = 120,
+ G_SHL = 121,
+ G_LSHR = 122,
+ G_ASHR = 123,
+ G_FSHL = 124,
+ G_FSHR = 125,
+ G_ROTR = 126,
+ G_ROTL = 127,
+ G_ICMP = 128,
+ G_FCMP = 129,
+ G_SELECT = 130,
+ G_UADDO = 131,
+ G_UADDE = 132,
+ G_USUBO = 133,
+ G_USUBE = 134,
+ G_SADDO = 135,
+ G_SADDE = 136,
+ G_SSUBO = 137,
+ G_SSUBE = 138,
+ G_UMULO = 139,
+ G_SMULO = 140,
+ G_UMULH = 141,
+ G_SMULH = 142,
+ G_UADDSAT = 143,
+ G_SADDSAT = 144,
+ G_USUBSAT = 145,
+ G_SSUBSAT = 146,
+ G_USHLSAT = 147,
+ G_SSHLSAT = 148,
+ G_SMULFIX = 149,
+ G_UMULFIX = 150,
+ G_SMULFIXSAT = 151,
+ G_UMULFIXSAT = 152,
+ G_SDIVFIX = 153,
+ G_UDIVFIX = 154,
+ G_SDIVFIXSAT = 155,
+ G_UDIVFIXSAT = 156,
+ G_FADD = 157,
+ G_FSUB = 158,
+ G_FMUL = 159,
+ G_FMA = 160,
+ G_FMAD = 161,
+ G_FDIV = 162,
+ G_FREM = 163,
+ G_FPOW = 164,
+ G_FPOWI = 165,
+ G_FEXP = 166,
+ G_FEXP2 = 167,
+ G_FLOG = 168,
+ G_FLOG2 = 169,
+ G_FLOG10 = 170,
+ G_FNEG = 171,
+ G_FPEXT = 172,
+ G_FPTRUNC = 173,
+ G_FPTOSI = 174,
+ G_FPTOUI = 175,
+ G_SITOFP = 176,
+ G_UITOFP = 177,
+ G_FABS = 178,
+ G_FCOPYSIGN = 179,
+ G_IS_FPCLASS = 180,
+ G_FCANONICALIZE = 181,
+ G_FMINNUM = 182,
+ G_FMAXNUM = 183,
+ G_FMINNUM_IEEE = 184,
+ G_FMAXNUM_IEEE = 185,
+ G_FMINIMUM = 186,
+ G_FMAXIMUM = 187,
+ G_PTR_ADD = 188,
+ G_PTRMASK = 189,
+ G_SMIN = 190,
+ G_SMAX = 191,
+ G_UMIN = 192,
+ G_UMAX = 193,
+ G_ABS = 194,
+ G_LROUND = 195,
+ G_LLROUND = 196,
+ G_BR = 197,
+ G_BRJT = 198,
+ G_INSERT_VECTOR_ELT = 199,
+ G_EXTRACT_VECTOR_ELT = 200,
+ G_SHUFFLE_VECTOR = 201,
+ G_CTTZ = 202,
+ G_CTTZ_ZERO_UNDEF = 203,
+ G_CTLZ = 204,
+ G_CTLZ_ZERO_UNDEF = 205,
+ G_CTPOP = 206,
+ G_BSWAP = 207,
+ G_BITREVERSE = 208,
+ G_FCEIL = 209,
+ G_FCOS = 210,
+ G_FSIN = 211,
+ G_FSQRT = 212,
+ G_FFLOOR = 213,
+ G_FRINT = 214,
+ G_FNEARBYINT = 215,
+ G_ADDRSPACE_CAST = 216,
+ G_BLOCK_ADDR = 217,
+ G_JUMP_TABLE = 218,
+ G_DYN_STACKALLOC = 219,
+ G_STRICT_FADD = 220,
+ G_STRICT_FSUB = 221,
+ G_STRICT_FMUL = 222,
+ G_STRICT_FDIV = 223,
+ G_STRICT_FREM = 224,
+ G_STRICT_FMA = 225,
+ G_STRICT_FSQRT = 226,
+ G_READ_REGISTER = 227,
+ G_WRITE_REGISTER = 228,
+ G_MEMCPY = 229,
+ G_MEMCPY_INLINE = 230,
+ G_MEMMOVE = 231,
+ G_MEMSET = 232,
+ G_BZERO = 233,
+ G_VECREDUCE_SEQ_FADD = 234,
+ G_VECREDUCE_SEQ_FMUL = 235,
+ G_VECREDUCE_FADD = 236,
+ G_VECREDUCE_FMUL = 237,
+ G_VECREDUCE_FMAX = 238,
+ G_VECREDUCE_FMIN = 239,
+ G_VECREDUCE_ADD = 240,
+ G_VECREDUCE_MUL = 241,
+ G_VECREDUCE_AND = 242,
+ G_VECREDUCE_OR = 243,
+ G_VECREDUCE_XOR = 244,
+ G_VECREDUCE_SMAX = 245,
+ G_VECREDUCE_SMIN = 246,
+ G_VECREDUCE_UMAX = 247,
+ G_VECREDUCE_UMIN = 248,
+ G_SBFX = 249,
+ G_UBFX = 250,
+ ADJCALLSTACKDOWN = 251,
+ ADJCALLSTACKUP = 252,
+ PseudoAtomicLoadAdd32 = 253,
+ PseudoAtomicLoadAnd32 = 254,
+ PseudoAtomicLoadNand32 = 255,
+ PseudoAtomicLoadNand64 = 256,
+ PseudoAtomicLoadOr32 = 257,
+ PseudoAtomicLoadSub32 = 258,
+ PseudoAtomicLoadXor32 = 259,
+ PseudoAtomicStoreD = 260,
+ PseudoAtomicStoreW = 261,
+ PseudoAtomicSwap32 = 262,
+ PseudoBR = 263,
+ PseudoBRIND = 264,
+ PseudoB_TAIL = 265,
+ PseudoCALL = 266,
+ PseudoCALLIndirect = 267,
+ PseudoCmpXchg32 = 268,
+ PseudoCmpXchg64 = 269,
+ PseudoJIRL_CALL = 270,
+ PseudoJIRL_TAIL = 271,
+ PseudoLA_ABS = 272,
+ PseudoLA_ABS_LARGE = 273,
+ PseudoLA_GOT = 274,
+ PseudoLA_GOT_LARGE = 275,
+ PseudoLA_PCREL = 276,
+ PseudoLA_PCREL_LARGE = 277,
+ PseudoLA_TLS_GD = 278,
+ PseudoLA_TLS_GD_LARGE = 279,
+ PseudoLA_TLS_IE = 280,
+ PseudoLA_TLS_IE_LARGE = 281,
+ PseudoLA_TLS_LD = 282,
+ PseudoLA_TLS_LD_LARGE = 283,
+ PseudoLA_TLS_LE = 284,
+ PseudoLD_CFR = 285,
+ PseudoLI_D = 286,
+ PseudoLI_W = 287,
+ PseudoMaskedAtomicLoadAdd32 = 288,
+ PseudoMaskedAtomicLoadMax32 = 289,
+ PseudoMaskedAtomicLoadMin32 = 290,
+ PseudoMaskedAtomicLoadNand32 = 291,
+ PseudoMaskedAtomicLoadSub32 = 292,
+ PseudoMaskedAtomicLoadUMax32 = 293,
+ PseudoMaskedAtomicLoadUMin32 = 294,
+ PseudoMaskedAtomicSwap32 = 295,
+ PseudoMaskedCmpXchg32 = 296,
+ PseudoRET = 297,
+ PseudoST_CFR = 298,
+ PseudoTAIL = 299,
+ PseudoTAILIndirect = 300,
+ PseudoUNIMP = 301,
+ RDFCSR = 302,
+ WRFCSR = 303,
+ ADDI_D = 304,
+ ADDI_W = 305,
+ ADDU16I_D = 306,
+ ADD_D = 307,
+ ADD_W = 308,
+ ALSL_D = 309,
+ ALSL_W = 310,
+ ALSL_WU = 311,
+ AMADD_D = 312,
+ AMADD_DB_D = 313,
+ AMADD_DB_W = 314,
+ AMADD_W = 315,
+ AMAND_D = 316,
+ AMAND_DB_D = 317,
+ AMAND_DB_W = 318,
+ AMAND_W = 319,
+ AMMAX_D = 320,
+ AMMAX_DB_D = 321,
+ AMMAX_DB_DU = 322,
+ AMMAX_DB_W = 323,
+ AMMAX_DB_WU = 324,
+ AMMAX_DU = 325,
+ AMMAX_W = 326,
+ AMMAX_WU = 327,
+ AMMIN_D = 328,
+ AMMIN_DB_D = 329,
+ AMMIN_DB_DU = 330,
+ AMMIN_DB_W = 331,
+ AMMIN_DB_WU = 332,
+ AMMIN_DU = 333,
+ AMMIN_W = 334,
+ AMMIN_WU = 335,
+ AMOR_D = 336,
+ AMOR_DB_D = 337,
+ AMOR_DB_W = 338,
+ AMOR_W = 339,
+ AMSWAP_D = 340,
+ AMSWAP_DB_D = 341,
+ AMSWAP_DB_W = 342,
+ AMSWAP_W = 343,
+ AMXOR_D = 344,
+ AMXOR_DB_D = 345,
+ AMXOR_DB_W = 346,
+ AMXOR_W = 347,
+ AND = 348,
+ ANDI = 349,
+ ANDN = 350,
+ ASRTGT_D = 351,
+ ASRTLE_D = 352,
+ B = 353,
+ BCEQZ = 354,
+ BCNEZ = 355,
+ BEQ = 356,
+ BEQZ = 357,
+ BGE = 358,
+ BGEU = 359,
+ BITREV_4B = 360,
+ BITREV_8B = 361,
+ BITREV_D = 362,
+ BITREV_W = 363,
+ BL = 364,
+ BLT = 365,
+ BLTU = 366,
+ BNE = 367,
+ BNEZ = 368,
+ BREAK = 369,
+ BSTRINS_D = 370,
+ BSTRINS_W = 371,
+ BSTRPICK_D = 372,
+ BSTRPICK_W = 373,
+ BYTEPICK_D = 374,
+ BYTEPICK_W = 375,
+ CACOP = 376,
+ CLO_D = 377,
+ CLO_W = 378,
+ CLZ_D = 379,
+ CLZ_W = 380,
+ CPUCFG = 381,
+ CRCC_W_B_W = 382,
+ CRCC_W_D_W = 383,
+ CRCC_W_H_W = 384,
+ CRCC_W_W_W = 385,
+ CRC_W_B_W = 386,
+ CRC_W_D_W = 387,
+ CRC_W_H_W = 388,
+ CRC_W_W_W = 389,
+ CSRRD = 390,
+ CSRWR = 391,
+ CSRXCHG = 392,
+ CTO_D = 393,
+ CTO_W = 394,
+ CTZ_D = 395,
+ CTZ_W = 396,
+ DBAR = 397,
+ DBCL = 398,
+ DIV_D = 399,
+ DIV_DU = 400,
+ DIV_W = 401,
+ DIV_WU = 402,
+ ERTN = 403,
+ EXT_W_B = 404,
+ EXT_W_H = 405,
+ FABS_D = 406,
+ FABS_S = 407,
+ FADD_D = 408,
+ FADD_S = 409,
+ FCLASS_D = 410,
+ FCLASS_S = 411,
+ FCMP_CAF_D = 412,
+ FCMP_CAF_S = 413,
+ FCMP_CEQ_D = 414,
+ FCMP_CEQ_S = 415,
+ FCMP_CLE_D = 416,
+ FCMP_CLE_S = 417,
+ FCMP_CLT_D = 418,
+ FCMP_CLT_S = 419,
+ FCMP_CNE_D = 420,
+ FCMP_CNE_S = 421,
+ FCMP_COR_D = 422,
+ FCMP_COR_S = 423,
+ FCMP_CUEQ_D = 424,
+ FCMP_CUEQ_S = 425,
+ FCMP_CULE_D = 426,
+ FCMP_CULE_S = 427,
+ FCMP_CULT_D = 428,
+ FCMP_CULT_S = 429,
+ FCMP_CUNE_D = 430,
+ FCMP_CUNE_S = 431,
+ FCMP_CUN_D = 432,
+ FCMP_CUN_S = 433,
+ FCMP_SAF_D = 434,
+ FCMP_SAF_S = 435,
+ FCMP_SEQ_D = 436,
+ FCMP_SEQ_S = 437,
+ FCMP_SLE_D = 438,
+ FCMP_SLE_S = 439,
+ FCMP_SLT_D = 440,
+ FCMP_SLT_S = 441,
+ FCMP_SNE_D = 442,
+ FCMP_SNE_S = 443,
+ FCMP_SOR_D = 444,
+ FCMP_SOR_S = 445,
+ FCMP_SUEQ_D = 446,
+ FCMP_SUEQ_S = 447,
+ FCMP_SULE_D = 448,
+ FCMP_SULE_S = 449,
+ FCMP_SULT_D = 450,
+ FCMP_SULT_S = 451,
+ FCMP_SUNE_D = 452,
+ FCMP_SUNE_S = 453,
+ FCMP_SUN_D = 454,
+ FCMP_SUN_S = 455,
+ FCOPYSIGN_D = 456,
+ FCOPYSIGN_S = 457,
+ FCVT_D_S = 458,
+ FCVT_S_D = 459,
+ FDIV_D = 460,
+ FDIV_S = 461,
+ FFINT_D_L = 462,
+ FFINT_D_W = 463,
+ FFINT_S_L = 464,
+ FFINT_S_W = 465,
+ FLDGT_D = 466,
+ FLDGT_S = 467,
+ FLDLE_D = 468,
+ FLDLE_S = 469,
+ FLDX_D = 470,
+ FLDX_S = 471,
+ FLD_D = 472,
+ FLD_S = 473,
+ FLOGB_D = 474,
+ FLOGB_S = 475,
+ FMADD_D = 476,
+ FMADD_S = 477,
+ FMAXA_D = 478,
+ FMAXA_S = 479,
+ FMAX_D = 480,
+ FMAX_S = 481,
+ FMINA_D = 482,
+ FMINA_S = 483,
+ FMIN_D = 484,
+ FMIN_S = 485,
+ FMOV_D = 486,
+ FMOV_S = 487,
+ FMSUB_D = 488,
+ FMSUB_S = 489,
+ FMUL_D = 490,
+ FMUL_S = 491,
+ FNEG_D = 492,
+ FNEG_S = 493,
+ FNMADD_D = 494,
+ FNMADD_S = 495,
+ FNMSUB_D = 496,
+ FNMSUB_S = 497,
+ FRECIP_D = 498,
+ FRECIP_S = 499,
+ FRINT_D = 500,
+ FRINT_S = 501,
+ FRSQRT_D = 502,
+ FRSQRT_S = 503,
+ FSCALEB_D = 504,
+ FSCALEB_S = 505,
+ FSEL_D = 506,
+ FSEL_S = 507,
+ FSQRT_D = 508,
+ FSQRT_S = 509,
+ FSTGT_D = 510,
+ FSTGT_S = 511,
+ FSTLE_D = 512,
+ FSTLE_S = 513,
+ FSTX_D = 514,
+ FSTX_S = 515,
+ FST_D = 516,
+ FST_S = 517,
+ FSUB_D = 518,
+ FSUB_S = 519,
+ FTINTRM_L_D = 520,
+ FTINTRM_L_S = 521,
+ FTINTRM_W_D = 522,
+ FTINTRM_W_S = 523,
+ FTINTRNE_L_D = 524,
+ FTINTRNE_L_S = 525,
+ FTINTRNE_W_D = 526,
+ FTINTRNE_W_S = 527,
+ FTINTRP_L_D = 528,
+ FTINTRP_L_S = 529,
+ FTINTRP_W_D = 530,
+ FTINTRP_W_S = 531,
+ FTINTRZ_L_D = 532,
+ FTINTRZ_L_S = 533,
+ FTINTRZ_W_D = 534,
+ FTINTRZ_W_S = 535,
+ FTINT_L_D = 536,
+ FTINT_L_S = 537,
+ FTINT_W_D = 538,
+ FTINT_W_S = 539,
+ IBAR = 540,
+ IDLE = 541,
+ INVTLB = 542,
+ IOCSRRD_B = 543,
+ IOCSRRD_D = 544,
+ IOCSRRD_H = 545,
+ IOCSRRD_W = 546,
+ IOCSRWR_B = 547,
+ IOCSRWR_D = 548,
+ IOCSRWR_H = 549,
+ IOCSRWR_W = 550,
+ JIRL = 551,
+ LDDIR = 552,
+ LDGT_B = 553,
+ LDGT_D = 554,
+ LDGT_H = 555,
+ LDGT_W = 556,
+ LDLE_B = 557,
+ LDLE_D = 558,
+ LDLE_H = 559,
+ LDLE_W = 560,
+ LDPTE = 561,
+ LDPTR_D = 562,
+ LDPTR_W = 563,
+ LDX_B = 564,
+ LDX_BU = 565,
+ LDX_D = 566,
+ LDX_H = 567,
+ LDX_HU = 568,
+ LDX_W = 569,
+ LDX_WU = 570,
+ LD_B = 571,
+ LD_BU = 572,
+ LD_D = 573,
+ LD_H = 574,
+ LD_HU = 575,
+ LD_W = 576,
+ LD_WU = 577,
+ LL_D = 578,
+ LL_W = 579,
+ LU12I_W = 580,
+ LU32I_D = 581,
+ LU52I_D = 582,
+ MASKEQZ = 583,
+ MASKNEZ = 584,
+ MOD_D = 585,
+ MOD_DU = 586,
+ MOD_W = 587,
+ MOD_WU = 588,
+ MOVCF2FR_S = 589,
+ MOVCF2GR = 590,
+ MOVFCSR2GR = 591,
+ MOVFR2CF_S = 592,
+ MOVFR2GR_D = 593,
+ MOVFR2GR_S = 594,
+ MOVFR2GR_S_64 = 595,
+ MOVFRH2GR_S = 596,
+ MOVGR2CF = 597,
+ MOVGR2FCSR = 598,
+ MOVGR2FRH_W = 599,
+ MOVGR2FR_D = 600,
+ MOVGR2FR_W = 601,
+ MOVGR2FR_W_64 = 602,
+ MULH_D = 603,
+ MULH_DU = 604,
+ MULH_W = 605,
+ MULH_WU = 606,
+ MULW_D_W = 607,
+ MULW_D_WU = 608,
+ MUL_D = 609,
+ MUL_W = 610,
+ NOR = 611,
+ OR = 612,
+ ORI = 613,
+ ORN = 614,
+ PCADDI = 615,
+ PCADDU12I = 616,
+ PCADDU18I = 617,
+ PCALAU12I = 618,
+ PRELD = 619,
+ PRELDX = 620,
+ RDTIMEH_W = 621,
+ RDTIMEL_W = 622,
+ RDTIME_D = 623,
+ REVB_2H = 624,
+ REVB_2W = 625,
+ REVB_4H = 626,
+ REVB_D = 627,
+ REVH_2W = 628,
+ REVH_D = 629,
+ ROTRI_D = 630,
+ ROTRI_W = 631,
+ ROTR_D = 632,
+ ROTR_W = 633,
+ SC_D = 634,
+ SC_W = 635,
+ SLLI_D = 636,
+ SLLI_W = 637,
+ SLL_D = 638,
+ SLL_W = 639,
+ SLT = 640,
+ SLTI = 641,
+ SLTU = 642,
+ SLTUI = 643,
+ SRAI_D = 644,
+ SRAI_W = 645,
+ SRA_D = 646,
+ SRA_W = 647,
+ SRLI_D = 648,
+ SRLI_W = 649,
+ SRL_D = 650,
+ SRL_W = 651,
+ STGT_B = 652,
+ STGT_D = 653,
+ STGT_H = 654,
+ STGT_W = 655,
+ STLE_B = 656,
+ STLE_D = 657,
+ STLE_H = 658,
+ STLE_W = 659,
+ STPTR_D = 660,
+ STPTR_W = 661,
+ STX_B = 662,
+ STX_D = 663,
+ STX_H = 664,
+ STX_W = 665,
+ ST_B = 666,
+ ST_D = 667,
+ ST_H = 668,
+ ST_W = 669,
+ SUB_D = 670,
+ SUB_W = 671,
+ SYSCALL = 672,
+ TLBCLR = 673,
+ TLBFILL = 674,
+ TLBFLUSH = 675,
+ TLBRD = 676,
+ TLBSRCH = 677,
+ TLBWR = 678,
+ XOR = 679,
+ XORI = 680,
+ INSTRUCTION_LIST_END = 681
+ };
+
+} // end namespace LoongArch
+} // end namespace llvm
+#endif // GET_INSTRINFO_ENUM
+
+#ifdef GET_INSTRINFO_SCHED_ENUM
+#undef GET_INSTRINFO_SCHED_ENUM
+namespace llvm {
+
+namespace LoongArch {
+namespace Sched {
+ enum {
+ NoInstrModel = 0,
+ SCHED_LIST_END = 1
+ };
+} // end namespace Sched
+} // end namespace LoongArch
+} // end namespace llvm
+#endif // GET_INSTRINFO_SCHED_ENUM
+
+#ifdef GET_INSTRINFO_MC_DESC
+#undef GET_INSTRINFO_MC_DESC
+namespace llvm {
+
+static const MCPhysReg ImplicitList1[] = { LoongArch::R3, LoongArch::R3 };
+static const MCPhysReg ImplicitList2[] = { LoongArch::R3 };
+static const MCPhysReg ImplicitList3[] = { LoongArch::R1 };
+
+static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo10[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo11[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo13[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo14[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo15[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo38[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
+static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
+static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo44[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo45[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo46[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo47[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo48[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo49[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo50[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo51[] = { { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo52[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo53[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo54[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo55[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo56[] = { { LoongArch::GPRTRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo57[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo58[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo59[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo60[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo61[] = { { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo62[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo63[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo64[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo65[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo66[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo67[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo68[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo69[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo70[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo71[] = { { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo72[] = { { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo73[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo74[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo75[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo76[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo77[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo78[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo79[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo80[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo81[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo82[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo83[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo84[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo85[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo86[] = { { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo87[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo88[] = { { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo89[] = { { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo90[] = { { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo91[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo92[] = { { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo93[] = { { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo94[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+
+extern const MCInstrDesc LoongArchInsts[] = {
+ { 680, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #680 = XORI
+ { 679, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #679 = XOR
+ { 678, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #678 = TLBWR
+ { 677, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #677 = TLBSRCH
+ { 676, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #676 = TLBRD
+ { 675, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #675 = TLBFLUSH
+ { 674, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #674 = TLBFILL
+ { 673, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #673 = TLBCLR
+ { 672, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #672 = SYSCALL
+ { 671, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #671 = SUB_W
+ { 670, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #670 = SUB_D
+ { 669, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo50 }, // Inst #669 = ST_W
+ { 668, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo50 }, // Inst #668 = ST_H
+ { 667, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo50 }, // Inst #667 = ST_D
+ { 666, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo50 }, // Inst #666 = ST_B
+ { 665, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo46 }, // Inst #665 = STX_W
+ { 664, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo46 }, // Inst #664 = STX_H
+ { 663, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo46 }, // Inst #663 = STX_D
+ { 662, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo46 }, // Inst #662 = STX_B
+ { 661, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo50 }, // Inst #661 = STPTR_W
+ { 660, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo50 }, // Inst #660 = STPTR_D
+ { 659, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #659 = STLE_W
+ { 658, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #658 = STLE_H
+ { 657, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #657 = STLE_D
+ { 656, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #656 = STLE_B
+ { 655, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #655 = STGT_W
+ { 654, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #654 = STGT_H
+ { 653, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #653 = STGT_D
+ { 652, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #652 = STGT_B
+ { 651, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #651 = SRL_W
+ { 650, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #650 = SRL_D
+ { 649, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #649 = SRLI_W
+ { 648, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #648 = SRLI_D
+ { 647, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #647 = SRA_W
+ { 646, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #646 = SRA_D
+ { 645, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #645 = SRAI_W
+ { 644, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #644 = SRAI_D
+ { 643, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #643 = SLTUI
+ { 642, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #642 = SLTU
+ { 641, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #641 = SLTI
+ { 640, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #640 = SLT
+ { 639, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #639 = SLL_W
+ { 638, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #638 = SLL_D
+ { 637, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #637 = SLLI_W
+ { 636, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #636 = SLLI_D
+ { 635, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo66 }, // Inst #635 = SC_W
+ { 634, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo66 }, // Inst #634 = SC_D
+ { 633, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #633 = ROTR_W
+ { 632, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #632 = ROTR_D
+ { 631, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #631 = ROTRI_W
+ { 630, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #630 = ROTRI_D
+ { 629, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #629 = REVH_D
+ { 628, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #628 = REVH_2W
+ { 627, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #627 = REVB_D
+ { 626, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #626 = REVB_4H
+ { 625, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #625 = REVB_2W
+ { 624, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #624 = REVB_2H
+ { 623, 2, 2, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #623 = RDTIME_D
+ { 622, 2, 2, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #622 = RDTIMEL_W
+ { 621, 2, 2, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #621 = RDTIMEH_W
+ { 620, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo94 }, // Inst #620 = PRELDX
+ { 619, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo64 }, // Inst #619 = PRELD
+ { 618, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #618 = PCALAU12I
+ { 617, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #617 = PCADDU18I
+ { 616, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #616 = PCADDU12I
+ { 615, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #615 = PCADDI
+ { 614, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #614 = ORN
+ { 613, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #613 = ORI
+ { 612, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #612 = OR
+ { 611, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #611 = NOR
+ { 610, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #610 = MUL_W
+ { 609, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #609 = MUL_D
+ { 608, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #608 = MULW_D_WU
+ { 607, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #607 = MULW_D_W
+ { 606, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #606 = MULH_WU
+ { 605, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #605 = MULH_W
+ { 604, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #604 = MULH_DU
+ { 603, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #603 = MULH_D
+ { 602, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo92 }, // Inst #602 = MOVGR2FR_W_64
+ { 601, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo93 }, // Inst #601 = MOVGR2FR_W
+ { 600, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo92 }, // Inst #600 = MOVGR2FR_D
+ { 599, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo91 }, // Inst #599 = MOVGR2FRH_W
+ { 598, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo90 }, // Inst #598 = MOVGR2FCSR
+ { 597, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo89 }, // Inst #597 = MOVGR2CF
+ { 596, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo87 }, // Inst #596 = MOVFRH2GR_S
+ { 595, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo87 }, // Inst #595 = MOVFR2GR_S_64
+ { 594, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo88 }, // Inst #594 = MOVFR2GR_S
+ { 593, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo87 }, // Inst #593 = MOVFR2GR_D
+ { 592, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo86 }, // Inst #592 = MOVFR2CF_S
+ { 591, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo85 }, // Inst #591 = MOVFCSR2GR
+ { 590, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo84 }, // Inst #590 = MOVCF2GR
+ { 589, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo83 }, // Inst #589 = MOVCF2FR_S
+ { 588, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #588 = MOD_WU
+ { 587, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #587 = MOD_W
+ { 586, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #586 = MOD_DU
+ { 585, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #585 = MOD_D
+ { 584, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #584 = MASKNEZ
+ { 583, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #583 = MASKEQZ
+ { 582, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #582 = LU52I_D
+ { 581, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo65 }, // Inst #581 = LU32I_D
+ { 580, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #580 = LU12I_W
+ { 579, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #579 = LL_W
+ { 578, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #578 = LL_D
+ { 577, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #577 = LD_WU
+ { 576, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #576 = LD_W
+ { 575, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #575 = LD_HU
+ { 574, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #574 = LD_H
+ { 573, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #573 = LD_D
+ { 572, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #572 = LD_BU
+ { 571, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #571 = LD_B
+ { 570, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #570 = LDX_WU
+ { 569, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #569 = LDX_W
+ { 568, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #568 = LDX_HU
+ { 567, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #567 = LDX_H
+ { 566, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #566 = LDX_D
+ { 565, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #565 = LDX_BU
+ { 564, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo46 }, // Inst #564 = LDX_B
+ { 563, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #563 = LDPTR_W
+ { 562, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #562 = LDPTR_D
+ { 561, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #561 = LDPTE
+ { 560, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #560 = LDLE_W
+ { 559, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #559 = LDLE_H
+ { 558, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #558 = LDLE_D
+ { 557, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #557 = LDLE_B
+ { 556, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #556 = LDGT_W
+ { 555, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #555 = LDGT_H
+ { 554, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #554 = LDGT_D
+ { 553, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo46 }, // Inst #553 = LDGT_B
+ { 552, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #552 = LDDIR
+ { 551, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #551 = JIRL
+ { 550, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #550 = IOCSRWR_W
+ { 549, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #549 = IOCSRWR_H
+ { 548, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #548 = IOCSRWR_D
+ { 547, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #547 = IOCSRWR_B
+ { 546, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #546 = IOCSRRD_W
+ { 545, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #545 = IOCSRRD_H
+ { 544, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #544 = IOCSRRD_D
+ { 543, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #543 = IOCSRRD_B
+ { 542, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #542 = INVTLB
+ { 541, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #541 = IDLE
+ { 540, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #540 = IBAR
+ { 539, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #539 = FTINT_W_S
+ { 538, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo74 }, // Inst #538 = FTINT_W_D
+ { 537, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #537 = FTINT_L_S
+ { 536, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #536 = FTINT_L_D
+ { 535, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #535 = FTINTRZ_W_S
+ { 534, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo74 }, // Inst #534 = FTINTRZ_W_D
+ { 533, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo73 }, // Inst #533 = FTINTRZ_L_S
+ { 532, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #532 = FTINTRZ_L_D
+ { 531, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #531 = FTINTRP_W_S
+ { 530, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo74 }, // Inst #530 = FTINTRP_W_D
+ { 529, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #529 = FTINTRP_L_S
+ { 528, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #528 = FTINTRP_L_D
+ { 527, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #527 = FTINTRNE_W_S
+ { 526, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo74 }, // Inst #526 = FTINTRNE_W_D
+ { 525, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #525 = FTINTRNE_L_S
+ { 524, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #524 = FTINTRNE_L_D
+ { 523, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #523 = FTINTRM_W_S
+ { 522, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo74 }, // Inst #522 = FTINTRM_W_D
+ { 521, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #521 = FTINTRM_L_S
+ { 520, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #520 = FTINTRM_L_D
+ { 519, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #519 = FSUB_S
+ { 518, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #518 = FSUB_D
+ { 517, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo78 }, // Inst #517 = FST_S
+ { 516, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo77 }, // Inst #516 = FST_D
+ { 515, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo76 }, // Inst #515 = FSTX_S
+ { 514, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo75 }, // Inst #514 = FSTX_D
+ { 513, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo76 }, // Inst #513 = FSTLE_S
+ { 512, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo75 }, // Inst #512 = FSTLE_D
+ { 511, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo76 }, // Inst #511 = FSTGT_S
+ { 510, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo75 }, // Inst #510 = FSTGT_D
+ { 509, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #509 = FSQRT_S
+ { 508, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #508 = FSQRT_D
+ { 507, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo82 }, // Inst #507 = FSEL_S
+ { 506, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo81 }, // Inst #506 = FSEL_D
+ { 505, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #505 = FSCALEB_S
+ { 504, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo69 }, // Inst #504 = FSCALEB_D
+ { 503, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #503 = FRSQRT_S
+ { 502, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #502 = FRSQRT_D
+ { 501, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #501 = FRINT_S
+ { 500, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #500 = FRINT_D
+ { 499, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #499 = FRECIP_S
+ { 498, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #498 = FRECIP_D
+ { 497, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo80 }, // Inst #497 = FNMSUB_S
+ { 496, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #496 = FNMSUB_D
+ { 495, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo80 }, // Inst #495 = FNMADD_S
+ { 494, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #494 = FNMADD_D
+ { 493, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #493 = FNEG_S
+ { 492, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #492 = FNEG_D
+ { 491, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #491 = FMUL_S
+ { 490, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #490 = FMUL_D
+ { 489, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo80 }, // Inst #489 = FMSUB_S
+ { 488, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #488 = FMSUB_D
+ { 487, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #487 = FMOV_S
+ { 486, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #486 = FMOV_D
+ { 485, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #485 = FMIN_S
+ { 484, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #484 = FMIN_D
+ { 483, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #483 = FMINA_S
+ { 482, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo69 }, // Inst #482 = FMINA_D
+ { 481, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #481 = FMAX_S
+ { 480, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #480 = FMAX_D
+ { 479, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #479 = FMAXA_S
+ { 478, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo69 }, // Inst #478 = FMAXA_D
+ { 477, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo80 }, // Inst #477 = FMADD_S
+ { 476, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #476 = FMADD_D
+ { 475, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #475 = FLOGB_S
+ { 474, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #474 = FLOGB_D
+ { 473, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo78 }, // Inst #473 = FLD_S
+ { 472, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo77 }, // Inst #472 = FLD_D
+ { 471, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo76 }, // Inst #471 = FLDX_S
+ { 470, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo75 }, // Inst #470 = FLDX_D
+ { 469, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo76 }, // Inst #469 = FLDLE_S
+ { 468, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo75 }, // Inst #468 = FLDLE_D
+ { 467, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo76 }, // Inst #467 = FLDGT_S
+ { 466, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo75 }, // Inst #466 = FLDGT_D
+ { 465, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #465 = FFINT_S_W
+ { 464, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo74 }, // Inst #464 = FFINT_S_L
+ { 463, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #463 = FFINT_D_W
+ { 462, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #462 = FFINT_D_L
+ { 461, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #461 = FDIV_S
+ { 460, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #460 = FDIV_D
+ { 459, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo74 }, // Inst #459 = FCVT_S_D
+ { 458, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo73 }, // Inst #458 = FCVT_D_S
+ { 457, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #457 = FCOPYSIGN_S
+ { 456, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #456 = FCOPYSIGN_D
+ { 455, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #455 = FCMP_SUN_S
+ { 454, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #454 = FCMP_SUN_D
+ { 453, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #453 = FCMP_SUNE_S
+ { 452, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #452 = FCMP_SUNE_D
+ { 451, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #451 = FCMP_SULT_S
+ { 450, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #450 = FCMP_SULT_D
+ { 449, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #449 = FCMP_SULE_S
+ { 448, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #448 = FCMP_SULE_D
+ { 447, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #447 = FCMP_SUEQ_S
+ { 446, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #446 = FCMP_SUEQ_D
+ { 445, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #445 = FCMP_SOR_S
+ { 444, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #444 = FCMP_SOR_D
+ { 443, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #443 = FCMP_SNE_S
+ { 442, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #442 = FCMP_SNE_D
+ { 441, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #441 = FCMP_SLT_S
+ { 440, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #440 = FCMP_SLT_D
+ { 439, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #439 = FCMP_SLE_S
+ { 438, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #438 = FCMP_SLE_D
+ { 437, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #437 = FCMP_SEQ_S
+ { 436, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #436 = FCMP_SEQ_D
+ { 435, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #435 = FCMP_SAF_S
+ { 434, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #434 = FCMP_SAF_D
+ { 433, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #433 = FCMP_CUN_S
+ { 432, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #432 = FCMP_CUN_D
+ { 431, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #431 = FCMP_CUNE_S
+ { 430, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #430 = FCMP_CUNE_D
+ { 429, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #429 = FCMP_CULT_S
+ { 428, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #428 = FCMP_CULT_D
+ { 427, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #427 = FCMP_CULE_S
+ { 426, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #426 = FCMP_CULE_D
+ { 425, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #425 = FCMP_CUEQ_S
+ { 424, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #424 = FCMP_CUEQ_D
+ { 423, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #423 = FCMP_COR_S
+ { 422, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #422 = FCMP_COR_D
+ { 421, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #421 = FCMP_CNE_S
+ { 420, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #420 = FCMP_CNE_D
+ { 419, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #419 = FCMP_CLT_S
+ { 418, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #418 = FCMP_CLT_D
+ { 417, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #417 = FCMP_CLE_S
+ { 416, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #416 = FCMP_CLE_D
+ { 415, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #415 = FCMP_CEQ_S
+ { 414, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo71 }, // Inst #414 = FCMP_CEQ_D
+ { 413, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #413 = FCMP_CAF_S
+ { 412, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #412 = FCMP_CAF_D
+ { 411, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo68 }, // Inst #411 = FCLASS_S
+ { 410, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo67 }, // Inst #410 = FCLASS_D
+ { 409, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo70 }, // Inst #409 = FADD_S
+ { 408, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo69 }, // Inst #408 = FADD_D
+ { 407, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo68 }, // Inst #407 = FABS_S
+ { 406, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #406 = FABS_D
+ { 405, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #405 = EXT_W_H
+ { 404, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #404 = EXT_W_B
+ { 403, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #403 = ERTN
+ { 402, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #402 = DIV_WU
+ { 401, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #401 = DIV_W
+ { 400, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #400 = DIV_DU
+ { 399, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo46 }, // Inst #399 = DIV_D
+ { 398, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #398 = DBCL
+ { 397, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #397 = DBAR
+ { 396, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #396 = CTZ_W
+ { 395, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #395 = CTZ_D
+ { 394, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #394 = CTO_W
+ { 393, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #393 = CTO_D
+ { 392, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo66 }, // Inst #392 = CSRXCHG
+ { 391, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo65 }, // Inst #391 = CSRWR
+ { 390, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #390 = CSRRD
+ { 389, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #389 = CRC_W_W_W
+ { 388, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #388 = CRC_W_H_W
+ { 387, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #387 = CRC_W_D_W
+ { 386, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #386 = CRC_W_B_W
+ { 385, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #385 = CRCC_W_W_W
+ { 384, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #384 = CRCC_W_H_W
+ { 383, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #383 = CRCC_W_D_W
+ { 382, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #382 = CRCC_W_B_W
+ { 381, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #381 = CPUCFG
+ { 380, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #380 = CLZ_W
+ { 379, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #379 = CLZ_D
+ { 378, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #378 = CLO_W
+ { 377, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #377 = CLO_D
+ { 376, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo64 }, // Inst #376 = CACOP
+ { 375, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #375 = BYTEPICK_W
+ { 374, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #374 = BYTEPICK_D
+ { 373, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo63 }, // Inst #373 = BSTRPICK_W
+ { 372, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo63 }, // Inst #372 = BSTRPICK_D
+ { 371, 5, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo62 }, // Inst #371 = BSTRINS_W
+ { 370, 5, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo62 }, // Inst #370 = BSTRINS_D
+ { 369, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #369 = BREAK
+ { 368, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo47 }, // Inst #368 = BNEZ
+ { 367, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo50 }, // Inst #367 = BNE
+ { 366, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo50 }, // Inst #366 = BLTU
+ { 365, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo50 }, // Inst #365 = BLT
+ { 364, 1, 0, 4, 0, 0, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, OperandInfo2 }, // Inst #364 = BL
+ { 363, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #363 = BITREV_W
+ { 362, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #362 = BITREV_D
+ { 361, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #361 = BITREV_8B
+ { 360, 2, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo60 }, // Inst #360 = BITREV_4B
+ { 359, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo50 }, // Inst #359 = BGEU
+ { 358, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo50 }, // Inst #358 = BGE
+ { 357, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo47 }, // Inst #357 = BEQZ
+ { 356, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo50 }, // Inst #356 = BEQ
+ { 355, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo61 }, // Inst #355 = BCNEZ
+ { 354, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo61 }, // Inst #354 = BCEQZ
+ { 353, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #353 = B
+ { 352, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #352 = ASRTLE_D
+ { 351, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo60 }, // Inst #351 = ASRTGT_D
+ { 350, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #350 = ANDN
+ { 349, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #349 = ANDI
+ { 348, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #348 = AND
+ { 347, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #347 = AMXOR_W
+ { 346, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #346 = AMXOR_DB_W
+ { 345, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #345 = AMXOR_DB_D
+ { 344, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #344 = AMXOR_D
+ { 343, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #343 = AMSWAP_W
+ { 342, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #342 = AMSWAP_DB_W
+ { 341, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #341 = AMSWAP_DB_D
+ { 340, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #340 = AMSWAP_D
+ { 339, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #339 = AMOR_W
+ { 338, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #338 = AMOR_DB_W
+ { 337, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #337 = AMOR_DB_D
+ { 336, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #336 = AMOR_D
+ { 335, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #335 = AMMIN_WU
+ { 334, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #334 = AMMIN_W
+ { 333, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #333 = AMMIN_DU
+ { 332, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #332 = AMMIN_DB_WU
+ { 331, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #331 = AMMIN_DB_W
+ { 330, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #330 = AMMIN_DB_DU
+ { 329, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #329 = AMMIN_DB_D
+ { 328, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #328 = AMMIN_D
+ { 327, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #327 = AMMAX_WU
+ { 326, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #326 = AMMAX_W
+ { 325, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #325 = AMMAX_DU
+ { 324, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #324 = AMMAX_DB_WU
+ { 323, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #323 = AMMAX_DB_W
+ { 322, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #322 = AMMAX_DB_DU
+ { 321, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #321 = AMMAX_DB_D
+ { 320, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #320 = AMMAX_D
+ { 319, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #319 = AMAND_W
+ { 318, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #318 = AMAND_DB_W
+ { 317, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #317 = AMAND_DB_D
+ { 316, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #316 = AMAND_D
+ { 315, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #315 = AMADD_W
+ { 314, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #314 = AMADD_DB_W
+ { 313, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #313 = AMADD_DB_D
+ { 312, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #312 = AMADD_D
+ { 311, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo58 }, // Inst #311 = ALSL_WU
+ { 310, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo58 }, // Inst #310 = ALSL_W
+ { 309, 4, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo58 }, // Inst #309 = ALSL_D
+ { 308, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #308 = ADD_W
+ { 307, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo46 }, // Inst #307 = ADD_D
+ { 306, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #306 = ADDU16I_D
+ { 305, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #305 = ADDI_W
+ { 304, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo50 }, // Inst #304 = ADDI_D
+ { 303, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo57 }, // Inst #303 = WRFCSR
+ { 302, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo47 }, // Inst #302 = RDFCSR
+ { 301, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #301 = PseudoUNIMP
+ { 300, 1, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, OperandInfo56 }, // Inst #300 = PseudoTAILIndirect
+ { 299, 1, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, OperandInfo2 }, // Inst #299 = PseudoTAIL
+ { 298, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo51 }, // Inst #298 = PseudoST_CFR
+ { 297, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr }, // Inst #297 = PseudoRET
+ { 296, 7, 2, 44, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo55 }, // Inst #296 = PseudoMaskedCmpXchg32
+ { 295, 6, 2, 36, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo52 }, // Inst #295 = PseudoMaskedAtomicSwap32
+ { 294, 7, 3, 48, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo54 }, // Inst #294 = PseudoMaskedAtomicLoadUMin32
+ { 293, 7, 3, 48, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo54 }, // Inst #293 = PseudoMaskedAtomicLoadUMax32
+ { 292, 6, 2, 36, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo52 }, // Inst #292 = PseudoMaskedAtomicLoadSub32
+ { 291, 6, 2, 36, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo52 }, // Inst #291 = PseudoMaskedAtomicLoadNand32
+ { 290, 8, 3, 56, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo53 }, // Inst #290 = PseudoMaskedAtomicLoadMin32
+ { 289, 8, 3, 56, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo53 }, // Inst #289 = PseudoMaskedAtomicLoadMax32
+ { 288, 6, 2, 36, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo52 }, // Inst #288 = PseudoMaskedAtomicLoadAdd32
+ { 287, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #287 = PseudoLI_W
+ { 286, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #286 = PseudoLI_D
+ { 285, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo51 }, // Inst #285 = PseudoLD_CFR
+ { 284, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #284 = PseudoLA_TLS_LE
+ { 283, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #283 = PseudoLA_TLS_LD_LARGE
+ { 282, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo47 }, // Inst #282 = PseudoLA_TLS_LD
+ { 281, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #281 = PseudoLA_TLS_IE_LARGE
+ { 280, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo47 }, // Inst #280 = PseudoLA_TLS_IE
+ { 279, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #279 = PseudoLA_TLS_GD_LARGE
+ { 278, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo47 }, // Inst #278 = PseudoLA_TLS_GD
+ { 277, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo50 }, // Inst #277 = PseudoLA_PCREL_LARGE
+ { 276, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #276 = PseudoLA_PCREL
+ { 275, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo50 }, // Inst #275 = PseudoLA_GOT_LARGE
+ { 274, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo47 }, // Inst #274 = PseudoLA_GOT
+ { 273, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo50 }, // Inst #273 = PseudoLA_ABS_LARGE
+ { 272, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #272 = PseudoLA_ABS
+ { 271, 2, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo47 }, // Inst #271 = PseudoJIRL_TAIL
+ { 270, 2, 0, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, OperandInfo47 }, // Inst #270 = PseudoJIRL_CALL
+ { 269, 5, 2, 36, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo49 }, // Inst #269 = PseudoCmpXchg64
+ { 268, 5, 2, 36, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo49 }, // Inst #268 = PseudoCmpXchg32
+ { 267, 1, 0, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList3, OperandInfo48 }, // Inst #267 = PseudoCALLIndirect
+ { 266, 1, 0, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList3, OperandInfo2 }, // Inst #266 = PseudoCALL
+ { 265, 1, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo2 }, // Inst #265 = PseudoB_TAIL
+ { 264, 2, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo47 }, // Inst #264 = PseudoBRIND
+ { 263, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo2 }, // Inst #263 = PseudoBR
+ { 262, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #262 = PseudoAtomicSwap32
+ { 261, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo46 }, // Inst #261 = PseudoAtomicStoreW
+ { 260, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo46 }, // Inst #260 = PseudoAtomicStoreD
+ { 259, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #259 = PseudoAtomicLoadXor32
+ { 258, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #258 = PseudoAtomicLoadSub32
+ { 257, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #257 = PseudoAtomicLoadOr32
+ { 256, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #256 = PseudoAtomicLoadNand64
+ { 255, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #255 = PseudoAtomicLoadNand32
+ { 254, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #254 = PseudoAtomicLoadAnd32
+ { 253, 5, 2, 24, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo45 }, // Inst #253 = PseudoAtomicLoadAdd32
+ { 252, 2, 0, 4, 0, 1, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, OperandInfo10 }, // Inst #252 = ADJCALLSTACKUP
+ { 251, 2, 0, 4, 0, 1, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, OperandInfo10 }, // Inst #251 = ADJCALLSTACKDOWN
+ { 250, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo44 }, // Inst #250 = G_UBFX
+ { 249, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo44 }, // Inst #249 = G_SBFX
+ { 248, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #248 = G_VECREDUCE_UMIN
+ { 247, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #247 = G_VECREDUCE_UMAX
+ { 246, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #246 = G_VECREDUCE_SMIN
+ { 245, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #245 = G_VECREDUCE_SMAX
+ { 244, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #244 = G_VECREDUCE_XOR
+ { 243, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #243 = G_VECREDUCE_OR
+ { 242, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #242 = G_VECREDUCE_AND
+ { 241, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #241 = G_VECREDUCE_MUL
+ { 240, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #240 = G_VECREDUCE_ADD
+ { 239, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #239 = G_VECREDUCE_FMIN
+ { 238, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #238 = G_VECREDUCE_FMAX
+ { 237, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #237 = G_VECREDUCE_FMUL
+ { 236, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #236 = G_VECREDUCE_FADD
+ { 235, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #235 = G_VECREDUCE_SEQ_FMUL
+ { 234, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #234 = G_VECREDUCE_SEQ_FADD
+ { 233, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo22 }, // Inst #233 = G_BZERO
+ { 232, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #232 = G_MEMSET
+ { 231, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #231 = G_MEMMOVE
+ { 230, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo40 }, // Inst #230 = G_MEMCPY_INLINE
+ { 229, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #229 = G_MEMCPY
+ { 228, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo42 }, // Inst #228 = G_WRITE_REGISTER
+ { 227, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo21 }, // Inst #227 = G_READ_REGISTER
+ { 226, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo25 }, // Inst #226 = G_STRICT_FSQRT
+ { 225, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo19 }, // Inst #225 = G_STRICT_FMA
+ { 224, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #224 = G_STRICT_FREM
+ { 223, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #223 = G_STRICT_FDIV
+ { 222, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #222 = G_STRICT_FMUL
+ { 221, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #221 = G_STRICT_FSUB
+ { 220, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #220 = G_STRICT_FADD
+ { 219, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo26 }, // Inst #219 = G_DYN_STACKALLOC
+ { 218, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #218 = G_JUMP_TABLE
+ { 217, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #217 = G_BLOCK_ADDR
+ { 216, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #216 = G_ADDRSPACE_CAST
+ { 215, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #215 = G_FNEARBYINT
+ { 214, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #214 = G_FRINT
+ { 213, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #213 = G_FFLOOR
+ { 212, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #212 = G_FSQRT
+ { 211, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #211 = G_FSIN
+ { 210, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #210 = G_FCOS
+ { 209, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #209 = G_FCEIL
+ { 208, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #208 = G_BITREVERSE
+ { 207, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #207 = G_BSWAP
+ { 206, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #206 = G_CTPOP
+ { 205, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #205 = G_CTLZ_ZERO_UNDEF
+ { 204, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #204 = G_CTLZ
+ { 203, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #203 = G_CTTZ_ZERO_UNDEF
+ { 202, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #202 = G_CTTZ
+ { 201, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo41 }, // Inst #201 = G_SHUFFLE_VECTOR
+ { 200, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #200 = G_EXTRACT_VECTOR_ELT
+ { 199, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo39 }, // Inst #199 = G_INSERT_VECTOR_ELT
+ { 198, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo38 }, // Inst #198 = G_BRJT
+ { 197, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo2 }, // Inst #197 = G_BR
+ { 196, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #196 = G_LLROUND
+ { 195, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #195 = G_LROUND
+ { 194, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #194 = G_ABS
+ { 193, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #193 = G_UMAX
+ { 192, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #192 = G_UMIN
+ { 191, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #191 = G_SMAX
+ { 190, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #190 = G_SMIN
+ { 189, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #189 = G_PTRMASK
+ { 188, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #188 = G_PTR_ADD
+ { 187, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #187 = G_FMAXIMUM
+ { 186, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #186 = G_FMINIMUM
+ { 185, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #185 = G_FMAXNUM_IEEE
+ { 184, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #184 = G_FMINNUM_IEEE
+ { 183, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #183 = G_FMAXNUM
+ { 182, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #182 = G_FMINNUM
+ { 181, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #181 = G_FCANONICALIZE
+ { 180, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo32 }, // Inst #180 = G_IS_FPCLASS
+ { 179, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #179 = G_FCOPYSIGN
+ { 178, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #178 = G_FABS
+ { 177, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #177 = G_UITOFP
+ { 176, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #176 = G_SITOFP
+ { 175, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #175 = G_FPTOUI
+ { 174, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #174 = G_FPTOSI
+ { 173, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #173 = G_FPTRUNC
+ { 172, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #172 = G_FPEXT
+ { 171, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #171 = G_FNEG
+ { 170, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #170 = G_FLOG10
+ { 169, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #169 = G_FLOG2
+ { 168, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #168 = G_FLOG
+ { 167, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #167 = G_FEXP2
+ { 166, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #166 = G_FEXP
+ { 165, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #165 = G_FPOWI
+ { 164, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #164 = G_FPOW
+ { 163, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #163 = G_FREM
+ { 162, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #162 = G_FDIV
+ { 161, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #161 = G_FMAD
+ { 160, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #160 = G_FMA
+ { 159, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #159 = G_FMUL
+ { 158, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #158 = G_FSUB
+ { 157, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #157 = G_FADD
+ { 156, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #156 = G_UDIVFIXSAT
+ { 155, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #155 = G_SDIVFIXSAT
+ { 154, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #154 = G_UDIVFIX
+ { 153, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #153 = G_SDIVFIX
+ { 152, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #152 = G_UMULFIXSAT
+ { 151, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #151 = G_SMULFIXSAT
+ { 150, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #150 = G_UMULFIX
+ { 149, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #149 = G_SMULFIX
+ { 148, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #148 = G_SSHLSAT
+ { 147, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #147 = G_USHLSAT
+ { 146, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #146 = G_SSUBSAT
+ { 145, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #145 = G_USUBSAT
+ { 144, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #144 = G_SADDSAT
+ { 143, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #143 = G_UADDSAT
+ { 142, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #142 = G_SMULH
+ { 141, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #141 = G_UMULH
+ { 140, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #140 = G_SMULO
+ { 139, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #139 = G_UMULO
+ { 138, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #138 = G_SSUBE
+ { 137, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #137 = G_SSUBO
+ { 136, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #136 = G_SADDE
+ { 135, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #135 = G_SADDO
+ { 134, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #134 = G_USUBE
+ { 133, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #133 = G_USUBO
+ { 132, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #132 = G_UADDE
+ { 131, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #131 = G_UADDO
+ { 130, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #130 = G_SELECT
+ { 129, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo35 }, // Inst #129 = G_FCMP
+ { 128, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo35 }, // Inst #128 = G_ICMP
+ { 127, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #127 = G_ROTL
+ { 126, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #126 = G_ROTR
+ { 125, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo34 }, // Inst #125 = G_FSHR
+ { 124, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo34 }, // Inst #124 = G_FSHL
+ { 123, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #123 = G_ASHR
+ { 122, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #122 = G_LSHR
+ { 121, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #121 = G_SHL
+ { 120, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #120 = G_ZEXT
+ { 119, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #119 = G_SEXT_INREG
+ { 118, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #118 = G_SEXT
+ { 117, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo32 }, // Inst #117 = G_VAARG
+ { 116, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo20 }, // Inst #116 = G_VASTART
+ { 115, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #115 = G_FCONSTANT
+ { 114, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #114 = G_CONSTANT
+ { 113, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #113 = G_TRUNC
+ { 112, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #112 = G_ANYEXT
+ { 111, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo2 }, // Inst #111 = G_INTRINSIC_W_SIDE_EFFECTS
+ { 110, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo2 }, // Inst #110 = G_INTRINSIC
+ { 109, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr }, // Inst #109 = G_INVOKE_REGION_START
+ { 108, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo20 }, // Inst #108 = G_BRINDIRECT
+ { 107, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo21 }, // Inst #107 = G_BRCOND
+ { 106, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo10 }, // Inst #106 = G_FENCE
+ { 105, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #105 = G_ATOMICRMW_UDEC_WRAP
+ { 104, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #104 = G_ATOMICRMW_UINC_WRAP
+ { 103, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #103 = G_ATOMICRMW_FMIN
+ { 102, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #102 = G_ATOMICRMW_FMAX
+ { 101, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #101 = G_ATOMICRMW_FSUB
+ { 100, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #100 = G_ATOMICRMW_FADD
+ { 99, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #99 = G_ATOMICRMW_UMIN
+ { 98, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #98 = G_ATOMICRMW_UMAX
+ { 97, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #97 = G_ATOMICRMW_MIN
+ { 96, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #96 = G_ATOMICRMW_MAX
+ { 95, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #95 = G_ATOMICRMW_XOR
+ { 94, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #94 = G_ATOMICRMW_OR
+ { 93, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #93 = G_ATOMICRMW_NAND
+ { 92, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #92 = G_ATOMICRMW_AND
+ { 91, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #91 = G_ATOMICRMW_SUB
+ { 90, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #90 = G_ATOMICRMW_ADD
+ { 89, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #89 = G_ATOMICRMW_XCHG
+ { 88, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo30 }, // Inst #88 = G_ATOMIC_CMPXCHG
+ { 87, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo29 }, // Inst #87 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
+ { 86, 5, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo28 }, // Inst #86 = G_INDEXED_STORE
+ { 85, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo23 }, // Inst #85 = G_STORE
+ { 84, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #84 = G_INDEXED_ZEXTLOAD
+ { 83, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #83 = G_INDEXED_SEXTLOAD
+ { 82, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #82 = G_INDEXED_LOAD
+ { 81, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #81 = G_ZEXTLOAD
+ { 80, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #80 = G_SEXTLOAD
+ { 79, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #79 = G_LOAD
+ { 78, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo20 }, // Inst #78 = G_READCYCLECOUNTER
+ { 77, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #77 = G_INTRINSIC_ROUNDEVEN
+ { 76, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #76 = G_INTRINSIC_LRINT
+ { 75, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #75 = G_INTRINSIC_ROUND
+ { 74, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #74 = G_INTRINSIC_TRUNC
+ { 73, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo26 }, // Inst #73 = G_INTRINSIC_FPTRUNC_ROUND
+ { 72, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #72 = G_FREEZE
+ { 71, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #71 = G_BITCAST
+ { 70, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #70 = G_INTTOPTR
+ { 69, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #69 = G_PTRTOINT
+ { 68, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #68 = G_CONCAT_VECTORS
+ { 67, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #67 = G_BUILD_VECTOR_TRUNC
+ { 66, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #66 = G_BUILD_VECTOR
+ { 65, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #65 = G_MERGE_VALUES
+ { 64, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo24 }, // Inst #64 = G_INSERT
+ { 63, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #63 = G_UNMERGE_VALUES
+ { 62, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo22 }, // Inst #62 = G_EXTRACT
+ { 61, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #61 = G_GLOBAL_VALUE
+ { 60, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #60 = G_FRAME_INDEX
+ { 59, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo20 }, // Inst #59 = G_PHI
+ { 58, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo20 }, // Inst #58 = G_IMPLICIT_DEF
+ { 57, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #57 = G_XOR
+ { 56, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #56 = G_OR
+ { 55, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #55 = G_AND
+ { 54, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #54 = G_UDIVREM
+ { 53, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #53 = G_SDIVREM
+ { 52, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #52 = G_UREM
+ { 51, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #51 = G_SREM
+ { 50, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #50 = G_UDIV
+ { 49, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #49 = G_SDIV
+ { 48, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #48 = G_MUL
+ { 47, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #47 = G_SUB
+ { 46, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #46 = G_ADD
+ { 45, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #45 = G_ASSERT_ALIGN
+ { 44, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #44 = G_ASSERT_ZEXT
+ { 43, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #43 = G_ASSERT_SEXT
+ { 42, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #42 = MEMBARRIER
+ { 41, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #41 = ICALL_BRANCH_FUNNEL
+ { 40, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo16 }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
+ { 39, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo15 }, // Inst #39 = PATCHABLE_EVENT_CALL
+ { 38, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #38 = PATCHABLE_TAIL_CALL
+ { 37, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #37 = PATCHABLE_FUNCTION_EXIT
+ { 36, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #36 = PATCHABLE_RET
+ { 35, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #35 = PATCHABLE_FUNCTION_ENTER
+ { 34, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #34 = PATCHABLE_OP
+ { 33, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #33 = FAULTING_OP
+ { 32, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo14 }, // Inst #32 = LOCAL_ESCAPE
+ { 31, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #31 = STATEPOINT
+ { 30, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo13 }, // Inst #30 = PREALLOCATED_ARG
+ { 29, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo3 }, // Inst #29 = PREALLOCATED_SETUP
+ { 28, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo12 }, // Inst #28 = LOAD_STACK_GUARD
+ { 27, 6, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo11 }, // Inst #27 = PATCHPOINT
+ { 26, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #26 = FENTRY_CALL
+ { 25, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo10 }, // Inst #25 = STACKMAP
+ { 24, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo9 }, // Inst #24 = ARITH_FENCE
+ { 23, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo8 }, // Inst #23 = PSEUDO_PROBE
+ { 22, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo3 }, // Inst #22 = LIFETIME_END
+ { 21, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo3 }, // Inst #21 = LIFETIME_START
+ { 20, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #20 = BUNDLE
+ { 19, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo7 }, // Inst #19 = COPY
+ { 18, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo7 }, // Inst #18 = REG_SEQUENCE
+ { 17, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo2 }, // Inst #17 = DBG_LABEL
+ { 16, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #16 = DBG_PHI
+ { 15, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #15 = DBG_INSTR_REF
+ { 14, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #14 = DBG_VALUE_LIST
+ { 13, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #13 = DBG_VALUE
+ { 12, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo4 }, // Inst #12 = COPY_TO_REGCLASS
+ { 11, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo6 }, // Inst #11 = SUBREG_TO_REG
+ { 10, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo2 }, // Inst #10 = IMPLICIT_DEF
+ { 9, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo5 }, // Inst #9 = INSERT_SUBREG
+ { 8, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo4 }, // Inst #8 = EXTRACT_SUBREG
+ { 7, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #7 = KILL
+ { 6, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #6 = ANNOTATION_LABEL
+ { 5, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #5 = GC_LABEL
+ { 4, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #4 = EH_LABEL
+ { 3, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #3 = CFI_INSTRUCTION
+ { 2, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #2 = INLINEASM_BR
+ { 1, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #1 = INLINEASM
+ { 0, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo2 }, // Inst #0 = PHI
+};
+
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Woverlength-strings"
+#endif
+extern const char LoongArchInstrNameData[] = {
+ /* 0 */ "G_FLOG10\0"
+ /* 9 */ "PseudoMaskedAtomicLoadSub32\0"
+ /* 37 */ "PseudoAtomicLoadSub32\0"
+ /* 59 */ "PseudoMaskedAtomicLoadAdd32\0"
+ /* 87 */ "PseudoAtomicLoadAdd32\0"
+ /* 109 */ "PseudoAtomicLoadAnd32\0"
+ /* 131 */ "PseudoMaskedAtomicLoadNand32\0"
+ /* 160 */ "PseudoAtomicLoadNand32\0"
+ /* 183 */ "PseudoMaskedCmpXchg32\0"
+ /* 205 */ "PseudoCmpXchg32\0"
+ /* 221 */ "PseudoMaskedAtomicLoadUMin32\0"
+ /* 250 */ "PseudoMaskedAtomicLoadMin32\0"
+ /* 278 */ "PseudoMaskedAtomicSwap32\0"
+ /* 303 */ "PseudoAtomicSwap32\0"
+ /* 322 */ "PseudoAtomicLoadOr32\0"
+ /* 343 */ "PseudoAtomicLoadXor32\0"
+ /* 365 */ "PseudoMaskedAtomicLoadUMax32\0"
+ /* 394 */ "PseudoMaskedAtomicLoadMax32\0"
+ /* 422 */ "G_FLOG2\0"
+ /* 430 */ "G_FEXP2\0"
+ /* 438 */ "MOVFR2GR_S_64\0"
+ /* 452 */ "MOVGR2FR_W_64\0"
+ /* 466 */ "PseudoAtomicLoadNand64\0"
+ /* 489 */ "PseudoCmpXchg64\0"
+ /* 505 */ "G_FMA\0"
+ /* 511 */ "G_STRICT_FMA\0"
+ /* 524 */ "BITREV_4B\0"
+ /* 534 */ "BITREV_8B\0"
+ /* 544 */ "INVTLB\0"
+ /* 551 */ "G_FSUB\0"
+ /* 558 */ "G_STRICT_FSUB\0"
+ /* 572 */ "G_ATOMICRMW_FSUB\0"
+ /* 589 */ "G_SUB\0"
+ /* 595 */ "G_ATOMICRMW_SUB\0"
+ /* 611 */ "LD_B\0"
+ /* 616 */ "IOCSRRD_B\0"
+ /* 626 */ "LDLE_B\0"
+ /* 633 */ "STLE_B\0"
+ /* 640 */ "IOCSRWR_B\0"
+ /* 650 */ "LDGT_B\0"
+ /* 657 */ "STGT_B\0"
+ /* 664 */ "ST_B\0"
+ /* 669 */ "EXT_W_B\0"
+ /* 677 */ "LDX_B\0"
+ /* 683 */ "STX_B\0"
+ /* 689 */ "G_INTRINSIC\0"
+ /* 701 */ "G_FPTRUNC\0"
+ /* 711 */ "G_INTRINSIC_TRUNC\0"
+ /* 729 */ "G_TRUNC\0"
+ /* 737 */ "G_BUILD_VECTOR_TRUNC\0"
+ /* 758 */ "G_DYN_STACKALLOC\0"
+ /* 775 */ "G_FMAD\0"
+ /* 782 */ "G_INDEXED_SEXTLOAD\0"
+ /* 801 */ "G_SEXTLOAD\0"
+ /* 812 */ "G_INDEXED_ZEXTLOAD\0"
+ /* 831 */ "G_ZEXTLOAD\0"
+ /* 842 */ "G_INDEXED_LOAD\0"
+ /* 857 */ "G_LOAD\0"
+ /* 864 */ "G_VECREDUCE_FADD\0"
+ /* 881 */ "G_FADD\0"
+ /* 888 */ "G_VECREDUCE_SEQ_FADD\0"
+ /* 909 */ "G_STRICT_FADD\0"
+ /* 923 */ "G_ATOMICRMW_FADD\0"
+ /* 940 */ "G_VECREDUCE_ADD\0"
+ /* 956 */ "G_ADD\0"
+ /* 962 */ "G_PTR_ADD\0"
+ /* 972 */ "G_ATOMICRMW_ADD\0"
+ /* 988 */ "PseudoLA_TLS_GD\0"
+ /* 1004 */ "PRELD\0"
+ /* 1010 */ "PseudoLA_TLS_LD\0"
+ /* 1026 */ "G_ATOMICRMW_NAND\0"
+ /* 1043 */ "G_VECREDUCE_AND\0"
+ /* 1059 */ "G_AND\0"
+ /* 1065 */ "G_ATOMICRMW_AND\0"
+ /* 1081 */ "LIFETIME_END\0"
+ /* 1094 */ "PseudoBRIND\0"
+ /* 1106 */ "G_BRCOND\0"
+ /* 1115 */ "G_LLROUND\0"
+ /* 1125 */ "G_LROUND\0"
+ /* 1134 */ "G_INTRINSIC_ROUND\0"
+ /* 1152 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
+ /* 1178 */ "LOAD_STACK_GUARD\0"
+ /* 1195 */ "TLBRD\0"
+ /* 1201 */ "CSRRD\0"
+ /* 1207 */ "FMINA_D\0"
+ /* 1215 */ "SRA_D\0"
+ /* 1221 */ "FMAXA_D\0"
+ /* 1229 */ "AMADD_DB_D\0"
+ /* 1240 */ "AMAND_DB_D\0"
+ /* 1251 */ "AMMIN_DB_D\0"
+ /* 1262 */ "AMSWAP_DB_D\0"
+ /* 1274 */ "AMOR_DB_D\0"
+ /* 1284 */ "AMXOR_DB_D\0"
+ /* 1295 */ "AMMAX_DB_D\0"
+ /* 1306 */ "FSCALEB_D\0"
+ /* 1316 */ "FLOGB_D\0"
+ /* 1324 */ "FSUB_D\0"
+ /* 1331 */ "FMSUB_D\0"
+ /* 1339 */ "FNMSUB_D\0"
+ /* 1348 */ "REVB_D\0"
+ /* 1355 */ "SC_D\0"
+ /* 1360 */ "FADD_D\0"
+ /* 1367 */ "AMADD_D\0"
+ /* 1375 */ "FMADD_D\0"
+ /* 1383 */ "FNMADD_D\0"
+ /* 1392 */ "FLD_D\0"
+ /* 1398 */ "AMAND_D\0"
+ /* 1406 */ "MOD_D\0"
+ /* 1412 */ "IOCSRRD_D\0"
+ /* 1422 */ "FCMP_CLE_D\0"
+ /* 1433 */ "FLDLE_D\0"
+ /* 1441 */ "FCMP_SLE_D\0"
+ /* 1452 */ "ASRTLE_D\0"
+ /* 1461 */ "FSTLE_D\0"
+ /* 1469 */ "FCMP_CULE_D\0"
+ /* 1481 */ "FCMP_SULE_D\0"
+ /* 1493 */ "RDTIME_D\0"
+ /* 1502 */ "FCMP_CNE_D\0"
+ /* 1513 */ "FCMP_SNE_D\0"
+ /* 1524 */ "FCMP_CUNE_D\0"
+ /* 1536 */ "FCMP_SUNE_D\0"
+ /* 1548 */ "FCMP_CAF_D\0"
+ /* 1559 */ "FCMP_SAF_D\0"
+ /* 1570 */ "FNEG_D\0"
+ /* 1577 */ "MULH_D\0"
+ /* 1584 */ "REVH_D\0"
+ /* 1591 */ "LU32I_D\0"
+ /* 1599 */ "LU52I_D\0"
+ /* 1607 */ "ADDU16I_D\0"
+ /* 1617 */ "SRAI_D\0"
+ /* 1624 */ "ADDI_D\0"
+ /* 1631 */ "SLLI_D\0"
+ /* 1638 */ "SRLI_D\0"
+ /* 1645 */ "PseudoLI_D\0"
+ /* 1656 */ "ROTRI_D\0"
+ /* 1664 */ "BYTEPICK_D\0"
+ /* 1675 */ "BSTRPICK_D\0"
+ /* 1686 */ "FSEL_D\0"
+ /* 1693 */ "SLL_D\0"
+ /* 1699 */ "SRL_D\0"
+ /* 1705 */ "ALSL_D\0"
+ /* 1712 */ "FMUL_D\0"
+ /* 1719 */ "FTINTRNE_L_D\0"
+ /* 1732 */ "FTINTRM_L_D\0"
+ /* 1744 */ "FTINTRP_L_D\0"
+ /* 1756 */ "FTINT_L_D\0"
+ /* 1766 */ "FTINTRZ_L_D\0"
+ /* 1778 */ "FCOPYSIGN_D\0"
+ /* 1790 */ "FMIN_D\0"
+ /* 1797 */ "AMMIN_D\0"
+ /* 1805 */ "FCMP_CUN_D\0"
+ /* 1816 */ "FCMP_SUN_D\0"
+ /* 1827 */ "CLO_D\0"
+ /* 1833 */ "CTO_D\0"
+ /* 1839 */ "AMSWAP_D\0"
+ /* 1848 */ "FRECIP_D\0"
+ /* 1857 */ "FCMP_CEQ_D\0"
+ /* 1868 */ "FCMP_SEQ_D\0"
+ /* 1879 */ "FCMP_CUEQ_D\0"
+ /* 1891 */ "FCMP_SUEQ_D\0"
+ /* 1903 */ "MOVGR2FR_D\0"
+ /* 1914 */ "MOVFR2GR_D\0"
+ /* 1925 */ "FCMP_COR_D\0"
+ /* 1936 */ "AMOR_D\0"
+ /* 1943 */ "FCMP_SOR_D\0"
+ /* 1954 */ "AMXOR_D\0"
+ /* 1962 */ "ROTR_D\0"
+ /* 1969 */ "LDPTR_D\0"
+ /* 1977 */ "STPTR_D\0"
+ /* 1985 */ "IOCSRWR_D\0"
+ /* 1995 */ "FABS_D\0"
+ /* 2002 */ "BSTRINS_D\0"
+ /* 2012 */ "FCLASS_D\0"
+ /* 2021 */ "FCVT_S_D\0"
+ /* 2030 */ "FLDGT_D\0"
+ /* 2038 */ "ASRTGT_D\0"
+ /* 2047 */ "FSTGT_D\0"
+ /* 2055 */ "FCMP_CLT_D\0"
+ /* 2066 */ "FCMP_SLT_D\0"
+ /* 2077 */ "FCMP_CULT_D\0"
+ /* 2089 */ "FCMP_SULT_D\0"
+ /* 2101 */ "FRINT_D\0"
+ /* 2109 */ "FSQRT_D\0"
+ /* 2117 */ "FRSQRT_D\0"
+ /* 2126 */ "FST_D\0"
+ /* 2132 */ "BITREV_D\0"
+ /* 2141 */ "FDIV_D\0"
+ /* 2148 */ "FMOV_D\0"
+ /* 2155 */ "FTINTRNE_W_D\0"
+ /* 2168 */ "FTINTRM_W_D\0"
+ /* 2180 */ "FTINTRP_W_D\0"
+ /* 2192 */ "FTINT_W_D\0"
+ /* 2202 */ "FTINTRZ_W_D\0"
+ /* 2214 */ "FMAX_D\0"
+ /* 2221 */ "AMMAX_D\0"
+ /* 2229 */ "FLDX_D\0"
+ /* 2236 */ "FSTX_D\0"
+ /* 2243 */ "CLZ_D\0"
+ /* 2249 */ "CTZ_D\0"
+ /* 2255 */ "PseudoAtomicStoreD\0"
+ /* 2274 */ "PSEUDO_PROBE\0"
+ /* 2287 */ "G_SSUBE\0"
+ /* 2295 */ "G_USUBE\0"
+ /* 2303 */ "G_FENCE\0"
+ /* 2311 */ "ARITH_FENCE\0"
+ /* 2323 */ "REG_SEQUENCE\0"
+ /* 2336 */ "G_SADDE\0"
+ /* 2344 */ "G_UADDE\0"
+ /* 2352 */ "G_FMINNUM_IEEE\0"
+ /* 2367 */ "G_FMAXNUM_IEEE\0"
+ /* 2382 */ "BGE\0"
+ /* 2386 */ "PseudoLA_TLS_GD_LARGE\0"
+ /* 2408 */ "PseudoLA_TLS_LD_LARGE\0"
+ /* 2430 */ "PseudoLA_TLS_IE_LARGE\0"
+ /* 2452 */ "PseudoLA_PCREL_LARGE\0"
+ /* 2473 */ "PseudoLA_ABS_LARGE\0"
+ /* 2492 */ "PseudoLA_GOT_LARGE\0"
+ /* 2511 */ "PseudoLA_TLS_IE\0"
+ /* 2527 */ "G_JUMP_TABLE\0"
+ /* 2540 */ "IDLE\0"
+ /* 2545 */ "BUNDLE\0"
+ /* 2552 */ "PseudoLA_TLS_LE\0"
+ /* 2568 */ "BNE\0"
+ /* 2572 */ "G_MEMCPY_INLINE\0"
+ /* 2588 */ "LOCAL_ESCAPE\0"
+ /* 2601 */ "G_INDEXED_STORE\0"
+ /* 2617 */ "G_STORE\0"
+ /* 2625 */ "G_BITREVERSE\0"
+ /* 2638 */ "LDPTE\0"
+ /* 2644 */ "DBG_VALUE\0"
+ /* 2654 */ "G_GLOBAL_VALUE\0"
+ /* 2669 */ "G_MEMMOVE\0"
+ /* 2679 */ "G_FREEZE\0"
+ /* 2688 */ "G_FCANONICALIZE\0"
+ /* 2704 */ "MOVGR2CF\0"
+ /* 2713 */ "G_CTLZ_ZERO_UNDEF\0"
+ /* 2731 */ "G_CTTZ_ZERO_UNDEF\0"
+ /* 2749 */ "G_IMPLICIT_DEF\0"
+ /* 2764 */ "DBG_INSTR_REF\0"
+ /* 2778 */ "G_FNEG\0"
+ /* 2785 */ "EXTRACT_SUBREG\0"
+ /* 2800 */ "INSERT_SUBREG\0"
+ /* 2814 */ "G_SEXT_INREG\0"
+ /* 2827 */ "SUBREG_TO_REG\0"
+ /* 2841 */ "CPUCFG\0"
+ /* 2848 */ "G_ATOMIC_CMPXCHG\0"
+ /* 2865 */ "CSRXCHG\0"
+ /* 2873 */ "G_ATOMICRMW_XCHG\0"
+ /* 2890 */ "G_FLOG\0"
+ /* 2897 */ "G_VAARG\0"
+ /* 2905 */ "PREALLOCATED_ARG\0"
+ /* 2922 */ "REVB_2H\0"
+ /* 2930 */ "REVB_4H\0"
+ /* 2938 */ "TLBSRCH\0"
+ /* 2946 */ "G_SMULH\0"
+ /* 2954 */ "G_UMULH\0"
+ /* 2962 */ "TLBFLUSH\0"
+ /* 2971 */ "LD_H\0"
+ /* 2976 */ "IOCSRRD_H\0"
+ /* 2986 */ "LDLE_H\0"
+ /* 2993 */ "STLE_H\0"
+ /* 3000 */ "IOCSRWR_H\0"
+ /* 3010 */ "LDGT_H\0"
+ /* 3017 */ "STGT_H\0"
+ /* 3024 */ "ST_H\0"
+ /* 3029 */ "EXT_W_H\0"
+ /* 3037 */ "LDX_H\0"
+ /* 3043 */ "STX_H\0"
+ /* 3049 */ "PCALAU12I\0"
+ /* 3059 */ "PCADDU12I\0"
+ /* 3069 */ "PCADDU18I\0"
+ /* 3079 */ "PCADDI\0"
+ /* 3086 */ "ANDI\0"
+ /* 3091 */ "DBG_PHI\0"
+ /* 3099 */ "XORI\0"
+ /* 3104 */ "G_FPTOSI\0"
+ /* 3113 */ "SLTI\0"
+ /* 3118 */ "G_FPTOUI\0"
+ /* 3127 */ "SLTUI\0"
+ /* 3133 */ "G_FPOWI\0"
+ /* 3141 */ "BREAK\0"
+ /* 3147 */ "G_PTRMASK\0"
+ /* 3157 */ "BL\0"
+ /* 3160 */ "DBCL\0"
+ /* 3165 */ "GC_LABEL\0"
+ /* 3174 */ "DBG_LABEL\0"
+ /* 3184 */ "EH_LABEL\0"
+ /* 3193 */ "ANNOTATION_LABEL\0"
+ /* 3210 */ "ICALL_BRANCH_FUNNEL\0"
+ /* 3230 */ "PseudoLA_PCREL\0"
+ /* 3245 */ "G_FSHL\0"
+ /* 3252 */ "G_SHL\0"
+ /* 3258 */ "PseudoB_TAIL\0"
+ /* 3271 */ "PseudoJIRL_TAIL\0"
+ /* 3287 */ "PseudoTAIL\0"
+ /* 3298 */ "G_FCEIL\0"
+ /* 3306 */ "SYSCALL\0"
+ /* 3314 */ "PATCHABLE_TAIL_CALL\0"
+ /* 3334 */ "PseudoJIRL_CALL\0"
+ /* 3350 */ "PATCHABLE_TYPED_EVENT_CALL\0"
+ /* 3377 */ "PATCHABLE_EVENT_CALL\0"
+ /* 3398 */ "FENTRY_CALL\0"
+ /* 3410 */ "PseudoCALL\0"
+ /* 3421 */ "TLBFILL\0"
+ /* 3429 */ "KILL\0"
+ /* 3434 */ "JIRL\0"
+ /* 3439 */ "G_ROTL\0"
+ /* 3446 */ "G_VECREDUCE_FMUL\0"
+ /* 3463 */ "G_FMUL\0"
+ /* 3470 */ "G_VECREDUCE_SEQ_FMUL\0"
+ /* 3491 */ "G_STRICT_FMUL\0"
+ /* 3505 */ "G_VECREDUCE_MUL\0"
+ /* 3521 */ "G_MUL\0"
+ /* 3527 */ "FFINT_D_L\0"
+ /* 3537 */ "FFINT_S_L\0"
+ /* 3547 */ "G_FREM\0"
+ /* 3554 */ "G_STRICT_FREM\0"
+ /* 3568 */ "G_SREM\0"
+ /* 3575 */ "G_UREM\0"
+ /* 3582 */ "G_SDIVREM\0"
+ /* 3592 */ "G_UDIVREM\0"
+ /* 3602 */ "INLINEASM\0"
+ /* 3612 */ "G_FMINIMUM\0"
+ /* 3623 */ "G_FMAXIMUM\0"
+ /* 3634 */ "G_FMINNUM\0"
+ /* 3644 */ "G_FMAXNUM\0"
+ /* 3654 */ "ANDN\0"
+ /* 3659 */ "G_INTRINSIC_ROUNDEVEN\0"
+ /* 3681 */ "G_ASSERT_ALIGN\0"
+ /* 3696 */ "G_FCOPYSIGN\0"
+ /* 3708 */ "G_VECREDUCE_FMIN\0"
+ /* 3725 */ "G_ATOMICRMW_FMIN\0"
+ /* 3742 */ "G_VECREDUCE_SMIN\0"
+ /* 3759 */ "G_SMIN\0"
+ /* 3766 */ "G_VECREDUCE_UMIN\0"
+ /* 3783 */ "G_UMIN\0"
+ /* 3790 */ "G_ATOMICRMW_UMIN\0"
+ /* 3807 */ "G_ATOMICRMW_MIN\0"
+ /* 3823 */ "G_FSIN\0"
+ /* 3830 */ "CFI_INSTRUCTION\0"
+ /* 3846 */ "ORN\0"
+ /* 3850 */ "ERTN\0"
+ /* 3855 */ "ADJCALLSTACKDOWN\0"
+ /* 3872 */ "G_SSUBO\0"
+ /* 3880 */ "G_USUBO\0"
+ /* 3888 */ "G_SADDO\0"
+ /* 3896 */ "G_UADDO\0"
+ /* 3904 */ "G_SMULO\0"
+ /* 3912 */ "G_UMULO\0"
+ /* 3920 */ "G_BZERO\0"
+ /* 3928 */ "STACKMAP\0"
+ /* 3937 */ "G_ATOMICRMW_UDEC_WRAP\0"
+ /* 3959 */ "G_ATOMICRMW_UINC_WRAP\0"
+ /* 3981 */ "G_BSWAP\0"
+ /* 3989 */ "G_SITOFP\0"
+ /* 3998 */ "G_UITOFP\0"
+ /* 4007 */ "G_FCMP\0"
+ /* 4014 */ "G_ICMP\0"
+ /* 4021 */ "PseudoUNIMP\0"
+ /* 4033 */ "CACOP\0"
+ /* 4039 */ "G_CTPOP\0"
+ /* 4047 */ "PATCHABLE_OP\0"
+ /* 4060 */ "FAULTING_OP\0"
+ /* 4072 */ "ADJCALLSTACKUP\0"
+ /* 4087 */ "PREALLOCATED_SETUP\0"
+ /* 4106 */ "G_FEXP\0"
+ /* 4113 */ "BEQ\0"
+ /* 4117 */ "DBAR\0"
+ /* 4122 */ "IBAR\0"
+ /* 4127 */ "G_BR\0"
+ /* 4132 */ "INLINEASM_BR\0"
+ /* 4145 */ "PseudoBR\0"
+ /* 4154 */ "G_BLOCK_ADDR\0"
+ /* 4167 */ "MEMBARRIER\0"
+ /* 4178 */ "PATCHABLE_FUNCTION_ENTER\0"
+ /* 4203 */ "G_READCYCLECOUNTER\0"
+ /* 4222 */ "G_READ_REGISTER\0"
+ /* 4238 */ "G_WRITE_REGISTER\0"
+ /* 4255 */ "PseudoLD_CFR\0"
+ /* 4268 */ "PseudoST_CFR\0"
+ /* 4281 */ "MOVCF2GR\0"
+ /* 4290 */ "MOVFCSR2GR\0"
+ /* 4301 */ "G_ASHR\0"
+ /* 4308 */ "G_FSHR\0"
+ /* 4315 */ "G_LSHR\0"
+ /* 4322 */ "LDDIR\0"
+ /* 4328 */ "TLBCLR\0"
+ /* 4335 */ "NOR\0"
+ /* 4339 */ "G_FFLOOR\0"
+ /* 4348 */ "G_BUILD_VECTOR\0"
+ /* 4363 */ "G_SHUFFLE_VECTOR\0"
+ /* 4380 */ "G_VECREDUCE_XOR\0"
+ /* 4396 */ "G_XOR\0"
+ /* 4402 */ "G_ATOMICRMW_XOR\0"
+ /* 4418 */ "G_VECREDUCE_OR\0"
+ /* 4433 */ "G_OR\0"
+ /* 4438 */ "G_ATOMICRMW_OR\0"
+ /* 4453 */ "MOVGR2FCSR\0"
+ /* 4464 */ "RDFCSR\0"
+ /* 4471 */ "WRFCSR\0"
+ /* 4478 */ "G_ROTR\0"
+ /* 4485 */ "G_INTTOPTR\0"
+ /* 4496 */ "TLBWR\0"
+ /* 4502 */ "CSRWR\0"
+ /* 4508 */ "G_FABS\0"
+ /* 4515 */ "PseudoLA_ABS\0"
+ /* 4528 */ "G_ABS\0"
+ /* 4534 */ "G_UNMERGE_VALUES\0"
+ /* 4551 */ "G_MERGE_VALUES\0"
+ /* 4566 */ "G_FCOS\0"
+ /* 4573 */ "G_CONCAT_VECTORS\0"
+ /* 4590 */ "COPY_TO_REGCLASS\0"
+ /* 4607 */ "G_IS_FPCLASS\0"
+ /* 4620 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
+ /* 4650 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
+ /* 4677 */ "FMINA_S\0"
+ /* 4685 */ "FMAXA_S\0"
+ /* 4693 */ "FSCALEB_S\0"
+ /* 4703 */ "FLOGB_S\0"
+ /* 4711 */ "FSUB_S\0"
+ /* 4718 */ "FMSUB_S\0"
+ /* 4726 */ "FNMSUB_S\0"
+ /* 4735 */ "FADD_S\0"
+ /* 4742 */ "FMADD_S\0"
+ /* 4750 */ "FNMADD_S\0"
+ /* 4759 */ "FLD_S\0"
+ /* 4765 */ "FCVT_D_S\0"
+ /* 4774 */ "FCMP_CLE_S\0"
+ /* 4785 */ "FLDLE_S\0"
+ /* 4793 */ "FCMP_SLE_S\0"
+ /* 4804 */ "FSTLE_S\0"
+ /* 4812 */ "FCMP_CULE_S\0"
+ /* 4824 */ "FCMP_SULE_S\0"
+ /* 4836 */ "FCMP_CNE_S\0"
+ /* 4847 */ "FCMP_SNE_S\0"
+ /* 4858 */ "FCMP_CUNE_S\0"
+ /* 4870 */ "FCMP_SUNE_S\0"
+ /* 4882 */ "FCMP_CAF_S\0"
+ /* 4893 */ "FCMP_SAF_S\0"
+ /* 4904 */ "MOVFR2CF_S\0"
+ /* 4915 */ "FNEG_S\0"
+ /* 4922 */ "FSEL_S\0"
+ /* 4929 */ "FMUL_S\0"
+ /* 4936 */ "FTINTRNE_L_S\0"
+ /* 4949 */ "FTINTRM_L_S\0"
+ /* 4961 */ "FTINTRP_L_S\0"
+ /* 4973 */ "FTINT_L_S\0"
+ /* 4983 */ "FTINTRZ_L_S\0"
+ /* 4995 */ "FCOPYSIGN_S\0"
+ /* 5007 */ "FMIN_S\0"
+ /* 5014 */ "FCMP_CUN_S\0"
+ /* 5025 */ "FCMP_SUN_S\0"
+ /* 5036 */ "FRECIP_S\0"
+ /* 5045 */ "FCMP_CEQ_S\0"
+ /* 5056 */ "FCMP_SEQ_S\0"
+ /* 5067 */ "FCMP_CUEQ_S\0"
+ /* 5079 */ "FCMP_SUEQ_S\0"
+ /* 5091 */ "MOVCF2FR_S\0"
+ /* 5102 */ "MOVFRH2GR_S\0"
+ /* 5114 */ "MOVFR2GR_S\0"
+ /* 5125 */ "FCMP_COR_S\0"
+ /* 5136 */ "FCMP_SOR_S\0"
+ /* 5147 */ "FABS_S\0"
+ /* 5154 */ "FCLASS_S\0"
+ /* 5163 */ "FLDGT_S\0"
+ /* 5171 */ "FSTGT_S\0"
+ /* 5179 */ "FCMP_CLT_S\0"
+ /* 5190 */ "FCMP_SLT_S\0"
+ /* 5201 */ "FCMP_CULT_S\0"
+ /* 5213 */ "FCMP_SULT_S\0"
+ /* 5225 */ "FRINT_S\0"
+ /* 5233 */ "FSQRT_S\0"
+ /* 5241 */ "FRSQRT_S\0"
+ /* 5250 */ "FST_S\0"
+ /* 5256 */ "FDIV_S\0"
+ /* 5263 */ "FMOV_S\0"
+ /* 5270 */ "FTINTRNE_W_S\0"
+ /* 5283 */ "FTINTRM_W_S\0"
+ /* 5295 */ "FTINTRP_W_S\0"
+ /* 5307 */ "FTINT_W_S\0"
+ /* 5317 */ "FTINTRZ_W_S\0"
+ /* 5329 */ "FMAX_S\0"
+ /* 5336 */ "FLDX_S\0"
+ /* 5343 */ "FSTX_S\0"
+ /* 5350 */ "G_SSUBSAT\0"
+ /* 5360 */ "G_USUBSAT\0"
+ /* 5370 */ "G_SADDSAT\0"
+ /* 5380 */ "G_UADDSAT\0"
+ /* 5390 */ "G_SSHLSAT\0"
+ /* 5400 */ "G_USHLSAT\0"
+ /* 5410 */ "G_SMULFIXSAT\0"
+ /* 5423 */ "G_UMULFIXSAT\0"
+ /* 5436 */ "G_SDIVFIXSAT\0"
+ /* 5449 */ "G_UDIVFIXSAT\0"
+ /* 5462 */ "G_EXTRACT\0"
+ /* 5472 */ "G_SELECT\0"
+ /* 5481 */ "G_BRINDIRECT\0"
+ /* 5494 */ "PATCHABLE_RET\0"
+ /* 5508 */ "PseudoRET\0"
+ /* 5518 */ "G_MEMSET\0"
+ /* 5527 */ "PATCHABLE_FUNCTION_EXIT\0"
+ /* 5551 */ "G_BRJT\0"
+ /* 5558 */ "BLT\0"
+ /* 5562 */ "G_EXTRACT_VECTOR_ELT\0"
+ /* 5583 */ "G_INSERT_VECTOR_ELT\0"
+ /* 5603 */ "SLT\0"
+ /* 5607 */ "G_FCONSTANT\0"
+ /* 5619 */ "G_CONSTANT\0"
+ /* 5630 */ "STATEPOINT\0"
+ /* 5641 */ "PATCHPOINT\0"
+ /* 5652 */ "G_PTRTOINT\0"
+ /* 5663 */ "G_FRINT\0"
+ /* 5671 */ "G_INTRINSIC_LRINT\0"
+ /* 5689 */ "G_FNEARBYINT\0"
+ /* 5702 */ "PseudoLA_GOT\0"
+ /* 5715 */ "G_VASTART\0"
+ /* 5725 */ "LIFETIME_START\0"
+ /* 5740 */ "G_INVOKE_REGION_START\0"
+ /* 5762 */ "G_INSERT\0"
+ /* 5771 */ "G_FSQRT\0"
+ /* 5779 */ "G_STRICT_FSQRT\0"
+ /* 5794 */ "G_BITCAST\0"
+ /* 5804 */ "G_ADDRSPACE_CAST\0"
+ /* 5821 */ "DBG_VALUE_LIST\0"
+ /* 5836 */ "G_FPEXT\0"
+ /* 5844 */ "G_SEXT\0"
+ /* 5851 */ "G_ASSERT_SEXT\0"
+ /* 5865 */ "G_ANYEXT\0"
+ /* 5874 */ "G_ZEXT\0"
+ /* 5881 */ "G_ASSERT_ZEXT\0"
+ /* 5895 */ "LD_BU\0"
+ /* 5901 */ "LDX_BU\0"
+ /* 5908 */ "AMMIN_DB_DU\0"
+ /* 5920 */ "AMMAX_DB_DU\0"
+ /* 5932 */ "MOD_DU\0"
+ /* 5939 */ "MULH_DU\0"
+ /* 5947 */ "AMMIN_DU\0"
+ /* 5956 */ "DIV_DU\0"
+ /* 5963 */ "AMMAX_DU\0"
+ /* 5972 */ "BGEU\0"
+ /* 5977 */ "LD_HU\0"
+ /* 5983 */ "LDX_HU\0"
+ /* 5990 */ "BLTU\0"
+ /* 5995 */ "SLTU\0"
+ /* 6000 */ "AMMIN_DB_WU\0"
+ /* 6012 */ "AMMAX_DB_WU\0"
+ /* 6024 */ "LD_WU\0"
+ /* 6030 */ "MOD_WU\0"
+ /* 6037 */ "MULW_D_WU\0"
+ /* 6047 */ "MULH_WU\0"
+ /* 6055 */ "ALSL_WU\0"
+ /* 6063 */ "AMMIN_WU\0"
+ /* 6072 */ "DIV_WU\0"
+ /* 6079 */ "AMMAX_WU\0"
+ /* 6088 */ "LDX_WU\0"
+ /* 6095 */ "G_FDIV\0"
+ /* 6102 */ "G_STRICT_FDIV\0"
+ /* 6116 */ "G_SDIV\0"
+ /* 6123 */ "G_UDIV\0"
+ /* 6130 */ "REVB_2W\0"
+ /* 6138 */ "REVH_2W\0"
+ /* 6146 */ "G_FPOW\0"
+ /* 6153 */ "SRA_W\0"
+ /* 6159 */ "AMADD_DB_W\0"
+ /* 6170 */ "AMAND_DB_W\0"
+ /* 6181 */ "AMMIN_DB_W\0"
+ /* 6192 */ "AMSWAP_DB_W\0"
+ /* 6204 */ "AMOR_DB_W\0"
+ /* 6214 */ "AMXOR_DB_W\0"
+ /* 6225 */ "AMMAX_DB_W\0"
+ /* 6236 */ "SUB_W\0"
+ /* 6242 */ "CRCC_W_B_W\0"
+ /* 6253 */ "CRC_W_B_W\0"
+ /* 6263 */ "SC_W\0"
+ /* 6268 */ "AMADD_W\0"
+ /* 6276 */ "LD_W\0"
+ /* 6281 */ "AMAND_W\0"
+ /* 6289 */ "MOD_W\0"
+ /* 6295 */ "IOCSRRD_W\0"
+ /* 6305 */ "FFINT_D_W\0"
+ /* 6315 */ "MULW_D_W\0"
+ /* 6324 */ "CRCC_W_D_W\0"
+ /* 6335 */ "CRC_W_D_W\0"
+ /* 6345 */ "LDLE_W\0"
+ /* 6352 */ "STLE_W\0"
+ /* 6359 */ "RDTIMEH_W\0"
+ /* 6369 */ "MULH_W\0"
+ /* 6376 */ "MOVGR2FRH_W\0"
+ /* 6388 */ "CRCC_W_H_W\0"
+ /* 6399 */ "CRC_W_H_W\0"
+ /* 6409 */ "LU12I_W\0"
+ /* 6417 */ "SRAI_W\0"
+ /* 6424 */ "ADDI_W\0"
+ /* 6431 */ "SLLI_W\0"
+ /* 6438 */ "SRLI_W\0"
+ /* 6445 */ "PseudoLI_W\0"
+ /* 6456 */ "ROTRI_W\0"
+ /* 6464 */ "BYTEPICK_W\0"
+ /* 6475 */ "BSTRPICK_W\0"
+ /* 6486 */ "RDTIMEL_W\0"
+ /* 6496 */ "SLL_W\0"
+ /* 6502 */ "SRL_W\0"
+ /* 6508 */ "ALSL_W\0"
+ /* 6515 */ "MUL_W\0"
+ /* 6521 */ "AMMIN_W\0"
+ /* 6529 */ "CLO_W\0"
+ /* 6535 */ "CTO_W\0"
+ /* 6541 */ "AMSWAP_W\0"
+ /* 6550 */ "MOVGR2FR_W\0"
+ /* 6561 */ "AMOR_W\0"
+ /* 6568 */ "AMXOR_W\0"
+ /* 6576 */ "ROTR_W\0"
+ /* 6583 */ "LDPTR_W\0"
+ /* 6591 */ "STPTR_W\0"
+ /* 6599 */ "IOCSRWR_W\0"
+ /* 6609 */ "BSTRINS_W\0"
+ /* 6619 */ "FFINT_S_W\0"
+ /* 6629 */ "LDGT_W\0"
+ /* 6636 */ "STGT_W\0"
+ /* 6643 */ "ST_W\0"
+ /* 6648 */ "BITREV_W\0"
+ /* 6657 */ "DIV_W\0"
+ /* 6663 */ "CRCC_W_W_W\0"
+ /* 6674 */ "CRC_W_W_W\0"
+ /* 6684 */ "AMMAX_W\0"
+ /* 6692 */ "LDX_W\0"
+ /* 6698 */ "STX_W\0"
+ /* 6704 */ "CLZ_W\0"
+ /* 6710 */ "CTZ_W\0"
+ /* 6716 */ "PseudoAtomicStoreW\0"
+ /* 6735 */ "G_VECREDUCE_FMAX\0"
+ /* 6752 */ "G_ATOMICRMW_FMAX\0"
+ /* 6769 */ "G_VECREDUCE_SMAX\0"
+ /* 6786 */ "G_SMAX\0"
+ /* 6793 */ "G_VECREDUCE_UMAX\0"
+ /* 6810 */ "G_UMAX\0"
+ /* 6817 */ "G_ATOMICRMW_UMAX\0"
+ /* 6834 */ "G_ATOMICRMW_MAX\0"
+ /* 6850 */ "PRELDX\0"
+ /* 6857 */ "G_FRAME_INDEX\0"
+ /* 6871 */ "G_SBFX\0"
+ /* 6878 */ "G_UBFX\0"
+ /* 6885 */ "G_SMULFIX\0"
+ /* 6895 */ "G_UMULFIX\0"
+ /* 6905 */ "G_SDIVFIX\0"
+ /* 6915 */ "G_UDIVFIX\0"
+ /* 6925 */ "G_MEMCPY\0"
+ /* 6934 */ "COPY\0"
+ /* 6939 */ "BNEZ\0"
+ /* 6944 */ "BCNEZ\0"
+ /* 6950 */ "MASKNEZ\0"
+ /* 6958 */ "G_CTLZ\0"
+ /* 6965 */ "BEQZ\0"
+ /* 6970 */ "BCEQZ\0"
+ /* 6976 */ "MASKEQZ\0"
+ /* 6984 */ "G_CTTZ\0"
+ /* 6991 */ "PseudoTAILIndirect\0"
+ /* 7010 */ "PseudoCALLIndirect\0"
+};
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+extern const unsigned LoongArchInstrNameIndices[] = {
+ 3095U, 3602U, 4132U, 3830U, 3184U, 3165U, 3193U, 3429U,
+ 2785U, 2800U, 2751U, 2827U, 4590U, 2644U, 5821U, 2764U,
+ 3091U, 3174U, 2323U, 6934U, 2545U, 5725U, 1081U, 2274U,
+ 2311U, 3928U, 3398U, 5641U, 1178U, 4087U, 2905U, 5630U,
+ 2588U, 4060U, 4047U, 4178U, 5494U, 5527U, 3314U, 3377U,
+ 3350U, 3210U, 4167U, 5851U, 5881U, 3681U, 956U, 589U,
+ 3521U, 6116U, 6123U, 3568U, 3575U, 3582U, 3592U, 1059U,
+ 4433U, 4396U, 2749U, 3093U, 6857U, 2654U, 5462U, 4534U,
+ 5762U, 4551U, 4348U, 737U, 4573U, 5652U, 4485U, 5794U,
+ 2679U, 1152U, 711U, 1134U, 5671U, 3659U, 4203U, 857U,
+ 801U, 831U, 842U, 782U, 812U, 2617U, 2601U, 4620U,
+ 2848U, 2873U, 972U, 595U, 1065U, 1026U, 4438U, 4402U,
+ 6834U, 3807U, 6817U, 3790U, 923U, 572U, 6752U, 3725U,
+ 3959U, 3937U, 2303U, 1106U, 5481U, 5740U, 689U, 4650U,
+ 5865U, 729U, 5619U, 5607U, 5715U, 2897U, 5844U, 2814U,
+ 5874U, 3252U, 4315U, 4301U, 3245U, 4308U, 4478U, 3439U,
+ 4014U, 4007U, 5472U, 3896U, 2344U, 3880U, 2295U, 3888U,
+ 2336U, 3872U, 2287U, 3912U, 3904U, 2954U, 2946U, 5380U,
+ 5370U, 5360U, 5350U, 5400U, 5390U, 6885U, 6895U, 5410U,
+ 5423U, 6905U, 6915U, 5436U, 5449U, 881U, 551U, 3463U,
+ 505U, 775U, 6095U, 3547U, 6146U, 3133U, 4106U, 430U,
+ 2890U, 422U, 0U, 2778U, 5836U, 701U, 3104U, 3118U,
+ 3989U, 3998U, 4508U, 3696U, 4607U, 2688U, 3634U, 3644U,
+ 2352U, 2367U, 3612U, 3623U, 962U, 3147U, 3759U, 6786U,
+ 3783U, 6810U, 4528U, 1125U, 1115U, 4127U, 5551U, 5583U,
+ 5562U, 4363U, 6984U, 2731U, 6958U, 2713U, 4039U, 3981U,
+ 2625U, 3298U, 4566U, 3823U, 5771U, 4339U, 5663U, 5689U,
+ 5804U, 4154U, 2527U, 758U, 909U, 558U, 3491U, 6102U,
+ 3554U, 511U, 5779U, 4222U, 4238U, 6925U, 2572U, 2669U,
+ 5518U, 3920U, 888U, 3470U, 864U, 3446U, 6735U, 3708U,
+ 940U, 3505U, 1043U, 4418U, 4380U, 6769U, 3742U, 6793U,
+ 3766U, 6871U, 6878U, 3855U, 4072U, 87U, 109U, 160U,
+ 466U, 322U, 37U, 343U, 2255U, 6716U, 303U, 4145U,
+ 1094U, 3258U, 3410U, 7010U, 205U, 489U, 3334U, 3271U,
+ 4515U, 2473U, 5702U, 2492U, 3230U, 2452U, 988U, 2386U,
+ 2511U, 2430U, 1010U, 2408U, 2552U, 4255U, 1645U, 6445U,
+ 59U, 394U, 250U, 131U, 9U, 365U, 221U, 278U,
+ 183U, 5508U, 4268U, 3287U, 6991U, 4021U, 4464U, 4471U,
+ 1624U, 6424U, 1607U, 1361U, 6270U, 1705U, 6508U, 6055U,
+ 1367U, 1229U, 6159U, 6268U, 1398U, 1240U, 6170U, 6281U,
+ 2221U, 1295U, 5920U, 6225U, 6012U, 5963U, 6684U, 6079U,
+ 1797U, 1251U, 5908U, 6181U, 6000U, 5947U, 6521U, 6063U,
+ 1936U, 1274U, 6204U, 6561U, 1839U, 1262U, 6192U, 6541U,
+ 1954U, 1284U, 6214U, 6568U, 1039U, 3086U, 3654U, 2038U,
+ 1452U, 532U, 6970U, 6944U, 4113U, 6965U, 2382U, 5972U,
+ 524U, 534U, 2132U, 6648U, 3157U, 5558U, 5990U, 2568U,
+ 6939U, 3141U, 2002U, 6609U, 1675U, 6475U, 1664U, 6464U,
+ 4033U, 1827U, 6529U, 2243U, 6704U, 2841U, 6242U, 6324U,
+ 6388U, 6663U, 6253U, 6335U, 6399U, 6674U, 1201U, 4502U,
+ 2865U, 1833U, 6535U, 2249U, 6710U, 4117U, 3160U, 2142U,
+ 5956U, 6657U, 6072U, 3850U, 669U, 3029U, 1995U, 5147U,
+ 1360U, 4735U, 2012U, 5154U, 1548U, 4882U, 1857U, 5045U,
+ 1422U, 4774U, 2055U, 5179U, 1502U, 4836U, 1925U, 5125U,
+ 1879U, 5067U, 1469U, 4812U, 2077U, 5201U, 1524U, 4858U,
+ 1805U, 5014U, 1559U, 4893U, 1868U, 5056U, 1441U, 4793U,
+ 2066U, 5190U, 1513U, 4847U, 1943U, 5136U, 1891U, 5079U,
+ 1481U, 4824U, 2089U, 5213U, 1536U, 4870U, 1816U, 5025U,
+ 1778U, 4995U, 4765U, 2021U, 2141U, 5256U, 3527U, 6305U,
+ 3537U, 6619U, 2030U, 5163U, 1433U, 4785U, 2229U, 5336U,
+ 1392U, 4759U, 1316U, 4703U, 1375U, 4742U, 1221U, 4685U,
+ 2214U, 5329U, 1207U, 4677U, 1790U, 5007U, 2148U, 5263U,
+ 1331U, 4718U, 1712U, 4929U, 1570U, 4915U, 1383U, 4750U,
+ 1339U, 4726U, 1848U, 5036U, 2101U, 5225U, 2117U, 5241U,
+ 1306U, 4693U, 1686U, 4922U, 2109U, 5233U, 2047U, 5171U,
+ 1461U, 4804U, 2236U, 5343U, 2126U, 5250U, 1324U, 4711U,
+ 1732U, 4949U, 2168U, 5283U, 1719U, 4936U, 2155U, 5270U,
+ 1744U, 4961U, 2180U, 5295U, 1766U, 4983U, 2202U, 5317U,
+ 1756U, 4973U, 2192U, 5307U, 4122U, 2540U, 544U, 616U,
+ 1412U, 2976U, 6295U, 640U, 1985U, 3000U, 6599U, 3434U,
+ 4322U, 650U, 2031U, 3010U, 6629U, 626U, 1434U, 2986U,
+ 6345U, 2638U, 1969U, 6583U, 677U, 5901U, 2230U, 3037U,
+ 5983U, 6692U, 6088U, 611U, 5895U, 1393U, 2971U, 5977U,
+ 6276U, 6024U, 1694U, 6497U, 6409U, 1591U, 1599U, 6976U,
+ 6950U, 1406U, 5932U, 6289U, 6030U, 5091U, 4281U, 4290U,
+ 4904U, 1914U, 5114U, 438U, 5102U, 2704U, 4453U, 6376U,
+ 1903U, 6550U, 452U, 1577U, 5939U, 6369U, 6047U, 6315U,
+ 6037U, 1713U, 6515U, 4335U, 4336U, 3100U, 3846U, 3079U,
+ 3059U, 3069U, 3049U, 1004U, 6850U, 6359U, 6486U, 1493U,
+ 2922U, 6130U, 2930U, 1348U, 6138U, 1584U, 1656U, 6456U,
+ 1962U, 6576U, 1355U, 6263U, 1631U, 6431U, 1693U, 6496U,
+ 5603U, 3113U, 5995U, 3127U, 1617U, 6417U, 1215U, 6153U,
+ 1638U, 6438U, 1699U, 6502U, 657U, 2048U, 3017U, 6636U,
+ 633U, 1462U, 2993U, 6352U, 1977U, 6591U, 683U, 2237U,
+ 3043U, 6698U, 664U, 2127U, 3024U, 6643U, 1325U, 6236U,
+ 3306U, 4328U, 3421U, 2962U, 1195U, 2938U, 4496U, 4392U,
+ 3099U,
+};
+
+static inline void InitLoongArchMCInstrInfo(MCInstrInfo *II) {
+ II->InitMCInstrInfo(LoongArchInsts, LoongArchInstrNameIndices, LoongArchInstrNameData, nullptr, nullptr, 681);
+}
+
+} // end namespace llvm
+#endif // GET_INSTRINFO_MC_DESC
+
+#ifdef GET_INSTRINFO_HEADER
+#undef GET_INSTRINFO_HEADER
+namespace llvm {
+struct LoongArchGenInstrInfo : public TargetInstrInfo {
+ explicit LoongArchGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
+ ~LoongArchGenInstrInfo() override = default;
+
+};
+} // end namespace llvm
+#endif // GET_INSTRINFO_HEADER
+
+#ifdef GET_INSTRINFO_HELPER_DECLS
+#undef GET_INSTRINFO_HELPER_DECLS
+
+
+#endif // GET_INSTRINFO_HELPER_DECLS
+
+#ifdef GET_INSTRINFO_HELPERS
+#undef GET_INSTRINFO_HELPERS
+
+#endif // GET_INSTRINFO_HELPERS
+
+#ifdef GET_INSTRINFO_CTOR_DTOR
+#undef GET_INSTRINFO_CTOR_DTOR
+namespace llvm {
+extern const MCInstrDesc LoongArchInsts[];
+extern const unsigned LoongArchInstrNameIndices[];
+extern const char LoongArchInstrNameData[];
+LoongArchGenInstrInfo::LoongArchGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
+ : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
+ InitMCInstrInfo(LoongArchInsts, LoongArchInstrNameIndices, LoongArchInstrNameData, nullptr, nullptr, 681);
+}
+} // end namespace llvm
+#endif // GET_INSTRINFO_CTOR_DTOR
+
+#ifdef GET_INSTRINFO_OPERAND_ENUM
+#undef GET_INSTRINFO_OPERAND_ENUM
+namespace llvm {
+namespace LoongArch {
+namespace OpName {
+enum {
+ OPERAND_LAST
+};
+} // end namespace OpName
+} // end namespace LoongArch
+} // end namespace llvm
+#endif //GET_INSTRINFO_OPERAND_ENUM
+
+#ifdef GET_INSTRINFO_NAMED_OPS
+#undef GET_INSTRINFO_NAMED_OPS
+namespace llvm {
+namespace LoongArch {
+LLVM_READONLY
+int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
+ return -1;
+}
+} // end namespace LoongArch
+} // end namespace llvm
+#endif //GET_INSTRINFO_NAMED_OPS
+
+#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
+#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
+namespace llvm {
+namespace LoongArch {
+namespace OpTypes {
+enum OperandType {
+ bare_symbol = 0,
+ f32imm = 1,
+ f64imm = 2,
+ grlenimm = 3,
+ i16imm = 4,
+ i1imm = 5,
+ i32imm = 6,
+ i64imm = 7,
+ i8imm = 8,
+ imm32 = 9,
+ ptype0 = 10,
+ ptype1 = 11,
+ ptype2 = 12,
+ ptype3 = 13,
+ ptype4 = 14,
+ ptype5 = 15,
+ simm12 = 16,
+ simm12_addlike = 17,
+ simm12_lu52id = 18,
+ simm14_lsl2 = 19,
+ simm16 = 20,
+ simm16_lsl2 = 21,
+ simm16_lsl2_br = 22,
+ simm20 = 23,
+ simm20_lu12iw = 24,
+ simm20_lu32id = 25,
+ simm20_pcalau12i = 26,
+ simm21_lsl2 = 27,
+ simm26_b = 28,
+ simm26_symbol = 29,
+ type0 = 30,
+ type1 = 31,
+ type2 = 32,
+ type3 = 33,
+ type4 = 34,
+ type5 = 35,
+ uimm12 = 36,
+ uimm12_ori = 37,
+ uimm14 = 38,
+ uimm15 = 39,
+ uimm2 = 40,
+ uimm2_plus1 = 41,
+ uimm3 = 42,
+ uimm5 = 43,
+ uimm6 = 44,
+ uimm8 = 45,
+ untyped_imm_0 = 46,
+ GPRMemAtomic = 47,
+ CFR = 48,
+ FCSR = 49,
+ FPR32 = 50,
+ FPR64 = 51,
+ GPR = 52,
+ GPRT = 53,
+ OPERAND_TYPE_LIST_END
+};
+} // end namespace OpTypes
+} // end namespace LoongArch
+} // end namespace llvm
+#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
+
+#ifdef GET_INSTRINFO_OPERAND_TYPE
+#undef GET_INSTRINFO_OPERAND_TYPE
+namespace llvm {
+namespace LoongArch {
+LLVM_READONLY
+static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
+ const uint16_t Offsets[] = {
+ /* PHI */
+ 0,
+ /* INLINEASM */
+ 1,
+ /* INLINEASM_BR */
+ 1,
+ /* CFI_INSTRUCTION */
+ 1,
+ /* EH_LABEL */
+ 2,
+ /* GC_LABEL */
+ 3,
+ /* ANNOTATION_LABEL */
+ 4,
+ /* KILL */
+ 5,
+ /* EXTRACT_SUBREG */
+ 5,
+ /* INSERT_SUBREG */
+ 8,
+ /* IMPLICIT_DEF */
+ 12,
+ /* SUBREG_TO_REG */
+ 13,
+ /* COPY_TO_REGCLASS */
+ 17,
+ /* DBG_VALUE */
+ 20,
+ /* DBG_VALUE_LIST */
+ 20,
+ /* DBG_INSTR_REF */
+ 20,
+ /* DBG_PHI */
+ 20,
+ /* DBG_LABEL */
+ 20,
+ /* REG_SEQUENCE */
+ 21,
+ /* COPY */
+ 23,
+ /* BUNDLE */
+ 25,
+ /* LIFETIME_START */
+ 25,
+ /* LIFETIME_END */
+ 26,
+ /* PSEUDO_PROBE */
+ 27,
+ /* ARITH_FENCE */
+ 31,
+ /* STACKMAP */
+ 33,
+ /* FENTRY_CALL */
+ 35,
+ /* PATCHPOINT */
+ 35,
+ /* LOAD_STACK_GUARD */
+ 41,
+ /* PREALLOCATED_SETUP */
+ 42,
+ /* PREALLOCATED_ARG */
+ 43,
+ /* STATEPOINT */
+ 46,
+ /* LOCAL_ESCAPE */
+ 46,
+ /* FAULTING_OP */
+ 48,
+ /* PATCHABLE_OP */
+ 49,
+ /* PATCHABLE_FUNCTION_ENTER */
+ 49,
+ /* PATCHABLE_RET */
+ 49,
+ /* PATCHABLE_FUNCTION_EXIT */
+ 49,
+ /* PATCHABLE_TAIL_CALL */
+ 49,
+ /* PATCHABLE_EVENT_CALL */
+ 49,
+ /* PATCHABLE_TYPED_EVENT_CALL */
+ 51,
+ /* ICALL_BRANCH_FUNNEL */
+ 54,
+ /* MEMBARRIER */
+ 54,
+ /* G_ASSERT_SEXT */
+ 54,
+ /* G_ASSERT_ZEXT */
+ 57,
+ /* G_ASSERT_ALIGN */
+ 60,
+ /* G_ADD */
+ 63,
+ /* G_SUB */
+ 66,
+ /* G_MUL */
+ 69,
+ /* G_SDIV */
+ 72,
+ /* G_UDIV */
+ 75,
+ /* G_SREM */
+ 78,
+ /* G_UREM */
+ 81,
+ /* G_SDIVREM */
+ 84,
+ /* G_UDIVREM */
+ 88,
+ /* G_AND */
+ 92,
+ /* G_OR */
+ 95,
+ /* G_XOR */
+ 98,
+ /* G_IMPLICIT_DEF */
+ 101,
+ /* G_PHI */
+ 102,
+ /* G_FRAME_INDEX */
+ 103,
+ /* G_GLOBAL_VALUE */
+ 105,
+ /* G_EXTRACT */
+ 107,
+ /* G_UNMERGE_VALUES */
+ 110,
+ /* G_INSERT */
+ 112,
+ /* G_MERGE_VALUES */
+ 116,
+ /* G_BUILD_VECTOR */
+ 118,
+ /* G_BUILD_VECTOR_TRUNC */
+ 120,
+ /* G_CONCAT_VECTORS */
+ 122,
+ /* G_PTRTOINT */
+ 124,
+ /* G_INTTOPTR */
+ 126,
+ /* G_BITCAST */
+ 128,
+ /* G_FREEZE */
+ 130,
+ /* G_INTRINSIC_FPTRUNC_ROUND */
+ 132,
+ /* G_INTRINSIC_TRUNC */
+ 135,
+ /* G_INTRINSIC_ROUND */
+ 137,
+ /* G_INTRINSIC_LRINT */
+ 139,
+ /* G_INTRINSIC_ROUNDEVEN */
+ 141,
+ /* G_READCYCLECOUNTER */
+ 143,
+ /* G_LOAD */
+ 144,
+ /* G_SEXTLOAD */
+ 146,
+ /* G_ZEXTLOAD */
+ 148,
+ /* G_INDEXED_LOAD */
+ 150,
+ /* G_INDEXED_SEXTLOAD */
+ 155,
+ /* G_INDEXED_ZEXTLOAD */
+ 160,
+ /* G_STORE */
+ 165,
+ /* G_INDEXED_STORE */
+ 167,
+ /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
+ 172,
+ /* G_ATOMIC_CMPXCHG */
+ 177,
+ /* G_ATOMICRMW_XCHG */
+ 181,
+ /* G_ATOMICRMW_ADD */
+ 184,
+ /* G_ATOMICRMW_SUB */
+ 187,
+ /* G_ATOMICRMW_AND */
+ 190,
+ /* G_ATOMICRMW_NAND */
+ 193,
+ /* G_ATOMICRMW_OR */
+ 196,
+ /* G_ATOMICRMW_XOR */
+ 199,
+ /* G_ATOMICRMW_MAX */
+ 202,
+ /* G_ATOMICRMW_MIN */
+ 205,
+ /* G_ATOMICRMW_UMAX */
+ 208,
+ /* G_ATOMICRMW_UMIN */
+ 211,
+ /* G_ATOMICRMW_FADD */
+ 214,
+ /* G_ATOMICRMW_FSUB */
+ 217,
+ /* G_ATOMICRMW_FMAX */
+ 220,
+ /* G_ATOMICRMW_FMIN */
+ 223,
+ /* G_ATOMICRMW_UINC_WRAP */
+ 226,
+ /* G_ATOMICRMW_UDEC_WRAP */
+ 229,
+ /* G_FENCE */
+ 232,
+ /* G_BRCOND */
+ 234,
+ /* G_BRINDIRECT */
+ 236,
+ /* G_INVOKE_REGION_START */
+ 237,
+ /* G_INTRINSIC */
+ 237,
+ /* G_INTRINSIC_W_SIDE_EFFECTS */
+ 238,
+ /* G_ANYEXT */
+ 239,
+ /* G_TRUNC */
+ 241,
+ /* G_CONSTANT */
+ 243,
+ /* G_FCONSTANT */
+ 245,
+ /* G_VASTART */
+ 247,
+ /* G_VAARG */
+ 248,
+ /* G_SEXT */
+ 251,
+ /* G_SEXT_INREG */
+ 253,
+ /* G_ZEXT */
+ 256,
+ /* G_SHL */
+ 258,
+ /* G_LSHR */
+ 261,
+ /* G_ASHR */
+ 264,
+ /* G_FSHL */
+ 267,
+ /* G_FSHR */
+ 271,
+ /* G_ROTR */
+ 275,
+ /* G_ROTL */
+ 278,
+ /* G_ICMP */
+ 281,
+ /* G_FCMP */
+ 285,
+ /* G_SELECT */
+ 289,
+ /* G_UADDO */
+ 293,
+ /* G_UADDE */
+ 297,
+ /* G_USUBO */
+ 302,
+ /* G_USUBE */
+ 306,
+ /* G_SADDO */
+ 311,
+ /* G_SADDE */
+ 315,
+ /* G_SSUBO */
+ 320,
+ /* G_SSUBE */
+ 324,
+ /* G_UMULO */
+ 329,
+ /* G_SMULO */
+ 333,
+ /* G_UMULH */
+ 337,
+ /* G_SMULH */
+ 340,
+ /* G_UADDSAT */
+ 343,
+ /* G_SADDSAT */
+ 346,
+ /* G_USUBSAT */
+ 349,
+ /* G_SSUBSAT */
+ 352,
+ /* G_USHLSAT */
+ 355,
+ /* G_SSHLSAT */
+ 358,
+ /* G_SMULFIX */
+ 361,
+ /* G_UMULFIX */
+ 365,
+ /* G_SMULFIXSAT */
+ 369,
+ /* G_UMULFIXSAT */
+ 373,
+ /* G_SDIVFIX */
+ 377,
+ /* G_UDIVFIX */
+ 381,
+ /* G_SDIVFIXSAT */
+ 385,
+ /* G_UDIVFIXSAT */
+ 389,
+ /* G_FADD */
+ 393,
+ /* G_FSUB */
+ 396,
+ /* G_FMUL */
+ 399,
+ /* G_FMA */
+ 402,
+ /* G_FMAD */
+ 406,
+ /* G_FDIV */
+ 410,
+ /* G_FREM */
+ 413,
+ /* G_FPOW */
+ 416,
+ /* G_FPOWI */
+ 419,
+ /* G_FEXP */
+ 422,
+ /* G_FEXP2 */
+ 424,
+ /* G_FLOG */
+ 426,
+ /* G_FLOG2 */
+ 428,
+ /* G_FLOG10 */
+ 430,
+ /* G_FNEG */
+ 432,
+ /* G_FPEXT */
+ 434,
+ /* G_FPTRUNC */
+ 436,
+ /* G_FPTOSI */
+ 438,
+ /* G_FPTOUI */
+ 440,
+ /* G_SITOFP */
+ 442,
+ /* G_UITOFP */
+ 444,
+ /* G_FABS */
+ 446,
+ /* G_FCOPYSIGN */
+ 448,
+ /* G_IS_FPCLASS */
+ 451,
+ /* G_FCANONICALIZE */
+ 454,
+ /* G_FMINNUM */
+ 456,
+ /* G_FMAXNUM */
+ 459,
+ /* G_FMINNUM_IEEE */
+ 462,
+ /* G_FMAXNUM_IEEE */
+ 465,
+ /* G_FMINIMUM */
+ 468,
+ /* G_FMAXIMUM */
+ 471,
+ /* G_PTR_ADD */
+ 474,
+ /* G_PTRMASK */
+ 477,
+ /* G_SMIN */
+ 480,
+ /* G_SMAX */
+ 483,
+ /* G_UMIN */
+ 486,
+ /* G_UMAX */
+ 489,
+ /* G_ABS */
+ 492,
+ /* G_LROUND */
+ 494,
+ /* G_LLROUND */
+ 496,
+ /* G_BR */
+ 498,
+ /* G_BRJT */
+ 499,
+ /* G_INSERT_VECTOR_ELT */
+ 502,
+ /* G_EXTRACT_VECTOR_ELT */
+ 506,
+ /* G_SHUFFLE_VECTOR */
+ 509,
+ /* G_CTTZ */
+ 513,
+ /* G_CTTZ_ZERO_UNDEF */
+ 515,
+ /* G_CTLZ */
+ 517,
+ /* G_CTLZ_ZERO_UNDEF */
+ 519,
+ /* G_CTPOP */
+ 521,
+ /* G_BSWAP */
+ 523,
+ /* G_BITREVERSE */
+ 525,
+ /* G_FCEIL */
+ 527,
+ /* G_FCOS */
+ 529,
+ /* G_FSIN */
+ 531,
+ /* G_FSQRT */
+ 533,
+ /* G_FFLOOR */
+ 535,
+ /* G_FRINT */
+ 537,
+ /* G_FNEARBYINT */
+ 539,
+ /* G_ADDRSPACE_CAST */
+ 541,
+ /* G_BLOCK_ADDR */
+ 543,
+ /* G_JUMP_TABLE */
+ 545,
+ /* G_DYN_STACKALLOC */
+ 547,
+ /* G_STRICT_FADD */
+ 550,
+ /* G_STRICT_FSUB */
+ 553,
+ /* G_STRICT_FMUL */
+ 556,
+ /* G_STRICT_FDIV */
+ 559,
+ /* G_STRICT_FREM */
+ 562,
+ /* G_STRICT_FMA */
+ 565,
+ /* G_STRICT_FSQRT */
+ 569,
+ /* G_READ_REGISTER */
+ 571,
+ /* G_WRITE_REGISTER */
+ 573,
+ /* G_MEMCPY */
+ 575,
+ /* G_MEMCPY_INLINE */
+ 579,
+ /* G_MEMMOVE */
+ 582,
+ /* G_MEMSET */
+ 586,
+ /* G_BZERO */
+ 590,
+ /* G_VECREDUCE_SEQ_FADD */
+ 593,
+ /* G_VECREDUCE_SEQ_FMUL */
+ 596,
+ /* G_VECREDUCE_FADD */
+ 599,
+ /* G_VECREDUCE_FMUL */
+ 601,
+ /* G_VECREDUCE_FMAX */
+ 603,
+ /* G_VECREDUCE_FMIN */
+ 605,
+ /* G_VECREDUCE_ADD */
+ 607,
+ /* G_VECREDUCE_MUL */
+ 609,
+ /* G_VECREDUCE_AND */
+ 611,
+ /* G_VECREDUCE_OR */
+ 613,
+ /* G_VECREDUCE_XOR */
+ 615,
+ /* G_VECREDUCE_SMAX */
+ 617,
+ /* G_VECREDUCE_SMIN */
+ 619,
+ /* G_VECREDUCE_UMAX */
+ 621,
+ /* G_VECREDUCE_UMIN */
+ 623,
+ /* G_SBFX */
+ 625,
+ /* G_UBFX */
+ 629,
+ /* ADJCALLSTACKDOWN */
+ 633,
+ /* ADJCALLSTACKUP */
+ 635,
+ /* PseudoAtomicLoadAdd32 */
+ 637,
+ /* PseudoAtomicLoadAnd32 */
+ 642,
+ /* PseudoAtomicLoadNand32 */
+ 647,
+ /* PseudoAtomicLoadNand64 */
+ 652,
+ /* PseudoAtomicLoadOr32 */
+ 657,
+ /* PseudoAtomicLoadSub32 */
+ 662,
+ /* PseudoAtomicLoadXor32 */
+ 667,
+ /* PseudoAtomicStoreD */
+ 672,
+ /* PseudoAtomicStoreW */
+ 675,
+ /* PseudoAtomicSwap32 */
+ 678,
+ /* PseudoBR */
+ 683,
+ /* PseudoBRIND */
+ 684,
+ /* PseudoB_TAIL */
+ 686,
+ /* PseudoCALL */
+ 687,
+ /* PseudoCALLIndirect */
+ 688,
+ /* PseudoCmpXchg32 */
+ 689,
+ /* PseudoCmpXchg64 */
+ 694,
+ /* PseudoJIRL_CALL */
+ 699,
+ /* PseudoJIRL_TAIL */
+ 701,
+ /* PseudoLA_ABS */
+ 703,
+ /* PseudoLA_ABS_LARGE */
+ 705,
+ /* PseudoLA_GOT */
+ 708,
+ /* PseudoLA_GOT_LARGE */
+ 710,
+ /* PseudoLA_PCREL */
+ 713,
+ /* PseudoLA_PCREL_LARGE */
+ 715,
+ /* PseudoLA_TLS_GD */
+ 718,
+ /* PseudoLA_TLS_GD_LARGE */
+ 720,
+ /* PseudoLA_TLS_IE */
+ 723,
+ /* PseudoLA_TLS_IE_LARGE */
+ 725,
+ /* PseudoLA_TLS_LD */
+ 728,
+ /* PseudoLA_TLS_LD_LARGE */
+ 730,
+ /* PseudoLA_TLS_LE */
+ 733,
+ /* PseudoLD_CFR */
+ 735,
+ /* PseudoLI_D */
+ 738,
+ /* PseudoLI_W */
+ 740,
+ /* PseudoMaskedAtomicLoadAdd32 */
+ 742,
+ /* PseudoMaskedAtomicLoadMax32 */
+ 748,
+ /* PseudoMaskedAtomicLoadMin32 */
+ 756,
+ /* PseudoMaskedAtomicLoadNand32 */
+ 764,
+ /* PseudoMaskedAtomicLoadSub32 */
+ 770,
+ /* PseudoMaskedAtomicLoadUMax32 */
+ 776,
+ /* PseudoMaskedAtomicLoadUMin32 */
+ 783,
+ /* PseudoMaskedAtomicSwap32 */
+ 790,
+ /* PseudoMaskedCmpXchg32 */
+ 796,
+ /* PseudoRET */
+ 803,
+ /* PseudoST_CFR */
+ 803,
+ /* PseudoTAIL */
+ 806,
+ /* PseudoTAILIndirect */
+ 807,
+ /* PseudoUNIMP */
+ 808,
+ /* RDFCSR */
+ 808,
+ /* WRFCSR */
+ 810,
+ /* ADDI_D */
+ 812,
+ /* ADDI_W */
+ 815,
+ /* ADDU16I_D */
+ 818,
+ /* ADD_D */
+ 821,
+ /* ADD_W */
+ 824,
+ /* ALSL_D */
+ 827,
+ /* ALSL_W */
+ 831,
+ /* ALSL_WU */
+ 835,
+ /* AMADD_D */
+ 839,
+ /* AMADD_DB_D */
+ 842,
+ /* AMADD_DB_W */
+ 845,
+ /* AMADD_W */
+ 848,
+ /* AMAND_D */
+ 851,
+ /* AMAND_DB_D */
+ 854,
+ /* AMAND_DB_W */
+ 857,
+ /* AMAND_W */
+ 860,
+ /* AMMAX_D */
+ 863,
+ /* AMMAX_DB_D */
+ 866,
+ /* AMMAX_DB_DU */
+ 869,
+ /* AMMAX_DB_W */
+ 872,
+ /* AMMAX_DB_WU */
+ 875,
+ /* AMMAX_DU */
+ 878,
+ /* AMMAX_W */
+ 881,
+ /* AMMAX_WU */
+ 884,
+ /* AMMIN_D */
+ 887,
+ /* AMMIN_DB_D */
+ 890,
+ /* AMMIN_DB_DU */
+ 893,
+ /* AMMIN_DB_W */
+ 896,
+ /* AMMIN_DB_WU */
+ 899,
+ /* AMMIN_DU */
+ 902,
+ /* AMMIN_W */
+ 905,
+ /* AMMIN_WU */
+ 908,
+ /* AMOR_D */
+ 911,
+ /* AMOR_DB_D */
+ 914,
+ /* AMOR_DB_W */
+ 917,
+ /* AMOR_W */
+ 920,
+ /* AMSWAP_D */
+ 923,
+ /* AMSWAP_DB_D */
+ 926,
+ /* AMSWAP_DB_W */
+ 929,
+ /* AMSWAP_W */
+ 932,
+ /* AMXOR_D */
+ 935,
+ /* AMXOR_DB_D */
+ 938,
+ /* AMXOR_DB_W */
+ 941,
+ /* AMXOR_W */
+ 944,
+ /* AND */
+ 947,
+ /* ANDI */
+ 950,
+ /* ANDN */
+ 953,
+ /* ASRTGT_D */
+ 956,
+ /* ASRTLE_D */
+ 958,
+ /* B */
+ 960,
+ /* BCEQZ */
+ 961,
+ /* BCNEZ */
+ 963,
+ /* BEQ */
+ 965,
+ /* BEQZ */
+ 968,
+ /* BGE */
+ 970,
+ /* BGEU */
+ 973,
+ /* BITREV_4B */
+ 976,
+ /* BITREV_8B */
+ 978,
+ /* BITREV_D */
+ 980,
+ /* BITREV_W */
+ 982,
+ /* BL */
+ 984,
+ /* BLT */
+ 985,
+ /* BLTU */
+ 988,
+ /* BNE */
+ 991,
+ /* BNEZ */
+ 994,
+ /* BREAK */
+ 996,
+ /* BSTRINS_D */
+ 997,
+ /* BSTRINS_W */
+ 1002,
+ /* BSTRPICK_D */
+ 1007,
+ /* BSTRPICK_W */
+ 1011,
+ /* BYTEPICK_D */
+ 1015,
+ /* BYTEPICK_W */
+ 1019,
+ /* CACOP */
+ 1023,
+ /* CLO_D */
+ 1026,
+ /* CLO_W */
+ 1028,
+ /* CLZ_D */
+ 1030,
+ /* CLZ_W */
+ 1032,
+ /* CPUCFG */
+ 1034,
+ /* CRCC_W_B_W */
+ 1036,
+ /* CRCC_W_D_W */
+ 1039,
+ /* CRCC_W_H_W */
+ 1042,
+ /* CRCC_W_W_W */
+ 1045,
+ /* CRC_W_B_W */
+ 1048,
+ /* CRC_W_D_W */
+ 1051,
+ /* CRC_W_H_W */
+ 1054,
+ /* CRC_W_W_W */
+ 1057,
+ /* CSRRD */
+ 1060,
+ /* CSRWR */
+ 1062,
+ /* CSRXCHG */
+ 1065,
+ /* CTO_D */
+ 1069,
+ /* CTO_W */
+ 1071,
+ /* CTZ_D */
+ 1073,
+ /* CTZ_W */
+ 1075,
+ /* DBAR */
+ 1077,
+ /* DBCL */
+ 1078,
+ /* DIV_D */
+ 1079,
+ /* DIV_DU */
+ 1082,
+ /* DIV_W */
+ 1085,
+ /* DIV_WU */
+ 1088,
+ /* ERTN */
+ 1091,
+ /* EXT_W_B */
+ 1091,
+ /* EXT_W_H */
+ 1093,
+ /* FABS_D */
+ 1095,
+ /* FABS_S */
+ 1097,
+ /* FADD_D */
+ 1099,
+ /* FADD_S */
+ 1102,
+ /* FCLASS_D */
+ 1105,
+ /* FCLASS_S */
+ 1107,
+ /* FCMP_CAF_D */
+ 1109,
+ /* FCMP_CAF_S */
+ 1112,
+ /* FCMP_CEQ_D */
+ 1115,
+ /* FCMP_CEQ_S */
+ 1118,
+ /* FCMP_CLE_D */
+ 1121,
+ /* FCMP_CLE_S */
+ 1124,
+ /* FCMP_CLT_D */
+ 1127,
+ /* FCMP_CLT_S */
+ 1130,
+ /* FCMP_CNE_D */
+ 1133,
+ /* FCMP_CNE_S */
+ 1136,
+ /* FCMP_COR_D */
+ 1139,
+ /* FCMP_COR_S */
+ 1142,
+ /* FCMP_CUEQ_D */
+ 1145,
+ /* FCMP_CUEQ_S */
+ 1148,
+ /* FCMP_CULE_D */
+ 1151,
+ /* FCMP_CULE_S */
+ 1154,
+ /* FCMP_CULT_D */
+ 1157,
+ /* FCMP_CULT_S */
+ 1160,
+ /* FCMP_CUNE_D */
+ 1163,
+ /* FCMP_CUNE_S */
+ 1166,
+ /* FCMP_CUN_D */
+ 1169,
+ /* FCMP_CUN_S */
+ 1172,
+ /* FCMP_SAF_D */
+ 1175,
+ /* FCMP_SAF_S */
+ 1178,
+ /* FCMP_SEQ_D */
+ 1181,
+ /* FCMP_SEQ_S */
+ 1184,
+ /* FCMP_SLE_D */
+ 1187,
+ /* FCMP_SLE_S */
+ 1190,
+ /* FCMP_SLT_D */
+ 1193,
+ /* FCMP_SLT_S */
+ 1196,
+ /* FCMP_SNE_D */
+ 1199,
+ /* FCMP_SNE_S */
+ 1202,
+ /* FCMP_SOR_D */
+ 1205,
+ /* FCMP_SOR_S */
+ 1208,
+ /* FCMP_SUEQ_D */
+ 1211,
+ /* FCMP_SUEQ_S */
+ 1214,
+ /* FCMP_SULE_D */
+ 1217,
+ /* FCMP_SULE_S */
+ 1220,
+ /* FCMP_SULT_D */
+ 1223,
+ /* FCMP_SULT_S */
+ 1226,
+ /* FCMP_SUNE_D */
+ 1229,
+ /* FCMP_SUNE_S */
+ 1232,
+ /* FCMP_SUN_D */
+ 1235,
+ /* FCMP_SUN_S */
+ 1238,
+ /* FCOPYSIGN_D */
+ 1241,
+ /* FCOPYSIGN_S */
+ 1244,
+ /* FCVT_D_S */
+ 1247,
+ /* FCVT_S_D */
+ 1249,
+ /* FDIV_D */
+ 1251,
+ /* FDIV_S */
+ 1254,
+ /* FFINT_D_L */
+ 1257,
+ /* FFINT_D_W */
+ 1259,
+ /* FFINT_S_L */
+ 1261,
+ /* FFINT_S_W */
+ 1263,
+ /* FLDGT_D */
+ 1265,
+ /* FLDGT_S */
+ 1268,
+ /* FLDLE_D */
+ 1271,
+ /* FLDLE_S */
+ 1274,
+ /* FLDX_D */
+ 1277,
+ /* FLDX_S */
+ 1280,
+ /* FLD_D */
+ 1283,
+ /* FLD_S */
+ 1286,
+ /* FLOGB_D */
+ 1289,
+ /* FLOGB_S */
+ 1291,
+ /* FMADD_D */
+ 1293,
+ /* FMADD_S */
+ 1297,
+ /* FMAXA_D */
+ 1301,
+ /* FMAXA_S */
+ 1304,
+ /* FMAX_D */
+ 1307,
+ /* FMAX_S */
+ 1310,
+ /* FMINA_D */
+ 1313,
+ /* FMINA_S */
+ 1316,
+ /* FMIN_D */
+ 1319,
+ /* FMIN_S */
+ 1322,
+ /* FMOV_D */
+ 1325,
+ /* FMOV_S */
+ 1327,
+ /* FMSUB_D */
+ 1329,
+ /* FMSUB_S */
+ 1333,
+ /* FMUL_D */
+ 1337,
+ /* FMUL_S */
+ 1340,
+ /* FNEG_D */
+ 1343,
+ /* FNEG_S */
+ 1345,
+ /* FNMADD_D */
+ 1347,
+ /* FNMADD_S */
+ 1351,
+ /* FNMSUB_D */
+ 1355,
+ /* FNMSUB_S */
+ 1359,
+ /* FRECIP_D */
+ 1363,
+ /* FRECIP_S */
+ 1365,
+ /* FRINT_D */
+ 1367,
+ /* FRINT_S */
+ 1369,
+ /* FRSQRT_D */
+ 1371,
+ /* FRSQRT_S */
+ 1373,
+ /* FSCALEB_D */
+ 1375,
+ /* FSCALEB_S */
+ 1378,
+ /* FSEL_D */
+ 1381,
+ /* FSEL_S */
+ 1385,
+ /* FSQRT_D */
+ 1389,
+ /* FSQRT_S */
+ 1391,
+ /* FSTGT_D */
+ 1393,
+ /* FSTGT_S */
+ 1396,
+ /* FSTLE_D */
+ 1399,
+ /* FSTLE_S */
+ 1402,
+ /* FSTX_D */
+ 1405,
+ /* FSTX_S */
+ 1408,
+ /* FST_D */
+ 1411,
+ /* FST_S */
+ 1414,
+ /* FSUB_D */
+ 1417,
+ /* FSUB_S */
+ 1420,
+ /* FTINTRM_L_D */
+ 1423,
+ /* FTINTRM_L_S */
+ 1425,
+ /* FTINTRM_W_D */
+ 1427,
+ /* FTINTRM_W_S */
+ 1429,
+ /* FTINTRNE_L_D */
+ 1431,
+ /* FTINTRNE_L_S */
+ 1433,
+ /* FTINTRNE_W_D */
+ 1435,
+ /* FTINTRNE_W_S */
+ 1437,
+ /* FTINTRP_L_D */
+ 1439,
+ /* FTINTRP_L_S */
+ 1441,
+ /* FTINTRP_W_D */
+ 1443,
+ /* FTINTRP_W_S */
+ 1445,
+ /* FTINTRZ_L_D */
+ 1447,
+ /* FTINTRZ_L_S */
+ 1449,
+ /* FTINTRZ_W_D */
+ 1451,
+ /* FTINTRZ_W_S */
+ 1453,
+ /* FTINT_L_D */
+ 1455,
+ /* FTINT_L_S */
+ 1457,
+ /* FTINT_W_D */
+ 1459,
+ /* FTINT_W_S */
+ 1461,
+ /* IBAR */
+ 1463,
+ /* IDLE */
+ 1464,
+ /* INVTLB */
+ 1465,
+ /* IOCSRRD_B */
+ 1468,
+ /* IOCSRRD_D */
+ 1470,
+ /* IOCSRRD_H */
+ 1472,
+ /* IOCSRRD_W */
+ 1474,
+ /* IOCSRWR_B */
+ 1476,
+ /* IOCSRWR_D */
+ 1478,
+ /* IOCSRWR_H */
+ 1480,
+ /* IOCSRWR_W */
+ 1482,
+ /* JIRL */
+ 1484,
+ /* LDDIR */
+ 1487,
+ /* LDGT_B */
+ 1490,
+ /* LDGT_D */
+ 1493,
+ /* LDGT_H */
+ 1496,
+ /* LDGT_W */
+ 1499,
+ /* LDLE_B */
+ 1502,
+ /* LDLE_D */
+ 1505,
+ /* LDLE_H */
+ 1508,
+ /* LDLE_W */
+ 1511,
+ /* LDPTE */
+ 1514,
+ /* LDPTR_D */
+ 1516,
+ /* LDPTR_W */
+ 1519,
+ /* LDX_B */
+ 1522,
+ /* LDX_BU */
+ 1525,
+ /* LDX_D */
+ 1528,
+ /* LDX_H */
+ 1531,
+ /* LDX_HU */
+ 1534,
+ /* LDX_W */
+ 1537,
+ /* LDX_WU */
+ 1540,
+ /* LD_B */
+ 1543,
+ /* LD_BU */
+ 1546,
+ /* LD_D */
+ 1549,
+ /* LD_H */
+ 1552,
+ /* LD_HU */
+ 1555,
+ /* LD_W */
+ 1558,
+ /* LD_WU */
+ 1561,
+ /* LL_D */
+ 1564,
+ /* LL_W */
+ 1567,
+ /* LU12I_W */
+ 1570,
+ /* LU32I_D */
+ 1572,
+ /* LU52I_D */
+ 1575,
+ /* MASKEQZ */
+ 1578,
+ /* MASKNEZ */
+ 1581,
+ /* MOD_D */
+ 1584,
+ /* MOD_DU */
+ 1587,
+ /* MOD_W */
+ 1590,
+ /* MOD_WU */
+ 1593,
+ /* MOVCF2FR_S */
+ 1596,
+ /* MOVCF2GR */
+ 1598,
+ /* MOVFCSR2GR */
+ 1600,
+ /* MOVFR2CF_S */
+ 1602,
+ /* MOVFR2GR_D */
+ 1604,
+ /* MOVFR2GR_S */
+ 1606,
+ /* MOVFR2GR_S_64 */
+ 1608,
+ /* MOVFRH2GR_S */
+ 1610,
+ /* MOVGR2CF */
+ 1612,
+ /* MOVGR2FCSR */
+ 1614,
+ /* MOVGR2FRH_W */
+ 1616,
+ /* MOVGR2FR_D */
+ 1619,
+ /* MOVGR2FR_W */
+ 1621,
+ /* MOVGR2FR_W_64 */
+ 1623,
+ /* MULH_D */
+ 1625,
+ /* MULH_DU */
+ 1628,
+ /* MULH_W */
+ 1631,
+ /* MULH_WU */
+ 1634,
+ /* MULW_D_W */
+ 1637,
+ /* MULW_D_WU */
+ 1640,
+ /* MUL_D */
+ 1643,
+ /* MUL_W */
+ 1646,
+ /* NOR */
+ 1649,
+ /* OR */
+ 1652,
+ /* ORI */
+ 1655,
+ /* ORN */
+ 1658,
+ /* PCADDI */
+ 1661,
+ /* PCADDU12I */
+ 1663,
+ /* PCADDU18I */
+ 1665,
+ /* PCALAU12I */
+ 1667,
+ /* PRELD */
+ 1669,
+ /* PRELDX */
+ 1672,
+ /* RDTIMEH_W */
+ 1675,
+ /* RDTIMEL_W */
+ 1677,
+ /* RDTIME_D */
+ 1679,
+ /* REVB_2H */
+ 1681,
+ /* REVB_2W */
+ 1683,
+ /* REVB_4H */
+ 1685,
+ /* REVB_D */
+ 1687,
+ /* REVH_2W */
+ 1689,
+ /* REVH_D */
+ 1691,
+ /* ROTRI_D */
+ 1693,
+ /* ROTRI_W */
+ 1696,
+ /* ROTR_D */
+ 1699,
+ /* ROTR_W */
+ 1702,
+ /* SC_D */
+ 1705,
+ /* SC_W */
+ 1709,
+ /* SLLI_D */
+ 1713,
+ /* SLLI_W */
+ 1716,
+ /* SLL_D */
+ 1719,
+ /* SLL_W */
+ 1722,
+ /* SLT */
+ 1725,
+ /* SLTI */
+ 1728,
+ /* SLTU */
+ 1731,
+ /* SLTUI */
+ 1734,
+ /* SRAI_D */
+ 1737,
+ /* SRAI_W */
+ 1740,
+ /* SRA_D */
+ 1743,
+ /* SRA_W */
+ 1746,
+ /* SRLI_D */
+ 1749,
+ /* SRLI_W */
+ 1752,
+ /* SRL_D */
+ 1755,
+ /* SRL_W */
+ 1758,
+ /* STGT_B */
+ 1761,
+ /* STGT_D */
+ 1764,
+ /* STGT_H */
+ 1767,
+ /* STGT_W */
+ 1770,
+ /* STLE_B */
+ 1773,
+ /* STLE_D */
+ 1776,
+ /* STLE_H */
+ 1779,
+ /* STLE_W */
+ 1782,
+ /* STPTR_D */
+ 1785,
+ /* STPTR_W */
+ 1788,
+ /* STX_B */
+ 1791,
+ /* STX_D */
+ 1794,
+ /* STX_H */
+ 1797,
+ /* STX_W */
+ 1800,
+ /* ST_B */
+ 1803,
+ /* ST_D */
+ 1806,
+ /* ST_H */
+ 1809,
+ /* ST_W */
+ 1812,
+ /* SUB_D */
+ 1815,
+ /* SUB_W */
+ 1818,
+ /* SYSCALL */
+ 1821,
+ /* TLBCLR */
+ 1822,
+ /* TLBFILL */
+ 1822,
+ /* TLBFLUSH */
+ 1822,
+ /* TLBRD */
+ 1822,
+ /* TLBSRCH */
+ 1822,
+ /* TLBWR */
+ 1822,
+ /* XOR */
+ 1822,
+ /* XORI */
+ 1825,
+ };
+
+ using namespace OpTypes;
+ const int8_t OpcodeOperandTypes[] = {
+
+ /* PHI */
+ -1,
+ /* INLINEASM */
+ /* INLINEASM_BR */
+ /* CFI_INSTRUCTION */
+ i32imm,
+ /* EH_LABEL */
+ i32imm,
+ /* GC_LABEL */
+ i32imm,
+ /* ANNOTATION_LABEL */
+ i32imm,
+ /* KILL */
+ /* EXTRACT_SUBREG */
+ -1, -1, i32imm,
+ /* INSERT_SUBREG */
+ -1, -1, -1, i32imm,
+ /* IMPLICIT_DEF */
+ -1,
+ /* SUBREG_TO_REG */
+ -1, -1, -1, i32imm,
+ /* COPY_TO_REGCLASS */
+ -1, -1, i32imm,
+ /* DBG_VALUE */
+ /* DBG_VALUE_LIST */
+ /* DBG_INSTR_REF */
+ /* DBG_PHI */
+ /* DBG_LABEL */
+ -1,
+ /* REG_SEQUENCE */
+ -1, -1,
+ /* COPY */
+ -1, -1,
+ /* BUNDLE */
+ /* LIFETIME_START */
+ i32imm,
+ /* LIFETIME_END */
+ i32imm,
+ /* PSEUDO_PROBE */
+ i64imm, i64imm, i8imm, i32imm,
+ /* ARITH_FENCE */
+ -1, -1,
+ /* STACKMAP */
+ i64imm, i32imm,
+ /* FENTRY_CALL */
+ /* PATCHPOINT */
+ -1, i64imm, i32imm, -1, i32imm, i32imm,
+ /* LOAD_STACK_GUARD */
+ -1,
+ /* PREALLOCATED_SETUP */
+ i32imm,
+ /* PREALLOCATED_ARG */
+ -1, i32imm, i32imm,
+ /* STATEPOINT */
+ /* LOCAL_ESCAPE */
+ -1, i32imm,
+ /* FAULTING_OP */
+ -1,
+ /* PATCHABLE_OP */
+ /* PATCHABLE_FUNCTION_ENTER */
+ /* PATCHABLE_RET */
+ /* PATCHABLE_FUNCTION_EXIT */
+ /* PATCHABLE_TAIL_CALL */
+ /* PATCHABLE_EVENT_CALL */
+ -1, -1,
+ /* PATCHABLE_TYPED_EVENT_CALL */
+ -1, -1, -1,
+ /* ICALL_BRANCH_FUNNEL */
+ /* MEMBARRIER */
+ /* G_ASSERT_SEXT */
+ type0, type0, untyped_imm_0,
+ /* G_ASSERT_ZEXT */
+ type0, type0, untyped_imm_0,
+ /* G_ASSERT_ALIGN */
+ type0, type0, untyped_imm_0,
+ /* G_ADD */
+ type0, type0, type0,
+ /* G_SUB */
+ type0, type0, type0,
+ /* G_MUL */
+ type0, type0, type0,
+ /* G_SDIV */
+ type0, type0, type0,
+ /* G_UDIV */
+ type0, type0, type0,
+ /* G_SREM */
+ type0, type0, type0,
+ /* G_UREM */
+ type0, type0, type0,
+ /* G_SDIVREM */
+ type0, type0, type0, type0,
+ /* G_UDIVREM */
+ type0, type0, type0, type0,
+ /* G_AND */
+ type0, type0, type0,
+ /* G_OR */
+ type0, type0, type0,
+ /* G_XOR */
+ type0, type0, type0,
+ /* G_IMPLICIT_DEF */
+ type0,
+ /* G_PHI */
+ type0,
+ /* G_FRAME_INDEX */
+ type0, -1,
+ /* G_GLOBAL_VALUE */
+ type0, -1,
+ /* G_EXTRACT */
+ type0, type1, untyped_imm_0,
+ /* G_UNMERGE_VALUES */
+ type0, type1,
+ /* G_INSERT */
+ type0, type0, type1, untyped_imm_0,
+ /* G_MERGE_VALUES */
+ type0, type1,
+ /* G_BUILD_VECTOR */
+ type0, type1,
+ /* G_BUILD_VECTOR_TRUNC */
+ type0, type1,
+ /* G_CONCAT_VECTORS */
+ type0, type1,
+ /* G_PTRTOINT */
+ type0, type1,
+ /* G_INTTOPTR */
+ type0, type1,
+ /* G_BITCAST */
+ type0, type1,
+ /* G_FREEZE */
+ type0, type0,
+ /* G_INTRINSIC_FPTRUNC_ROUND */
+ type0, type1, i32imm,
+ /* G_INTRINSIC_TRUNC */
+ type0, type0,
+ /* G_INTRINSIC_ROUND */
+ type0, type0,
+ /* G_INTRINSIC_LRINT */
+ type0, type1,
+ /* G_INTRINSIC_ROUNDEVEN */
+ type0, type0,
+ /* G_READCYCLECOUNTER */
+ type0,
+ /* G_LOAD */
+ type0, ptype1,
+ /* G_SEXTLOAD */
+ type0, ptype1,
+ /* G_ZEXTLOAD */
+ type0, ptype1,
+ /* G_INDEXED_LOAD */
+ type0, ptype1, ptype1, type2, -1,
+ /* G_INDEXED_SEXTLOAD */
+ type0, ptype1, ptype1, type2, -1,
+ /* G_INDEXED_ZEXTLOAD */
+ type0, ptype1, ptype1, type2, -1,
+ /* G_STORE */
+ type0, ptype1,
+ /* G_INDEXED_STORE */
+ ptype0, type1, ptype0, ptype2, -1,
+ /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
+ type0, type1, type2, type0, type0,
+ /* G_ATOMIC_CMPXCHG */
+ type0, ptype1, type0, type0,
+ /* G_ATOMICRMW_XCHG */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_ADD */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_SUB */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_AND */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_NAND */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_OR */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_XOR */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_MAX */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_MIN */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_UMAX */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_UMIN */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_FADD */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_FSUB */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_FMAX */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_FMIN */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_UINC_WRAP */
+ type0, ptype1, type0,
+ /* G_ATOMICRMW_UDEC_WRAP */
+ type0, ptype1, type0,
+ /* G_FENCE */
+ i32imm, i32imm,
+ /* G_BRCOND */
+ type0, -1,
+ /* G_BRINDIRECT */
+ type0,
+ /* G_INVOKE_REGION_START */
+ /* G_INTRINSIC */
+ -1,
+ /* G_INTRINSIC_W_SIDE_EFFECTS */
+ -1,
+ /* G_ANYEXT */
+ type0, type1,
+ /* G_TRUNC */
+ type0, type1,
+ /* G_CONSTANT */
+ type0, -1,
+ /* G_FCONSTANT */
+ type0, -1,
+ /* G_VASTART */
+ type0,
+ /* G_VAARG */
+ type0, type1, -1,
+ /* G_SEXT */
+ type0, type1,
+ /* G_SEXT_INREG */
+ type0, type0, untyped_imm_0,
+ /* G_ZEXT */
+ type0, type1,
+ /* G_SHL */
+ type0, type0, type1,
+ /* G_LSHR */
+ type0, type0, type1,
+ /* G_ASHR */
+ type0, type0, type1,
+ /* G_FSHL */
+ type0, type0, type0, type1,
+ /* G_FSHR */
+ type0, type0, type0, type1,
+ /* G_ROTR */
+ type0, type0, type1,
+ /* G_ROTL */
+ type0, type0, type1,
+ /* G_ICMP */
+ type0, -1, type1, type1,
+ /* G_FCMP */
+ type0, -1, type1, type1,
+ /* G_SELECT */
+ type0, type1, type0, type0,
+ /* G_UADDO */
+ type0, type1, type0, type0,
+ /* G_UADDE */
+ type0, type1, type0, type0, type1,
+ /* G_USUBO */
+ type0, type1, type0, type0,
+ /* G_USUBE */
+ type0, type1, type0, type0, type1,
+ /* G_SADDO */
+ type0, type1, type0, type0,
+ /* G_SADDE */
+ type0, type1, type0, type0, type1,
+ /* G_SSUBO */
+ type0, type1, type0, type0,
+ /* G_SSUBE */
+ type0, type1, type0, type0, type1,
+ /* G_UMULO */
+ type0, type1, type0, type0,
+ /* G_SMULO */
+ type0, type1, type0, type0,
+ /* G_UMULH */
+ type0, type0, type0,
+ /* G_SMULH */
+ type0, type0, type0,
+ /* G_UADDSAT */
+ type0, type0, type0,
+ /* G_SADDSAT */
+ type0, type0, type0,
+ /* G_USUBSAT */
+ type0, type0, type0,
+ /* G_SSUBSAT */
+ type0, type0, type0,
+ /* G_USHLSAT */
+ type0, type0, type1,
+ /* G_SSHLSAT */
+ type0, type0, type1,
+ /* G_SMULFIX */
+ type0, type0, type0, untyped_imm_0,
+ /* G_UMULFIX */
+ type0, type0, type0, untyped_imm_0,
+ /* G_SMULFIXSAT */
+ type0, type0, type0, untyped_imm_0,
+ /* G_UMULFIXSAT */
+ type0, type0, type0, untyped_imm_0,
+ /* G_SDIVFIX */
+ type0, type0, type0, untyped_imm_0,
+ /* G_UDIVFIX */
+ type0, type0, type0, untyped_imm_0,
+ /* G_SDIVFIXSAT */
+ type0, type0, type0, untyped_imm_0,
+ /* G_UDIVFIXSAT */
+ type0, type0, type0, untyped_imm_0,
+ /* G_FADD */
+ type0, type0, type0,
+ /* G_FSUB */
+ type0, type0, type0,
+ /* G_FMUL */
+ type0, type0, type0,
+ /* G_FMA */
+ type0, type0, type0, type0,
+ /* G_FMAD */
+ type0, type0, type0, type0,
+ /* G_FDIV */
+ type0, type0, type0,
+ /* G_FREM */
+ type0, type0, type0,
+ /* G_FPOW */
+ type0, type0, type0,
+ /* G_FPOWI */
+ type0, type0, type1,
+ /* G_FEXP */
+ type0, type0,
+ /* G_FEXP2 */
+ type0, type0,
+ /* G_FLOG */
+ type0, type0,
+ /* G_FLOG2 */
+ type0, type0,
+ /* G_FLOG10 */
+ type0, type0,
+ /* G_FNEG */
+ type0, type0,
+ /* G_FPEXT */
+ type0, type1,
+ /* G_FPTRUNC */
+ type0, type1,
+ /* G_FPTOSI */
+ type0, type1,
+ /* G_FPTOUI */
+ type0, type1,
+ /* G_SITOFP */
+ type0, type1,
+ /* G_UITOFP */
+ type0, type1,
+ /* G_FABS */
+ type0, type0,
+ /* G_FCOPYSIGN */
+ type0, type0, type1,
+ /* G_IS_FPCLASS */
+ type0, type1, -1,
+ /* G_FCANONICALIZE */
+ type0, type0,
+ /* G_FMINNUM */
+ type0, type0, type0,
+ /* G_FMAXNUM */
+ type0, type0, type0,
+ /* G_FMINNUM_IEEE */
+ type0, type0, type0,
+ /* G_FMAXNUM_IEEE */
+ type0, type0, type0,
+ /* G_FMINIMUM */
+ type0, type0, type0,
+ /* G_FMAXIMUM */
+ type0, type0, type0,
+ /* G_PTR_ADD */
+ ptype0, ptype0, type1,
+ /* G_PTRMASK */
+ ptype0, ptype0, type1,
+ /* G_SMIN */
+ type0, type0, type0,
+ /* G_SMAX */
+ type0, type0, type0,
+ /* G_UMIN */
+ type0, type0, type0,
+ /* G_UMAX */
+ type0, type0, type0,
+ /* G_ABS */
+ type0, type0,
+ /* G_LROUND */
+ type0, type1,
+ /* G_LLROUND */
+ type0, type1,
+ /* G_BR */
+ -1,
+ /* G_BRJT */
+ ptype0, -1, type1,
+ /* G_INSERT_VECTOR_ELT */
+ type0, type0, type1, type2,
+ /* G_EXTRACT_VECTOR_ELT */
+ type0, type1, type2,
+ /* G_SHUFFLE_VECTOR */
+ type0, type1, type1, -1,
+ /* G_CTTZ */
+ type0, type1,
+ /* G_CTTZ_ZERO_UNDEF */
+ type0, type1,
+ /* G_CTLZ */
+ type0, type1,
+ /* G_CTLZ_ZERO_UNDEF */
+ type0, type1,
+ /* G_CTPOP */
+ type0, type1,
+ /* G_BSWAP */
+ type0, type0,
+ /* G_BITREVERSE */
+ type0, type0,
+ /* G_FCEIL */
+ type0, type0,
+ /* G_FCOS */
+ type0, type0,
+ /* G_FSIN */
+ type0, type0,
+ /* G_FSQRT */
+ type0, type0,
+ /* G_FFLOOR */
+ type0, type0,
+ /* G_FRINT */
+ type0, type0,
+ /* G_FNEARBYINT */
+ type0, type0,
+ /* G_ADDRSPACE_CAST */
+ type0, type1,
+ /* G_BLOCK_ADDR */
+ type0, -1,
+ /* G_JUMP_TABLE */
+ type0, -1,
+ /* G_DYN_STACKALLOC */
+ ptype0, type1, i32imm,
+ /* G_STRICT_FADD */
+ type0, type0, type0,
+ /* G_STRICT_FSUB */
+ type0, type0, type0,
+ /* G_STRICT_FMUL */
+ type0, type0, type0,
+ /* G_STRICT_FDIV */
+ type0, type0, type0,
+ /* G_STRICT_FREM */
+ type0, type0, type0,
+ /* G_STRICT_FMA */
+ type0, type0, type0, type0,
+ /* G_STRICT_FSQRT */
+ type0, type0,
+ /* G_READ_REGISTER */
+ type0, -1,
+ /* G_WRITE_REGISTER */
+ -1, type0,
+ /* G_MEMCPY */
+ ptype0, ptype1, type2, untyped_imm_0,
+ /* G_MEMCPY_INLINE */
+ ptype0, ptype1, type2,
+ /* G_MEMMOVE */
+ ptype0, ptype1, type2, untyped_imm_0,
+ /* G_MEMSET */
+ ptype0, type1, type2, untyped_imm_0,
+ /* G_BZERO */
+ ptype0, type1, untyped_imm_0,
+ /* G_VECREDUCE_SEQ_FADD */
+ type0, type1, type2,
+ /* G_VECREDUCE_SEQ_FMUL */
+ type0, type1, type2,
+ /* G_VECREDUCE_FADD */
+ type0, type1,
+ /* G_VECREDUCE_FMUL */
+ type0, type1,
+ /* G_VECREDUCE_FMAX */
+ type0, type1,
+ /* G_VECREDUCE_FMIN */
+ type0, type1,
+ /* G_VECREDUCE_ADD */
+ type0, type1,
+ /* G_VECREDUCE_MUL */
+ type0, type1,
+ /* G_VECREDUCE_AND */
+ type0, type1,
+ /* G_VECREDUCE_OR */
+ type0, type1,
+ /* G_VECREDUCE_XOR */
+ type0, type1,
+ /* G_VECREDUCE_SMAX */
+ type0, type1,
+ /* G_VECREDUCE_SMIN */
+ type0, type1,
+ /* G_VECREDUCE_UMAX */
+ type0, type1,
+ /* G_VECREDUCE_UMIN */
+ type0, type1,
+ /* G_SBFX */
+ type0, type0, type1, type1,
+ /* G_UBFX */
+ type0, type0, type1, type1,
+ /* ADJCALLSTACKDOWN */
+ i32imm, i32imm,
+ /* ADJCALLSTACKUP */
+ i32imm, i32imm,
+ /* PseudoAtomicLoadAdd32 */
+ GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoAtomicLoadAnd32 */
+ GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoAtomicLoadNand32 */
+ GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoAtomicLoadNand64 */
+ GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoAtomicLoadOr32 */
+ GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoAtomicLoadSub32 */
+ GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoAtomicLoadXor32 */
+ GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoAtomicStoreD */
+ GPR, GPR, GPR,
+ /* PseudoAtomicStoreW */
+ GPR, GPR, GPR,
+ /* PseudoAtomicSwap32 */
+ GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoBR */
+ simm26_b,
+ /* PseudoBRIND */
+ GPR, simm16_lsl2,
+ /* PseudoB_TAIL */
+ simm26_b,
+ /* PseudoCALL */
+ simm26_symbol,
+ /* PseudoCALLIndirect */
+ GPR,
+ /* PseudoCmpXchg32 */
+ GPR, GPR, GPR, GPR, GPR,
+ /* PseudoCmpXchg64 */
+ GPR, GPR, GPR, GPR, GPR,
+ /* PseudoJIRL_CALL */
+ GPR, simm16_lsl2,
+ /* PseudoJIRL_TAIL */
+ GPR, simm16_lsl2,
+ /* PseudoLA_ABS */
+ GPR, bare_symbol,
+ /* PseudoLA_ABS_LARGE */
+ GPR, GPR, bare_symbol,
+ /* PseudoLA_GOT */
+ GPR, bare_symbol,
+ /* PseudoLA_GOT_LARGE */
+ GPR, GPR, bare_symbol,
+ /* PseudoLA_PCREL */
+ GPR, bare_symbol,
+ /* PseudoLA_PCREL_LARGE */
+ GPR, GPR, bare_symbol,
+ /* PseudoLA_TLS_GD */
+ GPR, bare_symbol,
+ /* PseudoLA_TLS_GD_LARGE */
+ GPR, GPR, bare_symbol,
+ /* PseudoLA_TLS_IE */
+ GPR, bare_symbol,
+ /* PseudoLA_TLS_IE_LARGE */
+ GPR, GPR, bare_symbol,
+ /* PseudoLA_TLS_LD */
+ GPR, bare_symbol,
+ /* PseudoLA_TLS_LD_LARGE */
+ GPR, GPR, bare_symbol,
+ /* PseudoLA_TLS_LE */
+ GPR, bare_symbol,
+ /* PseudoLD_CFR */
+ CFR, GPR, grlenimm,
+ /* PseudoLI_D */
+ GPR, grlenimm,
+ /* PseudoLI_W */
+ GPR, imm32,
+ /* PseudoMaskedAtomicLoadAdd32 */
+ GPR, GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoMaskedAtomicLoadMax32 */
+ GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, grlenimm,
+ /* PseudoMaskedAtomicLoadMin32 */
+ GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, grlenimm,
+ /* PseudoMaskedAtomicLoadNand32 */
+ GPR, GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoMaskedAtomicLoadSub32 */
+ GPR, GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoMaskedAtomicLoadUMax32 */
+ GPR, GPR, GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoMaskedAtomicLoadUMin32 */
+ GPR, GPR, GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoMaskedAtomicSwap32 */
+ GPR, GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoMaskedCmpXchg32 */
+ GPR, GPR, GPR, GPR, GPR, GPR, grlenimm,
+ /* PseudoRET */
+ /* PseudoST_CFR */
+ CFR, GPR, grlenimm,
+ /* PseudoTAIL */
+ simm26_symbol,
+ /* PseudoTAILIndirect */
+ GPRT,
+ /* PseudoUNIMP */
+ /* RDFCSR */
+ GPR, uimm2,
+ /* WRFCSR */
+ uimm2, GPR,
+ /* ADDI_D */
+ GPR, GPR, simm12_addlike,
+ /* ADDI_W */
+ GPR, GPR, simm12_addlike,
+ /* ADDU16I_D */
+ GPR, GPR, simm16,
+ /* ADD_D */
+ GPR, GPR, GPR,
+ /* ADD_W */
+ GPR, GPR, GPR,
+ /* ALSL_D */
+ GPR, GPR, GPR, uimm2_plus1,
+ /* ALSL_W */
+ GPR, GPR, GPR, uimm2_plus1,
+ /* ALSL_WU */
+ GPR, GPR, GPR, uimm2_plus1,
+ /* AMADD_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMADD_DB_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMADD_DB_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AMADD_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AMAND_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMAND_DB_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMAND_DB_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AMAND_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMAX_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMAX_DB_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMAX_DB_DU */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMAX_DB_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMAX_DB_WU */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMAX_DU */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMAX_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMAX_WU */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMIN_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMIN_DB_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMIN_DB_DU */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMIN_DB_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMIN_DB_WU */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMIN_DU */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMIN_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AMMIN_WU */
+ GPR, GPR, GPRMemAtomic,
+ /* AMOR_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMOR_DB_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMOR_DB_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AMOR_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AMSWAP_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMSWAP_DB_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMSWAP_DB_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AMSWAP_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AMXOR_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMXOR_DB_D */
+ GPR, GPR, GPRMemAtomic,
+ /* AMXOR_DB_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AMXOR_W */
+ GPR, GPR, GPRMemAtomic,
+ /* AND */
+ GPR, GPR, GPR,
+ /* ANDI */
+ GPR, GPR, uimm12,
+ /* ANDN */
+ GPR, GPR, GPR,
+ /* ASRTGT_D */
+ GPR, GPR,
+ /* ASRTLE_D */
+ GPR, GPR,
+ /* B */
+ simm26_b,
+ /* BCEQZ */
+ CFR, simm21_lsl2,
+ /* BCNEZ */
+ CFR, simm21_lsl2,
+ /* BEQ */
+ GPR, GPR, simm16_lsl2_br,
+ /* BEQZ */
+ GPR, simm21_lsl2,
+ /* BGE */
+ GPR, GPR, simm16_lsl2_br,
+ /* BGEU */
+ GPR, GPR, simm16_lsl2_br,
+ /* BITREV_4B */
+ GPR, GPR,
+ /* BITREV_8B */
+ GPR, GPR,
+ /* BITREV_D */
+ GPR, GPR,
+ /* BITREV_W */
+ GPR, GPR,
+ /* BL */
+ simm26_symbol,
+ /* BLT */
+ GPR, GPR, simm16_lsl2_br,
+ /* BLTU */
+ GPR, GPR, simm16_lsl2_br,
+ /* BNE */
+ GPR, GPR, simm16_lsl2_br,
+ /* BNEZ */
+ GPR, simm21_lsl2,
+ /* BREAK */
+ uimm15,
+ /* BSTRINS_D */
+ GPR, GPR, GPR, uimm6, uimm6,
+ /* BSTRINS_W */
+ GPR, GPR, GPR, uimm5, uimm5,
+ /* BSTRPICK_D */
+ GPR, GPR, uimm6, uimm6,
+ /* BSTRPICK_W */
+ GPR, GPR, uimm5, uimm5,
+ /* BYTEPICK_D */
+ GPR, GPR, GPR, uimm3,
+ /* BYTEPICK_W */
+ GPR, GPR, GPR, uimm2,
+ /* CACOP */
+ uimm5, GPR, simm12,
+ /* CLO_D */
+ GPR, GPR,
+ /* CLO_W */
+ GPR, GPR,
+ /* CLZ_D */
+ GPR, GPR,
+ /* CLZ_W */
+ GPR, GPR,
+ /* CPUCFG */
+ GPR, GPR,
+ /* CRCC_W_B_W */
+ GPR, GPR, GPR,
+ /* CRCC_W_D_W */
+ GPR, GPR, GPR,
+ /* CRCC_W_H_W */
+ GPR, GPR, GPR,
+ /* CRCC_W_W_W */
+ GPR, GPR, GPR,
+ /* CRC_W_B_W */
+ GPR, GPR, GPR,
+ /* CRC_W_D_W */
+ GPR, GPR, GPR,
+ /* CRC_W_H_W */
+ GPR, GPR, GPR,
+ /* CRC_W_W_W */
+ GPR, GPR, GPR,
+ /* CSRRD */
+ GPR, uimm14,
+ /* CSRWR */
+ GPR, GPR, uimm14,
+ /* CSRXCHG */
+ GPR, GPR, GPR, uimm14,
+ /* CTO_D */
+ GPR, GPR,
+ /* CTO_W */
+ GPR, GPR,
+ /* CTZ_D */
+ GPR, GPR,
+ /* CTZ_W */
+ GPR, GPR,
+ /* DBAR */
+ uimm15,
+ /* DBCL */
+ uimm15,
+ /* DIV_D */
+ GPR, GPR, GPR,
+ /* DIV_DU */
+ GPR, GPR, GPR,
+ /* DIV_W */
+ GPR, GPR, GPR,
+ /* DIV_WU */
+ GPR, GPR, GPR,
+ /* ERTN */
+ /* EXT_W_B */
+ GPR, GPR,
+ /* EXT_W_H */
+ GPR, GPR,
+ /* FABS_D */
+ FPR64, FPR64,
+ /* FABS_S */
+ FPR32, FPR32,
+ /* FADD_D */
+ FPR64, FPR64, FPR64,
+ /* FADD_S */
+ FPR32, FPR32, FPR32,
+ /* FCLASS_D */
+ FPR64, FPR64,
+ /* FCLASS_S */
+ FPR32, FPR32,
+ /* FCMP_CAF_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_CAF_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_CEQ_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_CEQ_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_CLE_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_CLE_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_CLT_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_CLT_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_CNE_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_CNE_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_COR_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_COR_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_CUEQ_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_CUEQ_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_CULE_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_CULE_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_CULT_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_CULT_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_CUNE_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_CUNE_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_CUN_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_CUN_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_SAF_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_SAF_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_SEQ_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_SEQ_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_SLE_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_SLE_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_SLT_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_SLT_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_SNE_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_SNE_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_SOR_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_SOR_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_SUEQ_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_SUEQ_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_SULE_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_SULE_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_SULT_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_SULT_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_SUNE_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_SUNE_S */
+ CFR, FPR32, FPR32,
+ /* FCMP_SUN_D */
+ CFR, FPR64, FPR64,
+ /* FCMP_SUN_S */
+ CFR, FPR32, FPR32,
+ /* FCOPYSIGN_D */
+ FPR64, FPR64, FPR64,
+ /* FCOPYSIGN_S */
+ FPR32, FPR32, FPR32,
+ /* FCVT_D_S */
+ FPR64, FPR32,
+ /* FCVT_S_D */
+ FPR32, FPR64,
+ /* FDIV_D */
+ FPR64, FPR64, FPR64,
+ /* FDIV_S */
+ FPR32, FPR32, FPR32,
+ /* FFINT_D_L */
+ FPR64, FPR64,
+ /* FFINT_D_W */
+ FPR64, FPR32,
+ /* FFINT_S_L */
+ FPR32, FPR64,
+ /* FFINT_S_W */
+ FPR32, FPR32,
+ /* FLDGT_D */
+ FPR64, GPR, GPR,
+ /* FLDGT_S */
+ FPR32, GPR, GPR,
+ /* FLDLE_D */
+ FPR64, GPR, GPR,
+ /* FLDLE_S */
+ FPR32, GPR, GPR,
+ /* FLDX_D */
+ FPR64, GPR, GPR,
+ /* FLDX_S */
+ FPR32, GPR, GPR,
+ /* FLD_D */
+ FPR64, GPR, simm12,
+ /* FLD_S */
+ FPR32, GPR, simm12,
+ /* FLOGB_D */
+ FPR64, FPR64,
+ /* FLOGB_S */
+ FPR32, FPR32,
+ /* FMADD_D */
+ FPR64, FPR64, FPR64, FPR64,
+ /* FMADD_S */
+ FPR32, FPR32, FPR32, FPR32,
+ /* FMAXA_D */
+ FPR64, FPR64, FPR64,
+ /* FMAXA_S */
+ FPR32, FPR32, FPR32,
+ /* FMAX_D */
+ FPR64, FPR64, FPR64,
+ /* FMAX_S */
+ FPR32, FPR32, FPR32,
+ /* FMINA_D */
+ FPR64, FPR64, FPR64,
+ /* FMINA_S */
+ FPR32, FPR32, FPR32,
+ /* FMIN_D */
+ FPR64, FPR64, FPR64,
+ /* FMIN_S */
+ FPR32, FPR32, FPR32,
+ /* FMOV_D */
+ FPR64, FPR64,
+ /* FMOV_S */
+ FPR32, FPR32,
+ /* FMSUB_D */
+ FPR64, FPR64, FPR64, FPR64,
+ /* FMSUB_S */
+ FPR32, FPR32, FPR32, FPR32,
+ /* FMUL_D */
+ FPR64, FPR64, FPR64,
+ /* FMUL_S */
+ FPR32, FPR32, FPR32,
+ /* FNEG_D */
+ FPR64, FPR64,
+ /* FNEG_S */
+ FPR32, FPR32,
+ /* FNMADD_D */
+ FPR64, FPR64, FPR64, FPR64,
+ /* FNMADD_S */
+ FPR32, FPR32, FPR32, FPR32,
+ /* FNMSUB_D */
+ FPR64, FPR64, FPR64, FPR64,
+ /* FNMSUB_S */
+ FPR32, FPR32, FPR32, FPR32,
+ /* FRECIP_D */
+ FPR64, FPR64,
+ /* FRECIP_S */
+ FPR32, FPR32,
+ /* FRINT_D */
+ FPR64, FPR64,
+ /* FRINT_S */
+ FPR32, FPR32,
+ /* FRSQRT_D */
+ FPR64, FPR64,
+ /* FRSQRT_S */
+ FPR32, FPR32,
+ /* FSCALEB_D */
+ FPR64, FPR64, FPR64,
+ /* FSCALEB_S */
+ FPR32, FPR32, FPR32,
+ /* FSEL_D */
+ FPR64, FPR64, FPR64, CFR,
+ /* FSEL_S */
+ FPR32, FPR32, FPR32, CFR,
+ /* FSQRT_D */
+ FPR64, FPR64,
+ /* FSQRT_S */
+ FPR32, FPR32,
+ /* FSTGT_D */
+ FPR64, GPR, GPR,
+ /* FSTGT_S */
+ FPR32, GPR, GPR,
+ /* FSTLE_D */
+ FPR64, GPR, GPR,
+ /* FSTLE_S */
+ FPR32, GPR, GPR,
+ /* FSTX_D */
+ FPR64, GPR, GPR,
+ /* FSTX_S */
+ FPR32, GPR, GPR,
+ /* FST_D */
+ FPR64, GPR, simm12,
+ /* FST_S */
+ FPR32, GPR, simm12,
+ /* FSUB_D */
+ FPR64, FPR64, FPR64,
+ /* FSUB_S */
+ FPR32, FPR32, FPR32,
+ /* FTINTRM_L_D */
+ FPR64, FPR64,
+ /* FTINTRM_L_S */
+ FPR64, FPR32,
+ /* FTINTRM_W_D */
+ FPR32, FPR64,
+ /* FTINTRM_W_S */
+ FPR32, FPR32,
+ /* FTINTRNE_L_D */
+ FPR64, FPR64,
+ /* FTINTRNE_L_S */
+ FPR64, FPR32,
+ /* FTINTRNE_W_D */
+ FPR32, FPR64,
+ /* FTINTRNE_W_S */
+ FPR32, FPR32,
+ /* FTINTRP_L_D */
+ FPR64, FPR64,
+ /* FTINTRP_L_S */
+ FPR64, FPR32,
+ /* FTINTRP_W_D */
+ FPR32, FPR64,
+ /* FTINTRP_W_S */
+ FPR32, FPR32,
+ /* FTINTRZ_L_D */
+ FPR64, FPR64,
+ /* FTINTRZ_L_S */
+ FPR64, FPR32,
+ /* FTINTRZ_W_D */
+ FPR32, FPR64,
+ /* FTINTRZ_W_S */
+ FPR32, FPR32,
+ /* FTINT_L_D */
+ FPR64, FPR64,
+ /* FTINT_L_S */
+ FPR64, FPR32,
+ /* FTINT_W_D */
+ FPR32, FPR64,
+ /* FTINT_W_S */
+ FPR32, FPR32,
+ /* IBAR */
+ uimm15,
+ /* IDLE */
+ uimm15,
+ /* INVTLB */
+ GPR, GPR, uimm5,
+ /* IOCSRRD_B */
+ GPR, GPR,
+ /* IOCSRRD_D */
+ GPR, GPR,
+ /* IOCSRRD_H */
+ GPR, GPR,
+ /* IOCSRRD_W */
+ GPR, GPR,
+ /* IOCSRWR_B */
+ GPR, GPR,
+ /* IOCSRWR_D */
+ GPR, GPR,
+ /* IOCSRWR_H */
+ GPR, GPR,
+ /* IOCSRWR_W */
+ GPR, GPR,
+ /* JIRL */
+ GPR, GPR, simm16_lsl2,
+ /* LDDIR */
+ GPR, GPR, uimm8,
+ /* LDGT_B */
+ GPR, GPR, GPR,
+ /* LDGT_D */
+ GPR, GPR, GPR,
+ /* LDGT_H */
+ GPR, GPR, GPR,
+ /* LDGT_W */
+ GPR, GPR, GPR,
+ /* LDLE_B */
+ GPR, GPR, GPR,
+ /* LDLE_D */
+ GPR, GPR, GPR,
+ /* LDLE_H */
+ GPR, GPR, GPR,
+ /* LDLE_W */
+ GPR, GPR, GPR,
+ /* LDPTE */
+ GPR, uimm8,
+ /* LDPTR_D */
+ GPR, GPR, simm14_lsl2,
+ /* LDPTR_W */
+ GPR, GPR, simm14_lsl2,
+ /* LDX_B */
+ GPR, GPR, GPR,
+ /* LDX_BU */
+ GPR, GPR, GPR,
+ /* LDX_D */
+ GPR, GPR, GPR,
+ /* LDX_H */
+ GPR, GPR, GPR,
+ /* LDX_HU */
+ GPR, GPR, GPR,
+ /* LDX_W */
+ GPR, GPR, GPR,
+ /* LDX_WU */
+ GPR, GPR, GPR,
+ /* LD_B */
+ GPR, GPR, simm12_addlike,
+ /* LD_BU */
+ GPR, GPR, simm12_addlike,
+ /* LD_D */
+ GPR, GPR, simm12_addlike,
+ /* LD_H */
+ GPR, GPR, simm12_addlike,
+ /* LD_HU */
+ GPR, GPR, simm12_addlike,
+ /* LD_W */
+ GPR, GPR, simm12_addlike,
+ /* LD_WU */
+ GPR, GPR, simm12_addlike,
+ /* LL_D */
+ GPR, GPR, simm14_lsl2,
+ /* LL_W */
+ GPR, GPR, simm14_lsl2,
+ /* LU12I_W */
+ GPR, simm20_lu12iw,
+ /* LU32I_D */
+ GPR, GPR, simm20_lu32id,
+ /* LU52I_D */
+ GPR, GPR, simm12_lu52id,
+ /* MASKEQZ */
+ GPR, GPR, GPR,
+ /* MASKNEZ */
+ GPR, GPR, GPR,
+ /* MOD_D */
+ GPR, GPR, GPR,
+ /* MOD_DU */
+ GPR, GPR, GPR,
+ /* MOD_W */
+ GPR, GPR, GPR,
+ /* MOD_WU */
+ GPR, GPR, GPR,
+ /* MOVCF2FR_S */
+ FPR32, CFR,
+ /* MOVCF2GR */
+ GPR, CFR,
+ /* MOVFCSR2GR */
+ GPR, FCSR,
+ /* MOVFR2CF_S */
+ CFR, FPR32,
+ /* MOVFR2GR_D */
+ GPR, FPR64,
+ /* MOVFR2GR_S */
+ GPR, FPR32,
+ /* MOVFR2GR_S_64 */
+ GPR, FPR64,
+ /* MOVFRH2GR_S */
+ GPR, FPR64,
+ /* MOVGR2CF */
+ CFR, GPR,
+ /* MOVGR2FCSR */
+ FCSR, GPR,
+ /* MOVGR2FRH_W */
+ FPR64, FPR64, GPR,
+ /* MOVGR2FR_D */
+ FPR64, GPR,
+ /* MOVGR2FR_W */
+ FPR32, GPR,
+ /* MOVGR2FR_W_64 */
+ FPR64, GPR,
+ /* MULH_D */
+ GPR, GPR, GPR,
+ /* MULH_DU */
+ GPR, GPR, GPR,
+ /* MULH_W */
+ GPR, GPR, GPR,
+ /* MULH_WU */
+ GPR, GPR, GPR,
+ /* MULW_D_W */
+ GPR, GPR, GPR,
+ /* MULW_D_WU */
+ GPR, GPR, GPR,
+ /* MUL_D */
+ GPR, GPR, GPR,
+ /* MUL_W */
+ GPR, GPR, GPR,
+ /* NOR */
+ GPR, GPR, GPR,
+ /* OR */
+ GPR, GPR, GPR,
+ /* ORI */
+ GPR, GPR, uimm12_ori,
+ /* ORN */
+ GPR, GPR, GPR,
+ /* PCADDI */
+ GPR, simm20,
+ /* PCADDU12I */
+ GPR, simm20,
+ /* PCADDU18I */
+ GPR, simm20,
+ /* PCALAU12I */
+ GPR, simm20_pcalau12i,
+ /* PRELD */
+ uimm5, GPR, simm12,
+ /* PRELDX */
+ uimm5, GPR, GPR,
+ /* RDTIMEH_W */
+ GPR, GPR,
+ /* RDTIMEL_W */
+ GPR, GPR,
+ /* RDTIME_D */
+ GPR, GPR,
+ /* REVB_2H */
+ GPR, GPR,
+ /* REVB_2W */
+ GPR, GPR,
+ /* REVB_4H */
+ GPR, GPR,
+ /* REVB_D */
+ GPR, GPR,
+ /* REVH_2W */
+ GPR, GPR,
+ /* REVH_D */
+ GPR, GPR,
+ /* ROTRI_D */
+ GPR, GPR, uimm6,
+ /* ROTRI_W */
+ GPR, GPR, uimm5,
+ /* ROTR_D */
+ GPR, GPR, GPR,
+ /* ROTR_W */
+ GPR, GPR, GPR,
+ /* SC_D */
+ GPR, GPR, GPR, simm14_lsl2,
+ /* SC_W */
+ GPR, GPR, GPR, simm14_lsl2,
+ /* SLLI_D */
+ GPR, GPR, uimm6,
+ /* SLLI_W */
+ GPR, GPR, uimm5,
+ /* SLL_D */
+ GPR, GPR, GPR,
+ /* SLL_W */
+ GPR, GPR, GPR,
+ /* SLT */
+ GPR, GPR, GPR,
+ /* SLTI */
+ GPR, GPR, simm12,
+ /* SLTU */
+ GPR, GPR, GPR,
+ /* SLTUI */
+ GPR, GPR, simm12,
+ /* SRAI_D */
+ GPR, GPR, uimm6,
+ /* SRAI_W */
+ GPR, GPR, uimm5,
+ /* SRA_D */
+ GPR, GPR, GPR,
+ /* SRA_W */
+ GPR, GPR, GPR,
+ /* SRLI_D */
+ GPR, GPR, uimm6,
+ /* SRLI_W */
+ GPR, GPR, uimm5,
+ /* SRL_D */
+ GPR, GPR, GPR,
+ /* SRL_W */
+ GPR, GPR, GPR,
+ /* STGT_B */
+ GPR, GPR, GPR,
+ /* STGT_D */
+ GPR, GPR, GPR,
+ /* STGT_H */
+ GPR, GPR, GPR,
+ /* STGT_W */
+ GPR, GPR, GPR,
+ /* STLE_B */
+ GPR, GPR, GPR,
+ /* STLE_D */
+ GPR, GPR, GPR,
+ /* STLE_H */
+ GPR, GPR, GPR,
+ /* STLE_W */
+ GPR, GPR, GPR,
+ /* STPTR_D */
+ GPR, GPR, simm14_lsl2,
+ /* STPTR_W */
+ GPR, GPR, simm14_lsl2,
+ /* STX_B */
+ GPR, GPR, GPR,
+ /* STX_D */
+ GPR, GPR, GPR,
+ /* STX_H */
+ GPR, GPR, GPR,
+ /* STX_W */
+ GPR, GPR, GPR,
+ /* ST_B */
+ GPR, GPR, simm12_addlike,
+ /* ST_D */
+ GPR, GPR, simm12_addlike,
+ /* ST_H */
+ GPR, GPR, simm12_addlike,
+ /* ST_W */
+ GPR, GPR, simm12_addlike,
+ /* SUB_D */
+ GPR, GPR, GPR,
+ /* SUB_W */
+ GPR, GPR, GPR,
+ /* SYSCALL */
+ uimm15,
+ /* TLBCLR */
+ /* TLBFILL */
+ /* TLBFLUSH */
+ /* TLBRD */
+ /* TLBSRCH */
+ /* TLBWR */
+ /* XOR */
+ GPR, GPR, GPR,
+ /* XORI */
+ GPR, GPR, uimm12,
+ };
+ return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
+}
+} // end namespace LoongArch
+} // end namespace llvm
+#endif // GET_INSTRINFO_OPERAND_TYPE
+
+#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
+#undef GET_INSTRINFO_MEM_OPERAND_SIZE
+namespace llvm {
+namespace LoongArch {
+LLVM_READONLY
+static int getMemOperandSize(int OpType) {
+ switch (OpType) {
+ default: return 0;
+ }
+}
+} // end namespace LoongArch
+} // end namespace llvm
+#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
+
+#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
+#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
+namespace llvm {
+namespace LoongArch {
+LLVM_READONLY static unsigned
+getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
+ return LogicalOpIdx;
+}
+LLVM_READONLY static inline unsigned
+getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
+ auto S = 0U;
+ for (auto i = 0U; i < LogicalOpIdx; ++i)
+ S += getLogicalOperandSize(Opcode, i);
+ return S;
+}
+} // end namespace LoongArch
+} // end namespace llvm
+#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
+
+#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
+#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
+namespace llvm {
+namespace LoongArch {
+LLVM_READONLY static int
+getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
+ return -1;
+}
+} // end namespace LoongArch
+} // end namespace llvm
+#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
+
+#ifdef GET_INSTRINFO_MC_HELPER_DECLS
+#undef GET_INSTRINFO_MC_HELPER_DECLS
+
+namespace llvm {
+class MCInst;
+class FeatureBitset;
+
+namespace LoongArch_MC {
+
+void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
+
+} // end namespace LoongArch_MC
+} // end namespace llvm
+
+#endif // GET_INSTRINFO_MC_HELPER_DECLS
+
+#ifdef GET_INSTRINFO_MC_HELPERS
+#undef GET_INSTRINFO_MC_HELPERS
+
+namespace llvm {
+namespace LoongArch_MC {
+
+} // end namespace LoongArch_MC
+} // end namespace llvm
+
+#endif // GET_GENISTRINFO_MC_HELPERS
+
+#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
+#undef ENABLE_INSTR_PREDICATE_VERIFIER
+#include <sstream>
+
+namespace llvm {
+namespace LoongArch_MC {
+
+// Bits for subtarget features that participate in instruction matching.
+enum SubtargetFeatureBits : uint8_t {
+ Feature_IsLA64Bit = 10,
+ Feature_IsLA32Bit = 9,
+ Feature_HasBasicFBit = 1,
+ Feature_HasBasicDBit = 0,
+ Feature_HasExtLSXBit = 4,
+ Feature_HasExtLASXBit = 2,
+ Feature_HasExtLVZBit = 5,
+ Feature_HasExtLBTBit = 3,
+ Feature_HasLaGlobalWithPcrelBit = 7,
+ Feature_HasLaGlobalWithAbsBit = 6,
+ Feature_HasLaLocalWithAbsBit = 8,
+};
+
+#ifndef NDEBUG
+static const char *SubtargetFeatureNames[] = {
+ "Feature_HasBasicD",
+ "Feature_HasBasicF",
+ "Feature_HasExtLASX",
+ "Feature_HasExtLBT",
+ "Feature_HasExtLSX",
+ "Feature_HasExtLVZ",
+ "Feature_HasLaGlobalWithAbs",
+ "Feature_HasLaGlobalWithPcrel",
+ "Feature_HasLaLocalWithAbs",
+ "Feature_IsLA32",
+ "Feature_IsLA64",
+ nullptr
+};
+
+#endif // NDEBUG
+
+FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
+ FeatureBitset Features;
+ if (FB[LoongArch::Feature64Bit])
+ Features.set(Feature_IsLA64Bit);
+ if (!FB[LoongArch::Feature64Bit])
+ Features.set(Feature_IsLA32Bit);
+ if (FB[LoongArch::FeatureBasicF])
+ Features.set(Feature_HasBasicFBit);
+ if (FB[LoongArch::FeatureBasicD])
+ Features.set(Feature_HasBasicDBit);
+ if (FB[LoongArch::FeatureExtLSX])
+ Features.set(Feature_HasExtLSXBit);
+ if (FB[LoongArch::FeatureExtLASX])
+ Features.set(Feature_HasExtLASXBit);
+ if (FB[LoongArch::FeatureExtLVZ])
+ Features.set(Feature_HasExtLVZBit);
+ if (FB[LoongArch::FeatureExtLBT])
+ Features.set(Feature_HasExtLBTBit);
+ if (FB[LoongArch::LaGlobalWithPcrel])
+ Features.set(Feature_HasLaGlobalWithPcrelBit);
+ if (FB[LoongArch::LaGlobalWithAbs])
+ Features.set(Feature_HasLaGlobalWithAbsBit);
+ if (FB[LoongArch::LaLocalWithAbs])
+ Features.set(Feature_HasLaLocalWithAbsBit);
+ return Features;
+}
+
+#ifndef NDEBUG
+// Feature bitsets.
+enum : uint8_t {
+ CEFBS_None,
+ CEFBS_HasBasicD,
+ CEFBS_HasBasicF,
+ CEFBS_IsLA64,
+ CEFBS_HasBasicD_IsLA32,
+ CEFBS_HasBasicD_IsLA64,
+};
+
+static constexpr FeatureBitset FeatureBitsets[] = {
+ {}, // CEFBS_None
+ {Feature_HasBasicDBit, },
+ {Feature_HasBasicFBit, },
+ {Feature_IsLA64Bit, },
+ {Feature_HasBasicDBit, Feature_IsLA32Bit, },
+ {Feature_HasBasicDBit, Feature_IsLA64Bit, },
+};
+#endif // NDEBUG
+
+void verifyInstructionPredicates(
+ unsigned Opcode, const FeatureBitset &Features) {
+#ifndef NDEBUG
+ static uint8_t RequiredFeaturesRefs[] = {
+ CEFBS_None, // PHI = 0
+ CEFBS_None, // INLINEASM = 1
+ CEFBS_None, // INLINEASM_BR = 2
+ CEFBS_None, // CFI_INSTRUCTION = 3
+ CEFBS_None, // EH_LABEL = 4
+ CEFBS_None, // GC_LABEL = 5
+ CEFBS_None, // ANNOTATION_LABEL = 6
+ CEFBS_None, // KILL = 7
+ CEFBS_None, // EXTRACT_SUBREG = 8
+ CEFBS_None, // INSERT_SUBREG = 9
+ CEFBS_None, // IMPLICIT_DEF = 10
+ CEFBS_None, // SUBREG_TO_REG = 11
+ CEFBS_None, // COPY_TO_REGCLASS = 12
+ CEFBS_None, // DBG_VALUE = 13
+ CEFBS_None, // DBG_VALUE_LIST = 14
+ CEFBS_None, // DBG_INSTR_REF = 15
+ CEFBS_None, // DBG_PHI = 16
+ CEFBS_None, // DBG_LABEL = 17
+ CEFBS_None, // REG_SEQUENCE = 18
+ CEFBS_None, // COPY = 19
+ CEFBS_None, // BUNDLE = 20
+ CEFBS_None, // LIFETIME_START = 21
+ CEFBS_None, // LIFETIME_END = 22
+ CEFBS_None, // PSEUDO_PROBE = 23
+ CEFBS_None, // ARITH_FENCE = 24
+ CEFBS_None, // STACKMAP = 25
+ CEFBS_None, // FENTRY_CALL = 26
+ CEFBS_None, // PATCHPOINT = 27
+ CEFBS_None, // LOAD_STACK_GUARD = 28
+ CEFBS_None, // PREALLOCATED_SETUP = 29
+ CEFBS_None, // PREALLOCATED_ARG = 30
+ CEFBS_None, // STATEPOINT = 31
+ CEFBS_None, // LOCAL_ESCAPE = 32
+ CEFBS_None, // FAULTING_OP = 33
+ CEFBS_None, // PATCHABLE_OP = 34
+ CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
+ CEFBS_None, // PATCHABLE_RET = 36
+ CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
+ CEFBS_None, // PATCHABLE_TAIL_CALL = 38
+ CEFBS_None, // PATCHABLE_EVENT_CALL = 39
+ CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
+ CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
+ CEFBS_None, // MEMBARRIER = 42
+ CEFBS_None, // G_ASSERT_SEXT = 43
+ CEFBS_None, // G_ASSERT_ZEXT = 44
+ CEFBS_None, // G_ASSERT_ALIGN = 45
+ CEFBS_None, // G_ADD = 46
+ CEFBS_None, // G_SUB = 47
+ CEFBS_None, // G_MUL = 48
+ CEFBS_None, // G_SDIV = 49
+ CEFBS_None, // G_UDIV = 50
+ CEFBS_None, // G_SREM = 51
+ CEFBS_None, // G_UREM = 52
+ CEFBS_None, // G_SDIVREM = 53
+ CEFBS_None, // G_UDIVREM = 54
+ CEFBS_None, // G_AND = 55
+ CEFBS_None, // G_OR = 56
+ CEFBS_None, // G_XOR = 57
+ CEFBS_None, // G_IMPLICIT_DEF = 58
+ CEFBS_None, // G_PHI = 59
+ CEFBS_None, // G_FRAME_INDEX = 60
+ CEFBS_None, // G_GLOBAL_VALUE = 61
+ CEFBS_None, // G_EXTRACT = 62
+ CEFBS_None, // G_UNMERGE_VALUES = 63
+ CEFBS_None, // G_INSERT = 64
+ CEFBS_None, // G_MERGE_VALUES = 65
+ CEFBS_None, // G_BUILD_VECTOR = 66
+ CEFBS_None, // G_BUILD_VECTOR_TRUNC = 67
+ CEFBS_None, // G_CONCAT_VECTORS = 68
+ CEFBS_None, // G_PTRTOINT = 69
+ CEFBS_None, // G_INTTOPTR = 70
+ CEFBS_None, // G_BITCAST = 71
+ CEFBS_None, // G_FREEZE = 72
+ CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 73
+ CEFBS_None, // G_INTRINSIC_TRUNC = 74
+ CEFBS_None, // G_INTRINSIC_ROUND = 75
+ CEFBS_None, // G_INTRINSIC_LRINT = 76
+ CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 77
+ CEFBS_None, // G_READCYCLECOUNTER = 78
+ CEFBS_None, // G_LOAD = 79
+ CEFBS_None, // G_SEXTLOAD = 80
+ CEFBS_None, // G_ZEXTLOAD = 81
+ CEFBS_None, // G_INDEXED_LOAD = 82
+ CEFBS_None, // G_INDEXED_SEXTLOAD = 83
+ CEFBS_None, // G_INDEXED_ZEXTLOAD = 84
+ CEFBS_None, // G_STORE = 85
+ CEFBS_None, // G_INDEXED_STORE = 86
+ CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87
+ CEFBS_None, // G_ATOMIC_CMPXCHG = 88
+ CEFBS_None, // G_ATOMICRMW_XCHG = 89
+ CEFBS_None, // G_ATOMICRMW_ADD = 90
+ CEFBS_None, // G_ATOMICRMW_SUB = 91
+ CEFBS_None, // G_ATOMICRMW_AND = 92
+ CEFBS_None, // G_ATOMICRMW_NAND = 93
+ CEFBS_None, // G_ATOMICRMW_OR = 94
+ CEFBS_None, // G_ATOMICRMW_XOR = 95
+ CEFBS_None, // G_ATOMICRMW_MAX = 96
+ CEFBS_None, // G_ATOMICRMW_MIN = 97
+ CEFBS_None, // G_ATOMICRMW_UMAX = 98
+ CEFBS_None, // G_ATOMICRMW_UMIN = 99
+ CEFBS_None, // G_ATOMICRMW_FADD = 100
+ CEFBS_None, // G_ATOMICRMW_FSUB = 101
+ CEFBS_None, // G_ATOMICRMW_FMAX = 102
+ CEFBS_None, // G_ATOMICRMW_FMIN = 103
+ CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 104
+ CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 105
+ CEFBS_None, // G_FENCE = 106
+ CEFBS_None, // G_BRCOND = 107
+ CEFBS_None, // G_BRINDIRECT = 108
+ CEFBS_None, // G_INVOKE_REGION_START = 109
+ CEFBS_None, // G_INTRINSIC = 110
+ CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 111
+ CEFBS_None, // G_ANYEXT = 112
+ CEFBS_None, // G_TRUNC = 113
+ CEFBS_None, // G_CONSTANT = 114
+ CEFBS_None, // G_FCONSTANT = 115
+ CEFBS_None, // G_VASTART = 116
+ CEFBS_None, // G_VAARG = 117
+ CEFBS_None, // G_SEXT = 118
+ CEFBS_None, // G_SEXT_INREG = 119
+ CEFBS_None, // G_ZEXT = 120
+ CEFBS_None, // G_SHL = 121
+ CEFBS_None, // G_LSHR = 122
+ CEFBS_None, // G_ASHR = 123
+ CEFBS_None, // G_FSHL = 124
+ CEFBS_None, // G_FSHR = 125
+ CEFBS_None, // G_ROTR = 126
+ CEFBS_None, // G_ROTL = 127
+ CEFBS_None, // G_ICMP = 128
+ CEFBS_None, // G_FCMP = 129
+ CEFBS_None, // G_SELECT = 130
+ CEFBS_None, // G_UADDO = 131
+ CEFBS_None, // G_UADDE = 132
+ CEFBS_None, // G_USUBO = 133
+ CEFBS_None, // G_USUBE = 134
+ CEFBS_None, // G_SADDO = 135
+ CEFBS_None, // G_SADDE = 136
+ CEFBS_None, // G_SSUBO = 137
+ CEFBS_None, // G_SSUBE = 138
+ CEFBS_None, // G_UMULO = 139
+ CEFBS_None, // G_SMULO = 140
+ CEFBS_None, // G_UMULH = 141
+ CEFBS_None, // G_SMULH = 142
+ CEFBS_None, // G_UADDSAT = 143
+ CEFBS_None, // G_SADDSAT = 144
+ CEFBS_None, // G_USUBSAT = 145
+ CEFBS_None, // G_SSUBSAT = 146
+ CEFBS_None, // G_USHLSAT = 147
+ CEFBS_None, // G_SSHLSAT = 148
+ CEFBS_None, // G_SMULFIX = 149
+ CEFBS_None, // G_UMULFIX = 150
+ CEFBS_None, // G_SMULFIXSAT = 151
+ CEFBS_None, // G_UMULFIXSAT = 152
+ CEFBS_None, // G_SDIVFIX = 153
+ CEFBS_None, // G_UDIVFIX = 154
+ CEFBS_None, // G_SDIVFIXSAT = 155
+ CEFBS_None, // G_UDIVFIXSAT = 156
+ CEFBS_None, // G_FADD = 157
+ CEFBS_None, // G_FSUB = 158
+ CEFBS_None, // G_FMUL = 159
+ CEFBS_None, // G_FMA = 160
+ CEFBS_None, // G_FMAD = 161
+ CEFBS_None, // G_FDIV = 162
+ CEFBS_None, // G_FREM = 163
+ CEFBS_None, // G_FPOW = 164
+ CEFBS_None, // G_FPOWI = 165
+ CEFBS_None, // G_FEXP = 166
+ CEFBS_None, // G_FEXP2 = 167
+ CEFBS_None, // G_FLOG = 168
+ CEFBS_None, // G_FLOG2 = 169
+ CEFBS_None, // G_FLOG10 = 170
+ CEFBS_None, // G_FNEG = 171
+ CEFBS_None, // G_FPEXT = 172
+ CEFBS_None, // G_FPTRUNC = 173
+ CEFBS_None, // G_FPTOSI = 174
+ CEFBS_None, // G_FPTOUI = 175
+ CEFBS_None, // G_SITOFP = 176
+ CEFBS_None, // G_UITOFP = 177
+ CEFBS_None, // G_FABS = 178
+ CEFBS_None, // G_FCOPYSIGN = 179
+ CEFBS_None, // G_IS_FPCLASS = 180
+ CEFBS_None, // G_FCANONICALIZE = 181
+ CEFBS_None, // G_FMINNUM = 182
+ CEFBS_None, // G_FMAXNUM = 183
+ CEFBS_None, // G_FMINNUM_IEEE = 184
+ CEFBS_None, // G_FMAXNUM_IEEE = 185
+ CEFBS_None, // G_FMINIMUM = 186
+ CEFBS_None, // G_FMAXIMUM = 187
+ CEFBS_None, // G_PTR_ADD = 188
+ CEFBS_None, // G_PTRMASK = 189
+ CEFBS_None, // G_SMIN = 190
+ CEFBS_None, // G_SMAX = 191
+ CEFBS_None, // G_UMIN = 192
+ CEFBS_None, // G_UMAX = 193
+ CEFBS_None, // G_ABS = 194
+ CEFBS_None, // G_LROUND = 195
+ CEFBS_None, // G_LLROUND = 196
+ CEFBS_None, // G_BR = 197
+ CEFBS_None, // G_BRJT = 198
+ CEFBS_None, // G_INSERT_VECTOR_ELT = 199
+ CEFBS_None, // G_EXTRACT_VECTOR_ELT = 200
+ CEFBS_None, // G_SHUFFLE_VECTOR = 201
+ CEFBS_None, // G_CTTZ = 202
+ CEFBS_None, // G_CTTZ_ZERO_UNDEF = 203
+ CEFBS_None, // G_CTLZ = 204
+ CEFBS_None, // G_CTLZ_ZERO_UNDEF = 205
+ CEFBS_None, // G_CTPOP = 206
+ CEFBS_None, // G_BSWAP = 207
+ CEFBS_None, // G_BITREVERSE = 208
+ CEFBS_None, // G_FCEIL = 209
+ CEFBS_None, // G_FCOS = 210
+ CEFBS_None, // G_FSIN = 211
+ CEFBS_None, // G_FSQRT = 212
+ CEFBS_None, // G_FFLOOR = 213
+ CEFBS_None, // G_FRINT = 214
+ CEFBS_None, // G_FNEARBYINT = 215
+ CEFBS_None, // G_ADDRSPACE_CAST = 216
+ CEFBS_None, // G_BLOCK_ADDR = 217
+ CEFBS_None, // G_JUMP_TABLE = 218
+ CEFBS_None, // G_DYN_STACKALLOC = 219
+ CEFBS_None, // G_STRICT_FADD = 220
+ CEFBS_None, // G_STRICT_FSUB = 221
+ CEFBS_None, // G_STRICT_FMUL = 222
+ CEFBS_None, // G_STRICT_FDIV = 223
+ CEFBS_None, // G_STRICT_FREM = 224
+ CEFBS_None, // G_STRICT_FMA = 225
+ CEFBS_None, // G_STRICT_FSQRT = 226
+ CEFBS_None, // G_READ_REGISTER = 227
+ CEFBS_None, // G_WRITE_REGISTER = 228
+ CEFBS_None, // G_MEMCPY = 229
+ CEFBS_None, // G_MEMCPY_INLINE = 230
+ CEFBS_None, // G_MEMMOVE = 231
+ CEFBS_None, // G_MEMSET = 232
+ CEFBS_None, // G_BZERO = 233
+ CEFBS_None, // G_VECREDUCE_SEQ_FADD = 234
+ CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 235
+ CEFBS_None, // G_VECREDUCE_FADD = 236
+ CEFBS_None, // G_VECREDUCE_FMUL = 237
+ CEFBS_None, // G_VECREDUCE_FMAX = 238
+ CEFBS_None, // G_VECREDUCE_FMIN = 239
+ CEFBS_None, // G_VECREDUCE_ADD = 240
+ CEFBS_None, // G_VECREDUCE_MUL = 241
+ CEFBS_None, // G_VECREDUCE_AND = 242
+ CEFBS_None, // G_VECREDUCE_OR = 243
+ CEFBS_None, // G_VECREDUCE_XOR = 244
+ CEFBS_None, // G_VECREDUCE_SMAX = 245
+ CEFBS_None, // G_VECREDUCE_SMIN = 246
+ CEFBS_None, // G_VECREDUCE_UMAX = 247
+ CEFBS_None, // G_VECREDUCE_UMIN = 248
+ CEFBS_None, // G_SBFX = 249
+ CEFBS_None, // G_UBFX = 250
+ CEFBS_None, // ADJCALLSTACKDOWN = 251
+ CEFBS_None, // ADJCALLSTACKUP = 252
+ CEFBS_None, // PseudoAtomicLoadAdd32 = 253
+ CEFBS_None, // PseudoAtomicLoadAnd32 = 254
+ CEFBS_None, // PseudoAtomicLoadNand32 = 255
+ CEFBS_None, // PseudoAtomicLoadNand64 = 256
+ CEFBS_None, // PseudoAtomicLoadOr32 = 257
+ CEFBS_None, // PseudoAtomicLoadSub32 = 258
+ CEFBS_None, // PseudoAtomicLoadXor32 = 259
+ CEFBS_IsLA64, // PseudoAtomicStoreD = 260
+ CEFBS_None, // PseudoAtomicStoreW = 261
+ CEFBS_None, // PseudoAtomicSwap32 = 262
+ CEFBS_None, // PseudoBR = 263
+ CEFBS_None, // PseudoBRIND = 264
+ CEFBS_None, // PseudoB_TAIL = 265
+ CEFBS_None, // PseudoCALL = 266
+ CEFBS_None, // PseudoCALLIndirect = 267
+ CEFBS_None, // PseudoCmpXchg32 = 268
+ CEFBS_None, // PseudoCmpXchg64 = 269
+ CEFBS_None, // PseudoJIRL_CALL = 270
+ CEFBS_None, // PseudoJIRL_TAIL = 271
+ CEFBS_None, // PseudoLA_ABS = 272
+ CEFBS_None, // PseudoLA_ABS_LARGE = 273
+ CEFBS_None, // PseudoLA_GOT = 274
+ CEFBS_IsLA64, // PseudoLA_GOT_LARGE = 275
+ CEFBS_None, // PseudoLA_PCREL = 276
+ CEFBS_IsLA64, // PseudoLA_PCREL_LARGE = 277
+ CEFBS_None, // PseudoLA_TLS_GD = 278
+ CEFBS_IsLA64, // PseudoLA_TLS_GD_LARGE = 279
+ CEFBS_None, // PseudoLA_TLS_IE = 280
+ CEFBS_IsLA64, // PseudoLA_TLS_IE_LARGE = 281
+ CEFBS_None, // PseudoLA_TLS_LD = 282
+ CEFBS_IsLA64, // PseudoLA_TLS_LD_LARGE = 283
+ CEFBS_None, // PseudoLA_TLS_LE = 284
+ CEFBS_HasBasicF, // PseudoLD_CFR = 285
+ CEFBS_IsLA64, // PseudoLI_D = 286
+ CEFBS_None, // PseudoLI_W = 287
+ CEFBS_None, // PseudoMaskedAtomicLoadAdd32 = 288
+ CEFBS_None, // PseudoMaskedAtomicLoadMax32 = 289
+ CEFBS_None, // PseudoMaskedAtomicLoadMin32 = 290
+ CEFBS_None, // PseudoMaskedAtomicLoadNand32 = 291
+ CEFBS_None, // PseudoMaskedAtomicLoadSub32 = 292
+ CEFBS_None, // PseudoMaskedAtomicLoadUMax32 = 293
+ CEFBS_None, // PseudoMaskedAtomicLoadUMin32 = 294
+ CEFBS_None, // PseudoMaskedAtomicSwap32 = 295
+ CEFBS_None, // PseudoMaskedCmpXchg32 = 296
+ CEFBS_None, // PseudoRET = 297
+ CEFBS_HasBasicF, // PseudoST_CFR = 298
+ CEFBS_None, // PseudoTAIL = 299
+ CEFBS_None, // PseudoTAILIndirect = 300
+ CEFBS_None, // PseudoUNIMP = 301
+ CEFBS_HasBasicF, // RDFCSR = 302
+ CEFBS_HasBasicF, // WRFCSR = 303
+ CEFBS_IsLA64, // ADDI_D = 304
+ CEFBS_None, // ADDI_W = 305
+ CEFBS_IsLA64, // ADDU16I_D = 306
+ CEFBS_IsLA64, // ADD_D = 307
+ CEFBS_None, // ADD_W = 308
+ CEFBS_IsLA64, // ALSL_D = 309
+ CEFBS_None, // ALSL_W = 310
+ CEFBS_IsLA64, // ALSL_WU = 311
+ CEFBS_IsLA64, // AMADD_D = 312
+ CEFBS_IsLA64, // AMADD_DB_D = 313
+ CEFBS_IsLA64, // AMADD_DB_W = 314
+ CEFBS_IsLA64, // AMADD_W = 315
+ CEFBS_IsLA64, // AMAND_D = 316
+ CEFBS_IsLA64, // AMAND_DB_D = 317
+ CEFBS_IsLA64, // AMAND_DB_W = 318
+ CEFBS_IsLA64, // AMAND_W = 319
+ CEFBS_IsLA64, // AMMAX_D = 320
+ CEFBS_IsLA64, // AMMAX_DB_D = 321
+ CEFBS_IsLA64, // AMMAX_DB_DU = 322
+ CEFBS_IsLA64, // AMMAX_DB_W = 323
+ CEFBS_IsLA64, // AMMAX_DB_WU = 324
+ CEFBS_IsLA64, // AMMAX_DU = 325
+ CEFBS_IsLA64, // AMMAX_W = 326
+ CEFBS_IsLA64, // AMMAX_WU = 327
+ CEFBS_IsLA64, // AMMIN_D = 328
+ CEFBS_IsLA64, // AMMIN_DB_D = 329
+ CEFBS_IsLA64, // AMMIN_DB_DU = 330
+ CEFBS_IsLA64, // AMMIN_DB_W = 331
+ CEFBS_IsLA64, // AMMIN_DB_WU = 332
+ CEFBS_IsLA64, // AMMIN_DU = 333
+ CEFBS_IsLA64, // AMMIN_W = 334
+ CEFBS_IsLA64, // AMMIN_WU = 335
+ CEFBS_IsLA64, // AMOR_D = 336
+ CEFBS_IsLA64, // AMOR_DB_D = 337
+ CEFBS_IsLA64, // AMOR_DB_W = 338
+ CEFBS_IsLA64, // AMOR_W = 339
+ CEFBS_IsLA64, // AMSWAP_D = 340
+ CEFBS_IsLA64, // AMSWAP_DB_D = 341
+ CEFBS_IsLA64, // AMSWAP_DB_W = 342
+ CEFBS_IsLA64, // AMSWAP_W = 343
+ CEFBS_IsLA64, // AMXOR_D = 344
+ CEFBS_IsLA64, // AMXOR_DB_D = 345
+ CEFBS_IsLA64, // AMXOR_DB_W = 346
+ CEFBS_IsLA64, // AMXOR_W = 347
+ CEFBS_None, // AND = 348
+ CEFBS_None, // ANDI = 349
+ CEFBS_None, // ANDN = 350
+ CEFBS_IsLA64, // ASRTGT_D = 351
+ CEFBS_IsLA64, // ASRTLE_D = 352
+ CEFBS_None, // B = 353
+ CEFBS_HasBasicF, // BCEQZ = 354
+ CEFBS_HasBasicF, // BCNEZ = 355
+ CEFBS_None, // BEQ = 356
+ CEFBS_None, // BEQZ = 357
+ CEFBS_None, // BGE = 358
+ CEFBS_None, // BGEU = 359
+ CEFBS_None, // BITREV_4B = 360
+ CEFBS_IsLA64, // BITREV_8B = 361
+ CEFBS_IsLA64, // BITREV_D = 362
+ CEFBS_None, // BITREV_W = 363
+ CEFBS_None, // BL = 364
+ CEFBS_None, // BLT = 365
+ CEFBS_None, // BLTU = 366
+ CEFBS_None, // BNE = 367
+ CEFBS_None, // BNEZ = 368
+ CEFBS_None, // BREAK = 369
+ CEFBS_IsLA64, // BSTRINS_D = 370
+ CEFBS_None, // BSTRINS_W = 371
+ CEFBS_IsLA64, // BSTRPICK_D = 372
+ CEFBS_None, // BSTRPICK_W = 373
+ CEFBS_IsLA64, // BYTEPICK_D = 374
+ CEFBS_None, // BYTEPICK_W = 375
+ CEFBS_None, // CACOP = 376
+ CEFBS_IsLA64, // CLO_D = 377
+ CEFBS_None, // CLO_W = 378
+ CEFBS_IsLA64, // CLZ_D = 379
+ CEFBS_None, // CLZ_W = 380
+ CEFBS_None, // CPUCFG = 381
+ CEFBS_IsLA64, // CRCC_W_B_W = 382
+ CEFBS_IsLA64, // CRCC_W_D_W = 383
+ CEFBS_IsLA64, // CRCC_W_H_W = 384
+ CEFBS_IsLA64, // CRCC_W_W_W = 385
+ CEFBS_IsLA64, // CRC_W_B_W = 386
+ CEFBS_IsLA64, // CRC_W_D_W = 387
+ CEFBS_IsLA64, // CRC_W_H_W = 388
+ CEFBS_IsLA64, // CRC_W_W_W = 389
+ CEFBS_None, // CSRRD = 390
+ CEFBS_None, // CSRWR = 391
+ CEFBS_None, // CSRXCHG = 392
+ CEFBS_IsLA64, // CTO_D = 393
+ CEFBS_None, // CTO_W = 394
+ CEFBS_IsLA64, // CTZ_D = 395
+ CEFBS_None, // CTZ_W = 396
+ CEFBS_None, // DBAR = 397
+ CEFBS_None, // DBCL = 398
+ CEFBS_IsLA64, // DIV_D = 399
+ CEFBS_IsLA64, // DIV_DU = 400
+ CEFBS_None, // DIV_W = 401
+ CEFBS_None, // DIV_WU = 402
+ CEFBS_None, // ERTN = 403
+ CEFBS_None, // EXT_W_B = 404
+ CEFBS_None, // EXT_W_H = 405
+ CEFBS_HasBasicD, // FABS_D = 406
+ CEFBS_HasBasicF, // FABS_S = 407
+ CEFBS_HasBasicD, // FADD_D = 408
+ CEFBS_HasBasicF, // FADD_S = 409
+ CEFBS_HasBasicD, // FCLASS_D = 410
+ CEFBS_HasBasicF, // FCLASS_S = 411
+ CEFBS_HasBasicD, // FCMP_CAF_D = 412
+ CEFBS_HasBasicF, // FCMP_CAF_S = 413
+ CEFBS_HasBasicD, // FCMP_CEQ_D = 414
+ CEFBS_HasBasicF, // FCMP_CEQ_S = 415
+ CEFBS_HasBasicD, // FCMP_CLE_D = 416
+ CEFBS_HasBasicF, // FCMP_CLE_S = 417
+ CEFBS_HasBasicD, // FCMP_CLT_D = 418
+ CEFBS_HasBasicF, // FCMP_CLT_S = 419
+ CEFBS_HasBasicD, // FCMP_CNE_D = 420
+ CEFBS_HasBasicF, // FCMP_CNE_S = 421
+ CEFBS_HasBasicD, // FCMP_COR_D = 422
+ CEFBS_HasBasicF, // FCMP_COR_S = 423
+ CEFBS_HasBasicD, // FCMP_CUEQ_D = 424
+ CEFBS_HasBasicF, // FCMP_CUEQ_S = 425
+ CEFBS_HasBasicD, // FCMP_CULE_D = 426
+ CEFBS_HasBasicF, // FCMP_CULE_S = 427
+ CEFBS_HasBasicD, // FCMP_CULT_D = 428
+ CEFBS_HasBasicF, // FCMP_CULT_S = 429
+ CEFBS_HasBasicD, // FCMP_CUNE_D = 430
+ CEFBS_HasBasicF, // FCMP_CUNE_S = 431
+ CEFBS_HasBasicD, // FCMP_CUN_D = 432
+ CEFBS_HasBasicF, // FCMP_CUN_S = 433
+ CEFBS_HasBasicD, // FCMP_SAF_D = 434
+ CEFBS_HasBasicF, // FCMP_SAF_S = 435
+ CEFBS_HasBasicD, // FCMP_SEQ_D = 436
+ CEFBS_HasBasicF, // FCMP_SEQ_S = 437
+ CEFBS_HasBasicD, // FCMP_SLE_D = 438
+ CEFBS_HasBasicF, // FCMP_SLE_S = 439
+ CEFBS_HasBasicD, // FCMP_SLT_D = 440
+ CEFBS_HasBasicF, // FCMP_SLT_S = 441
+ CEFBS_HasBasicD, // FCMP_SNE_D = 442
+ CEFBS_HasBasicF, // FCMP_SNE_S = 443
+ CEFBS_HasBasicD, // FCMP_SOR_D = 444
+ CEFBS_HasBasicF, // FCMP_SOR_S = 445
+ CEFBS_HasBasicD, // FCMP_SUEQ_D = 446
+ CEFBS_HasBasicF, // FCMP_SUEQ_S = 447
+ CEFBS_HasBasicD, // FCMP_SULE_D = 448
+ CEFBS_HasBasicF, // FCMP_SULE_S = 449
+ CEFBS_HasBasicD, // FCMP_SULT_D = 450
+ CEFBS_HasBasicF, // FCMP_SULT_S = 451
+ CEFBS_HasBasicD, // FCMP_SUNE_D = 452
+ CEFBS_HasBasicF, // FCMP_SUNE_S = 453
+ CEFBS_HasBasicD, // FCMP_SUN_D = 454
+ CEFBS_HasBasicF, // FCMP_SUN_S = 455
+ CEFBS_HasBasicD, // FCOPYSIGN_D = 456
+ CEFBS_HasBasicF, // FCOPYSIGN_S = 457
+ CEFBS_HasBasicD, // FCVT_D_S = 458
+ CEFBS_HasBasicD, // FCVT_S_D = 459
+ CEFBS_HasBasicD, // FDIV_D = 460
+ CEFBS_HasBasicF, // FDIV_S = 461
+ CEFBS_HasBasicD, // FFINT_D_L = 462
+ CEFBS_HasBasicD, // FFINT_D_W = 463
+ CEFBS_HasBasicD, // FFINT_S_L = 464
+ CEFBS_HasBasicF, // FFINT_S_W = 465
+ CEFBS_HasBasicD, // FLDGT_D = 466
+ CEFBS_HasBasicF, // FLDGT_S = 467
+ CEFBS_HasBasicD, // FLDLE_D = 468
+ CEFBS_HasBasicF, // FLDLE_S = 469
+ CEFBS_HasBasicD, // FLDX_D = 470
+ CEFBS_HasBasicF, // FLDX_S = 471
+ CEFBS_HasBasicD, // FLD_D = 472
+ CEFBS_HasBasicF, // FLD_S = 473
+ CEFBS_HasBasicD, // FLOGB_D = 474
+ CEFBS_HasBasicF, // FLOGB_S = 475
+ CEFBS_HasBasicD, // FMADD_D = 476
+ CEFBS_HasBasicF, // FMADD_S = 477
+ CEFBS_HasBasicD, // FMAXA_D = 478
+ CEFBS_HasBasicF, // FMAXA_S = 479
+ CEFBS_HasBasicD, // FMAX_D = 480
+ CEFBS_HasBasicF, // FMAX_S = 481
+ CEFBS_HasBasicD, // FMINA_D = 482
+ CEFBS_HasBasicF, // FMINA_S = 483
+ CEFBS_HasBasicD, // FMIN_D = 484
+ CEFBS_HasBasicF, // FMIN_S = 485
+ CEFBS_HasBasicD, // FMOV_D = 486
+ CEFBS_HasBasicF, // FMOV_S = 487
+ CEFBS_HasBasicD, // FMSUB_D = 488
+ CEFBS_HasBasicF, // FMSUB_S = 489
+ CEFBS_HasBasicD, // FMUL_D = 490
+ CEFBS_HasBasicF, // FMUL_S = 491
+ CEFBS_HasBasicD, // FNEG_D = 492
+ CEFBS_HasBasicF, // FNEG_S = 493
+ CEFBS_HasBasicD, // FNMADD_D = 494
+ CEFBS_HasBasicF, // FNMADD_S = 495
+ CEFBS_HasBasicD, // FNMSUB_D = 496
+ CEFBS_HasBasicF, // FNMSUB_S = 497
+ CEFBS_HasBasicD, // FRECIP_D = 498
+ CEFBS_HasBasicF, // FRECIP_S = 499
+ CEFBS_HasBasicD, // FRINT_D = 500
+ CEFBS_HasBasicF, // FRINT_S = 501
+ CEFBS_HasBasicD, // FRSQRT_D = 502
+ CEFBS_HasBasicF, // FRSQRT_S = 503
+ CEFBS_HasBasicD, // FSCALEB_D = 504
+ CEFBS_HasBasicF, // FSCALEB_S = 505
+ CEFBS_HasBasicD, // FSEL_D = 506
+ CEFBS_HasBasicF, // FSEL_S = 507
+ CEFBS_HasBasicD, // FSQRT_D = 508
+ CEFBS_HasBasicF, // FSQRT_S = 509
+ CEFBS_HasBasicD, // FSTGT_D = 510
+ CEFBS_HasBasicF, // FSTGT_S = 511
+ CEFBS_HasBasicD, // FSTLE_D = 512
+ CEFBS_HasBasicF, // FSTLE_S = 513
+ CEFBS_HasBasicD, // FSTX_D = 514
+ CEFBS_HasBasicF, // FSTX_S = 515
+ CEFBS_HasBasicD, // FST_D = 516
+ CEFBS_HasBasicF, // FST_S = 517
+ CEFBS_HasBasicD, // FSUB_D = 518
+ CEFBS_HasBasicF, // FSUB_S = 519
+ CEFBS_HasBasicD, // FTINTRM_L_D = 520
+ CEFBS_HasBasicD, // FTINTRM_L_S = 521
+ CEFBS_HasBasicD, // FTINTRM_W_D = 522
+ CEFBS_HasBasicF, // FTINTRM_W_S = 523
+ CEFBS_HasBasicD, // FTINTRNE_L_D = 524
+ CEFBS_HasBasicD, // FTINTRNE_L_S = 525
+ CEFBS_HasBasicD, // FTINTRNE_W_D = 526
+ CEFBS_HasBasicF, // FTINTRNE_W_S = 527
+ CEFBS_HasBasicD, // FTINTRP_L_D = 528
+ CEFBS_HasBasicD, // FTINTRP_L_S = 529
+ CEFBS_HasBasicD, // FTINTRP_W_D = 530
+ CEFBS_HasBasicF, // FTINTRP_W_S = 531
+ CEFBS_HasBasicD, // FTINTRZ_L_D = 532
+ CEFBS_HasBasicD, // FTINTRZ_L_S = 533
+ CEFBS_HasBasicD, // FTINTRZ_W_D = 534
+ CEFBS_HasBasicF, // FTINTRZ_W_S = 535
+ CEFBS_HasBasicD, // FTINT_L_D = 536
+ CEFBS_HasBasicD, // FTINT_L_S = 537
+ CEFBS_HasBasicD, // FTINT_W_D = 538
+ CEFBS_HasBasicF, // FTINT_W_S = 539
+ CEFBS_None, // IBAR = 540
+ CEFBS_None, // IDLE = 541
+ CEFBS_None, // INVTLB = 542
+ CEFBS_None, // IOCSRRD_B = 543
+ CEFBS_IsLA64, // IOCSRRD_D = 544
+ CEFBS_None, // IOCSRRD_H = 545
+ CEFBS_None, // IOCSRRD_W = 546
+ CEFBS_None, // IOCSRWR_B = 547
+ CEFBS_IsLA64, // IOCSRWR_D = 548
+ CEFBS_None, // IOCSRWR_H = 549
+ CEFBS_None, // IOCSRWR_W = 550
+ CEFBS_None, // JIRL = 551
+ CEFBS_None, // LDDIR = 552
+ CEFBS_IsLA64, // LDGT_B = 553
+ CEFBS_IsLA64, // LDGT_D = 554
+ CEFBS_IsLA64, // LDGT_H = 555
+ CEFBS_IsLA64, // LDGT_W = 556
+ CEFBS_IsLA64, // LDLE_B = 557
+ CEFBS_IsLA64, // LDLE_D = 558
+ CEFBS_IsLA64, // LDLE_H = 559
+ CEFBS_IsLA64, // LDLE_W = 560
+ CEFBS_None, // LDPTE = 561
+ CEFBS_IsLA64, // LDPTR_D = 562
+ CEFBS_IsLA64, // LDPTR_W = 563
+ CEFBS_IsLA64, // LDX_B = 564
+ CEFBS_IsLA64, // LDX_BU = 565
+ CEFBS_IsLA64, // LDX_D = 566
+ CEFBS_IsLA64, // LDX_H = 567
+ CEFBS_IsLA64, // LDX_HU = 568
+ CEFBS_IsLA64, // LDX_W = 569
+ CEFBS_IsLA64, // LDX_WU = 570
+ CEFBS_None, // LD_B = 571
+ CEFBS_None, // LD_BU = 572
+ CEFBS_IsLA64, // LD_D = 573
+ CEFBS_None, // LD_H = 574
+ CEFBS_None, // LD_HU = 575
+ CEFBS_None, // LD_W = 576
+ CEFBS_IsLA64, // LD_WU = 577
+ CEFBS_IsLA64, // LL_D = 578
+ CEFBS_None, // LL_W = 579
+ CEFBS_None, // LU12I_W = 580
+ CEFBS_IsLA64, // LU32I_D = 581
+ CEFBS_IsLA64, // LU52I_D = 582
+ CEFBS_None, // MASKEQZ = 583
+ CEFBS_None, // MASKNEZ = 584
+ CEFBS_IsLA64, // MOD_D = 585
+ CEFBS_IsLA64, // MOD_DU = 586
+ CEFBS_None, // MOD_W = 587
+ CEFBS_None, // MOD_WU = 588
+ CEFBS_HasBasicF, // MOVCF2FR_S = 589
+ CEFBS_HasBasicF, // MOVCF2GR = 590
+ CEFBS_HasBasicF, // MOVFCSR2GR = 591
+ CEFBS_HasBasicF, // MOVFR2CF_S = 592
+ CEFBS_HasBasicD_IsLA64, // MOVFR2GR_D = 593
+ CEFBS_HasBasicF, // MOVFR2GR_S = 594
+ CEFBS_HasBasicD, // MOVFR2GR_S_64 = 595
+ CEFBS_HasBasicD, // MOVFRH2GR_S = 596
+ CEFBS_HasBasicF, // MOVGR2CF = 597
+ CEFBS_HasBasicF, // MOVGR2FCSR = 598
+ CEFBS_HasBasicD, // MOVGR2FRH_W = 599
+ CEFBS_HasBasicD_IsLA64, // MOVGR2FR_D = 600
+ CEFBS_HasBasicF, // MOVGR2FR_W = 601
+ CEFBS_HasBasicD_IsLA32, // MOVGR2FR_W_64 = 602
+ CEFBS_IsLA64, // MULH_D = 603
+ CEFBS_IsLA64, // MULH_DU = 604
+ CEFBS_None, // MULH_W = 605
+ CEFBS_None, // MULH_WU = 606
+ CEFBS_IsLA64, // MULW_D_W = 607
+ CEFBS_IsLA64, // MULW_D_WU = 608
+ CEFBS_IsLA64, // MUL_D = 609
+ CEFBS_None, // MUL_W = 610
+ CEFBS_None, // NOR = 611
+ CEFBS_None, // OR = 612
+ CEFBS_None, // ORI = 613
+ CEFBS_None, // ORN = 614
+ CEFBS_None, // PCADDI = 615
+ CEFBS_None, // PCADDU12I = 616
+ CEFBS_IsLA64, // PCADDU18I = 617
+ CEFBS_None, // PCALAU12I = 618
+ CEFBS_None, // PRELD = 619
+ CEFBS_IsLA64, // PRELDX = 620
+ CEFBS_None, // RDTIMEH_W = 621
+ CEFBS_None, // RDTIMEL_W = 622
+ CEFBS_IsLA64, // RDTIME_D = 623
+ CEFBS_None, // REVB_2H = 624
+ CEFBS_IsLA64, // REVB_2W = 625
+ CEFBS_IsLA64, // REVB_4H = 626
+ CEFBS_IsLA64, // REVB_D = 627
+ CEFBS_IsLA64, // REVH_2W = 628
+ CEFBS_IsLA64, // REVH_D = 629
+ CEFBS_IsLA64, // ROTRI_D = 630
+ CEFBS_None, // ROTRI_W = 631
+ CEFBS_IsLA64, // ROTR_D = 632
+ CEFBS_None, // ROTR_W = 633
+ CEFBS_IsLA64, // SC_D = 634
+ CEFBS_None, // SC_W = 635
+ CEFBS_IsLA64, // SLLI_D = 636
+ CEFBS_None, // SLLI_W = 637
+ CEFBS_IsLA64, // SLL_D = 638
+ CEFBS_None, // SLL_W = 639
+ CEFBS_None, // SLT = 640
+ CEFBS_None, // SLTI = 641
+ CEFBS_None, // SLTU = 642
+ CEFBS_None, // SLTUI = 643
+ CEFBS_IsLA64, // SRAI_D = 644
+ CEFBS_None, // SRAI_W = 645
+ CEFBS_IsLA64, // SRA_D = 646
+ CEFBS_None, // SRA_W = 647
+ CEFBS_IsLA64, // SRLI_D = 648
+ CEFBS_None, // SRLI_W = 649
+ CEFBS_IsLA64, // SRL_D = 650
+ CEFBS_None, // SRL_W = 651
+ CEFBS_IsLA64, // STGT_B = 652
+ CEFBS_IsLA64, // STGT_D = 653
+ CEFBS_IsLA64, // STGT_H = 654
+ CEFBS_IsLA64, // STGT_W = 655
+ CEFBS_IsLA64, // STLE_B = 656
+ CEFBS_IsLA64, // STLE_D = 657
+ CEFBS_IsLA64, // STLE_H = 658
+ CEFBS_IsLA64, // STLE_W = 659
+ CEFBS_IsLA64, // STPTR_D = 660
+ CEFBS_IsLA64, // STPTR_W = 661
+ CEFBS_IsLA64, // STX_B = 662
+ CEFBS_IsLA64, // STX_D = 663
+ CEFBS_IsLA64, // STX_H = 664
+ CEFBS_IsLA64, // STX_W = 665
+ CEFBS_None, // ST_B = 666
+ CEFBS_IsLA64, // ST_D = 667
+ CEFBS_None, // ST_H = 668
+ CEFBS_None, // ST_W = 669
+ CEFBS_IsLA64, // SUB_D = 670
+ CEFBS_None, // SUB_W = 671
+ CEFBS_None, // SYSCALL = 672
+ CEFBS_None, // TLBCLR = 673
+ CEFBS_None, // TLBFILL = 674
+ CEFBS_None, // TLBFLUSH = 675
+ CEFBS_None, // TLBRD = 676
+ CEFBS_None, // TLBSRCH = 677
+ CEFBS_None, // TLBWR = 678
+ CEFBS_None, // XOR = 679
+ CEFBS_None, // XORI = 680
+ };
+
+ assert(Opcode < 681);
+ FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
+ const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Opcode]];
+ FeatureBitset MissingFeatures =
+ (AvailableFeatures & RequiredFeatures) ^
+ RequiredFeatures;
+ if (MissingFeatures.any()) {
+ std::ostringstream Msg;
+ Msg << "Attempting to emit " << &LoongArchInstrNameData[LoongArchInstrNameIndices[Opcode]]
+ << " instruction but the ";
+ for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
+ if (MissingFeatures.test(i))
+ Msg << SubtargetFeatureNames[i] << " ";
+ Msg << "predicate(s) are not met";
+ report_fatal_error(Msg.str().c_str());
+ }
+#endif // NDEBUG
+}
+} // end namespace LoongArch_MC
+} // end namespace llvm
+#endif // ENABLE_INSTR_PREDICATE_VERIFIER
+
diff --git a/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenMCCodeEmitter.inc b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenMCCodeEmitter.inc
new file mode 100644
index 0000000..1614eb9
--- /dev/null
+++ b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenMCCodeEmitter.inc
@@ -0,0 +1,1743 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Machine Code Emitter *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+uint64_t LoongArchMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ static const uint64_t InstBits[] = {
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(46137344), // ADDI_D
+ UINT64_C(41943040), // ADDI_W
+ UINT64_C(268435456), // ADDU16I_D
+ UINT64_C(1081344), // ADD_D
+ UINT64_C(1048576), // ADD_W
+ UINT64_C(2883584), // ALSL_D
+ UINT64_C(262144), // ALSL_W
+ UINT64_C(393216), // ALSL_WU
+ UINT64_C(945913856), // AMADD_D
+ UINT64_C(946503680), // AMADD_DB_D
+ UINT64_C(946470912), // AMADD_DB_W
+ UINT64_C(945881088), // AMADD_W
+ UINT64_C(945979392), // AMAND_D
+ UINT64_C(946569216), // AMAND_DB_D
+ UINT64_C(946536448), // AMAND_DB_W
+ UINT64_C(945946624), // AMAND_W
+ UINT64_C(946176000), // AMMAX_D
+ UINT64_C(946765824), // AMMAX_DB_D
+ UINT64_C(946896896), // AMMAX_DB_DU
+ UINT64_C(946733056), // AMMAX_DB_W
+ UINT64_C(946864128), // AMMAX_DB_WU
+ UINT64_C(946307072), // AMMAX_DU
+ UINT64_C(946143232), // AMMAX_W
+ UINT64_C(946274304), // AMMAX_WU
+ UINT64_C(946241536), // AMMIN_D
+ UINT64_C(946831360), // AMMIN_DB_D
+ UINT64_C(946962432), // AMMIN_DB_DU
+ UINT64_C(946798592), // AMMIN_DB_W
+ UINT64_C(946929664), // AMMIN_DB_WU
+ UINT64_C(946372608), // AMMIN_DU
+ UINT64_C(946208768), // AMMIN_W
+ UINT64_C(946339840), // AMMIN_WU
+ UINT64_C(946044928), // AMOR_D
+ UINT64_C(946634752), // AMOR_DB_D
+ UINT64_C(946601984), // AMOR_DB_W
+ UINT64_C(946012160), // AMOR_W
+ UINT64_C(945848320), // AMSWAP_D
+ UINT64_C(946438144), // AMSWAP_DB_D
+ UINT64_C(946405376), // AMSWAP_DB_W
+ UINT64_C(945815552), // AMSWAP_W
+ UINT64_C(946110464), // AMXOR_D
+ UINT64_C(946700288), // AMXOR_DB_D
+ UINT64_C(946667520), // AMXOR_DB_W
+ UINT64_C(946077696), // AMXOR_W
+ UINT64_C(1343488), // AND
+ UINT64_C(54525952), // ANDI
+ UINT64_C(1474560), // ANDN
+ UINT64_C(98304), // ASRTGT_D
+ UINT64_C(65536), // ASRTLE_D
+ UINT64_C(1342177280), // B
+ UINT64_C(1207959552), // BCEQZ
+ UINT64_C(1207959808), // BCNEZ
+ UINT64_C(1476395008), // BEQ
+ UINT64_C(1073741824), // BEQZ
+ UINT64_C(1677721600), // BGE
+ UINT64_C(1811939328), // BGEU
+ UINT64_C(18432), // BITREV_4B
+ UINT64_C(19456), // BITREV_8B
+ UINT64_C(21504), // BITREV_D
+ UINT64_C(20480), // BITREV_W
+ UINT64_C(1409286144), // BL
+ UINT64_C(1610612736), // BLT
+ UINT64_C(1744830464), // BLTU
+ UINT64_C(1543503872), // BNE
+ UINT64_C(1140850688), // BNEZ
+ UINT64_C(2752512), // BREAK
+ UINT64_C(8388608), // BSTRINS_D
+ UINT64_C(6291456), // BSTRINS_W
+ UINT64_C(12582912), // BSTRPICK_D
+ UINT64_C(6324224), // BSTRPICK_W
+ UINT64_C(786432), // BYTEPICK_D
+ UINT64_C(524288), // BYTEPICK_W
+ UINT64_C(100663296), // CACOP
+ UINT64_C(8192), // CLO_D
+ UINT64_C(4096), // CLO_W
+ UINT64_C(9216), // CLZ_D
+ UINT64_C(5120), // CLZ_W
+ UINT64_C(27648), // CPUCFG
+ UINT64_C(2490368), // CRCC_W_B_W
+ UINT64_C(2588672), // CRCC_W_D_W
+ UINT64_C(2523136), // CRCC_W_H_W
+ UINT64_C(2555904), // CRCC_W_W_W
+ UINT64_C(2359296), // CRC_W_B_W
+ UINT64_C(2457600), // CRC_W_D_W
+ UINT64_C(2392064), // CRC_W_H_W
+ UINT64_C(2424832), // CRC_W_W_W
+ UINT64_C(67108864), // CSRRD
+ UINT64_C(67108896), // CSRWR
+ UINT64_C(67108864), // CSRXCHG
+ UINT64_C(10240), // CTO_D
+ UINT64_C(6144), // CTO_W
+ UINT64_C(11264), // CTZ_D
+ UINT64_C(7168), // CTZ_W
+ UINT64_C(946995200), // DBAR
+ UINT64_C(2785280), // DBCL
+ UINT64_C(2228224), // DIV_D
+ UINT64_C(2293760), // DIV_DU
+ UINT64_C(2097152), // DIV_W
+ UINT64_C(2162688), // DIV_WU
+ UINT64_C(105396224), // ERTN
+ UINT64_C(23552), // EXT_W_B
+ UINT64_C(22528), // EXT_W_H
+ UINT64_C(18089984), // FABS_D
+ UINT64_C(18088960), // FABS_S
+ UINT64_C(16842752), // FADD_D
+ UINT64_C(16809984), // FADD_S
+ UINT64_C(18102272), // FCLASS_D
+ UINT64_C(18101248), // FCLASS_S
+ UINT64_C(203423744), // FCMP_CAF_D
+ UINT64_C(202375168), // FCMP_CAF_S
+ UINT64_C(203554816), // FCMP_CEQ_D
+ UINT64_C(202506240), // FCMP_CEQ_S
+ UINT64_C(203620352), // FCMP_CLE_D
+ UINT64_C(202571776), // FCMP_CLE_S
+ UINT64_C(203489280), // FCMP_CLT_D
+ UINT64_C(202440704), // FCMP_CLT_S
+ UINT64_C(203948032), // FCMP_CNE_D
+ UINT64_C(202899456), // FCMP_CNE_S
+ UINT64_C(204079104), // FCMP_COR_D
+ UINT64_C(203030528), // FCMP_COR_S
+ UINT64_C(203816960), // FCMP_CUEQ_D
+ UINT64_C(202768384), // FCMP_CUEQ_S
+ UINT64_C(203882496), // FCMP_CULE_D
+ UINT64_C(202833920), // FCMP_CULE_S
+ UINT64_C(203751424), // FCMP_CULT_D
+ UINT64_C(202702848), // FCMP_CULT_S
+ UINT64_C(204210176), // FCMP_CUNE_D
+ UINT64_C(203161600), // FCMP_CUNE_S
+ UINT64_C(203685888), // FCMP_CUN_D
+ UINT64_C(202637312), // FCMP_CUN_S
+ UINT64_C(203456512), // FCMP_SAF_D
+ UINT64_C(202407936), // FCMP_SAF_S
+ UINT64_C(203587584), // FCMP_SEQ_D
+ UINT64_C(202539008), // FCMP_SEQ_S
+ UINT64_C(203653120), // FCMP_SLE_D
+ UINT64_C(202604544), // FCMP_SLE_S
+ UINT64_C(203522048), // FCMP_SLT_D
+ UINT64_C(202473472), // FCMP_SLT_S
+ UINT64_C(203980800), // FCMP_SNE_D
+ UINT64_C(202932224), // FCMP_SNE_S
+ UINT64_C(204111872), // FCMP_SOR_D
+ UINT64_C(203063296), // FCMP_SOR_S
+ UINT64_C(203849728), // FCMP_SUEQ_D
+ UINT64_C(202801152), // FCMP_SUEQ_S
+ UINT64_C(203915264), // FCMP_SULE_D
+ UINT64_C(202866688), // FCMP_SULE_S
+ UINT64_C(203784192), // FCMP_SULT_D
+ UINT64_C(202735616), // FCMP_SULT_S
+ UINT64_C(204242944), // FCMP_SUNE_D
+ UINT64_C(203194368), // FCMP_SUNE_S
+ UINT64_C(203718656), // FCMP_SUN_D
+ UINT64_C(202670080), // FCMP_SUN_S
+ UINT64_C(18022400), // FCOPYSIGN_D
+ UINT64_C(17989632), // FCOPYSIGN_S
+ UINT64_C(18424832), // FCVT_D_S
+ UINT64_C(18421760), // FCVT_S_D
+ UINT64_C(17235968), // FDIV_D
+ UINT64_C(17203200), // FDIV_S
+ UINT64_C(18688000), // FFINT_D_L
+ UINT64_C(18685952), // FFINT_D_W
+ UINT64_C(18683904), // FFINT_S_L
+ UINT64_C(18681856), // FFINT_S_W
+ UINT64_C(947159040), // FLDGT_D
+ UINT64_C(947126272), // FLDGT_S
+ UINT64_C(947224576), // FLDLE_D
+ UINT64_C(947191808), // FLDLE_S
+ UINT64_C(942931968), // FLDX_D
+ UINT64_C(942669824), // FLDX_S
+ UINT64_C(729808896), // FLD_D
+ UINT64_C(721420288), // FLD_S
+ UINT64_C(18098176), // FLOGB_D
+ UINT64_C(18097152), // FLOGB_S
+ UINT64_C(136314880), // FMADD_D
+ UINT64_C(135266304), // FMADD_S
+ UINT64_C(17629184), // FMAXA_D
+ UINT64_C(17596416), // FMAXA_S
+ UINT64_C(17367040), // FMAX_D
+ UINT64_C(17334272), // FMAX_S
+ UINT64_C(17760256), // FMINA_D
+ UINT64_C(17727488), // FMINA_S
+ UINT64_C(17498112), // FMIN_D
+ UINT64_C(17465344), // FMIN_S
+ UINT64_C(18126848), // FMOV_D
+ UINT64_C(18125824), // FMOV_S
+ UINT64_C(140509184), // FMSUB_D
+ UINT64_C(139460608), // FMSUB_S
+ UINT64_C(17104896), // FMUL_D
+ UINT64_C(17072128), // FMUL_S
+ UINT64_C(18094080), // FNEG_D
+ UINT64_C(18093056), // FNEG_S
+ UINT64_C(144703488), // FNMADD_D
+ UINT64_C(143654912), // FNMADD_S
+ UINT64_C(148897792), // FNMSUB_D
+ UINT64_C(147849216), // FNMSUB_S
+ UINT64_C(18110464), // FRECIP_D
+ UINT64_C(18109440), // FRECIP_S
+ UINT64_C(18761728), // FRINT_D
+ UINT64_C(18760704), // FRINT_S
+ UINT64_C(18114560), // FRSQRT_D
+ UINT64_C(18113536), // FRSQRT_S
+ UINT64_C(17891328), // FSCALEB_D
+ UINT64_C(17858560), // FSCALEB_S
+ UINT64_C(218103808), // FSEL_D
+ UINT64_C(218103808), // FSEL_S
+ UINT64_C(18106368), // FSQRT_D
+ UINT64_C(18105344), // FSQRT_S
+ UINT64_C(947290112), // FSTGT_D
+ UINT64_C(947257344), // FSTGT_S
+ UINT64_C(947355648), // FSTLE_D
+ UINT64_C(947322880), // FSTLE_S
+ UINT64_C(943456256), // FSTX_D
+ UINT64_C(943194112), // FSTX_S
+ UINT64_C(734003200), // FST_D
+ UINT64_C(725614592), // FST_S
+ UINT64_C(16973824), // FSUB_D
+ UINT64_C(16941056), // FSUB_S
+ UINT64_C(18491392), // FTINTRM_L_D
+ UINT64_C(18490368), // FTINTRM_L_S
+ UINT64_C(18483200), // FTINTRM_W_D
+ UINT64_C(18482176), // FTINTRM_W_S
+ UINT64_C(18540544), // FTINTRNE_L_D
+ UINT64_C(18539520), // FTINTRNE_L_S
+ UINT64_C(18532352), // FTINTRNE_W_D
+ UINT64_C(18531328), // FTINTRNE_W_S
+ UINT64_C(18507776), // FTINTRP_L_D
+ UINT64_C(18506752), // FTINTRP_L_S
+ UINT64_C(18499584), // FTINTRP_W_D
+ UINT64_C(18498560), // FTINTRP_W_S
+ UINT64_C(18524160), // FTINTRZ_L_D
+ UINT64_C(18523136), // FTINTRZ_L_S
+ UINT64_C(18515968), // FTINTRZ_W_D
+ UINT64_C(18514944), // FTINTRZ_W_S
+ UINT64_C(18556928), // FTINT_L_D
+ UINT64_C(18555904), // FTINT_L_S
+ UINT64_C(18548736), // FTINT_W_D
+ UINT64_C(18547712), // FTINT_W_S
+ UINT64_C(947027968), // IBAR
+ UINT64_C(105414656), // IDLE
+ UINT64_C(105480192), // INVTLB
+ UINT64_C(105381888), // IOCSRRD_B
+ UINT64_C(105384960), // IOCSRRD_D
+ UINT64_C(105382912), // IOCSRRD_H
+ UINT64_C(105383936), // IOCSRRD_W
+ UINT64_C(105385984), // IOCSRWR_B
+ UINT64_C(105389056), // IOCSRWR_D
+ UINT64_C(105387008), // IOCSRWR_H
+ UINT64_C(105388032), // IOCSRWR_W
+ UINT64_C(1275068416), // JIRL
+ UINT64_C(104857600), // LDDIR
+ UINT64_C(947388416), // LDGT_B
+ UINT64_C(947486720), // LDGT_D
+ UINT64_C(947421184), // LDGT_H
+ UINT64_C(947453952), // LDGT_W
+ UINT64_C(947519488), // LDLE_B
+ UINT64_C(947617792), // LDLE_D
+ UINT64_C(947552256), // LDLE_H
+ UINT64_C(947585024), // LDLE_W
+ UINT64_C(105119744), // LDPTE
+ UINT64_C(637534208), // LDPTR_D
+ UINT64_C(603979776), // LDPTR_W
+ UINT64_C(939524096), // LDX_B
+ UINT64_C(941621248), // LDX_BU
+ UINT64_C(940310528), // LDX_D
+ UINT64_C(939786240), // LDX_H
+ UINT64_C(941883392), // LDX_HU
+ UINT64_C(940048384), // LDX_W
+ UINT64_C(942145536), // LDX_WU
+ UINT64_C(671088640), // LD_B
+ UINT64_C(704643072), // LD_BU
+ UINT64_C(683671552), // LD_D
+ UINT64_C(675282944), // LD_H
+ UINT64_C(708837376), // LD_HU
+ UINT64_C(679477248), // LD_W
+ UINT64_C(713031680), // LD_WU
+ UINT64_C(570425344), // LL_D
+ UINT64_C(536870912), // LL_W
+ UINT64_C(335544320), // LU12I_W
+ UINT64_C(369098752), // LU32I_D
+ UINT64_C(50331648), // LU52I_D
+ UINT64_C(1245184), // MASKEQZ
+ UINT64_C(1277952), // MASKNEZ
+ UINT64_C(2260992), // MOD_D
+ UINT64_C(2326528), // MOD_DU
+ UINT64_C(2129920), // MOD_W
+ UINT64_C(2195456), // MOD_WU
+ UINT64_C(18142208), // MOVCF2FR_S
+ UINT64_C(18144256), // MOVCF2GR
+ UINT64_C(18139136), // MOVFCSR2GR
+ UINT64_C(18141184), // MOVFR2CF_S
+ UINT64_C(18135040), // MOVFR2GR_D
+ UINT64_C(18134016), // MOVFR2GR_S
+ UINT64_C(18134016), // MOVFR2GR_S_64
+ UINT64_C(18136064), // MOVFRH2GR_S
+ UINT64_C(18143232), // MOVGR2CF
+ UINT64_C(18137088), // MOVGR2FCSR
+ UINT64_C(18131968), // MOVGR2FRH_W
+ UINT64_C(18130944), // MOVGR2FR_D
+ UINT64_C(18129920), // MOVGR2FR_W
+ UINT64_C(18129920), // MOVGR2FR_W_64
+ UINT64_C(1966080), // MULH_D
+ UINT64_C(1998848), // MULH_DU
+ UINT64_C(1867776), // MULH_W
+ UINT64_C(1900544), // MULH_WU
+ UINT64_C(2031616), // MULW_D_W
+ UINT64_C(2064384), // MULW_D_WU
+ UINT64_C(1933312), // MUL_D
+ UINT64_C(1835008), // MUL_W
+ UINT64_C(1310720), // NOR
+ UINT64_C(1376256), // OR
+ UINT64_C(58720256), // ORI
+ UINT64_C(1441792), // ORN
+ UINT64_C(402653184), // PCADDI
+ UINT64_C(469762048), // PCADDU12I
+ UINT64_C(503316480), // PCADDU18I
+ UINT64_C(436207616), // PCALAU12I
+ UINT64_C(717225984), // PRELD
+ UINT64_C(942407680), // PRELDX
+ UINT64_C(25600), // RDTIMEH_W
+ UINT64_C(24576), // RDTIMEL_W
+ UINT64_C(26624), // RDTIME_D
+ UINT64_C(12288), // REVB_2H
+ UINT64_C(14336), // REVB_2W
+ UINT64_C(13312), // REVB_4H
+ UINT64_C(15360), // REVB_D
+ UINT64_C(16384), // REVH_2W
+ UINT64_C(17408), // REVH_D
+ UINT64_C(5046272), // ROTRI_D
+ UINT64_C(5013504), // ROTRI_W
+ UINT64_C(1802240), // ROTR_D
+ UINT64_C(1769472), // ROTR_W
+ UINT64_C(587202560), // SC_D
+ UINT64_C(553648128), // SC_W
+ UINT64_C(4259840), // SLLI_D
+ UINT64_C(4227072), // SLLI_W
+ UINT64_C(1605632), // SLL_D
+ UINT64_C(1507328), // SLL_W
+ UINT64_C(1179648), // SLT
+ UINT64_C(33554432), // SLTI
+ UINT64_C(1212416), // SLTU
+ UINT64_C(37748736), // SLTUI
+ UINT64_C(4784128), // SRAI_D
+ UINT64_C(4751360), // SRAI_W
+ UINT64_C(1671168), // SRA_D
+ UINT64_C(1572864), // SRA_W
+ UINT64_C(4521984), // SRLI_D
+ UINT64_C(4489216), // SRLI_W
+ UINT64_C(1638400), // SRL_D
+ UINT64_C(1540096), // SRL_W
+ UINT64_C(947650560), // STGT_B
+ UINT64_C(947748864), // STGT_D
+ UINT64_C(947683328), // STGT_H
+ UINT64_C(947716096), // STGT_W
+ UINT64_C(947781632), // STLE_B
+ UINT64_C(947879936), // STLE_D
+ UINT64_C(947814400), // STLE_H
+ UINT64_C(947847168), // STLE_W
+ UINT64_C(654311424), // STPTR_D
+ UINT64_C(620756992), // STPTR_W
+ UINT64_C(940572672), // STX_B
+ UINT64_C(941359104), // STX_D
+ UINT64_C(940834816), // STX_H
+ UINT64_C(941096960), // STX_W
+ UINT64_C(687865856), // ST_B
+ UINT64_C(700448768), // ST_D
+ UINT64_C(692060160), // ST_H
+ UINT64_C(696254464), // ST_W
+ UINT64_C(1146880), // SUB_D
+ UINT64_C(1114112), // SUB_W
+ UINT64_C(2818048), // SYSCALL
+ UINT64_C(105390080), // TLBCLR
+ UINT64_C(105395200), // TLBFILL
+ UINT64_C(105391104), // TLBFLUSH
+ UINT64_C(105393152), // TLBRD
+ UINT64_C(105392128), // TLBSRCH
+ UINT64_C(105394176), // TLBWR
+ UINT64_C(1409024), // XOR
+ UINT64_C(62914560), // XORI
+ UINT64_C(0)
+ };
+ const unsigned opcode = MI.getOpcode();
+ uint64_t Value = InstBits[opcode];
+ uint64_t op = 0;
+ (void)op; // suppress warning
+ switch (opcode) {
+ case LoongArch::ERTN:
+ case LoongArch::TLBCLR:
+ case LoongArch::TLBFILL:
+ case LoongArch::TLBFLUSH:
+ case LoongArch::TLBRD:
+ case LoongArch::TLBSRCH:
+ case LoongArch::TLBWR: {
+ break;
+ }
+ case LoongArch::FSEL_D:
+ case LoongArch::FSEL_S: {
+ // op: ca
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 15;
+ Value |= op;
+ // op: fk
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: fj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::CSRRD: {
+ // op: csr_num
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(16383);
+ op <<= 10;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::CSRWR: {
+ // op: csr_num
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(16383);
+ op <<= 10;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::CSRXCHG: {
+ // op: csr_num
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ op &= UINT64_C(16383);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::FMADD_D:
+ case LoongArch::FMADD_S:
+ case LoongArch::FMSUB_D:
+ case LoongArch::FMSUB_S:
+ case LoongArch::FNMADD_D:
+ case LoongArch::FNMADD_S:
+ case LoongArch::FNMSUB_D:
+ case LoongArch::FNMSUB_S: {
+ // op: fa
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 15;
+ Value |= op;
+ // op: fk
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: fj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::FABS_D:
+ case LoongArch::FABS_S:
+ case LoongArch::FCLASS_D:
+ case LoongArch::FCLASS_S:
+ case LoongArch::FCVT_D_S:
+ case LoongArch::FCVT_S_D:
+ case LoongArch::FFINT_D_L:
+ case LoongArch::FFINT_D_W:
+ case LoongArch::FFINT_S_L:
+ case LoongArch::FFINT_S_W:
+ case LoongArch::FLOGB_D:
+ case LoongArch::FLOGB_S:
+ case LoongArch::FNEG_D:
+ case LoongArch::FNEG_S:
+ case LoongArch::FRECIP_D:
+ case LoongArch::FRECIP_S:
+ case LoongArch::FRINT_D:
+ case LoongArch::FRINT_S:
+ case LoongArch::FRSQRT_D:
+ case LoongArch::FRSQRT_S:
+ case LoongArch::FSQRT_D:
+ case LoongArch::FSQRT_S:
+ case LoongArch::FTINTRM_L_D:
+ case LoongArch::FTINTRM_L_S:
+ case LoongArch::FTINTRM_W_D:
+ case LoongArch::FTINTRM_W_S:
+ case LoongArch::FTINTRNE_L_D:
+ case LoongArch::FTINTRNE_L_S:
+ case LoongArch::FTINTRNE_W_D:
+ case LoongArch::FTINTRNE_W_S:
+ case LoongArch::FTINTRP_L_D:
+ case LoongArch::FTINTRP_L_S:
+ case LoongArch::FTINTRP_W_D:
+ case LoongArch::FTINTRP_W_S:
+ case LoongArch::FTINTRZ_L_D:
+ case LoongArch::FTINTRZ_L_S:
+ case LoongArch::FTINTRZ_W_D:
+ case LoongArch::FTINTRZ_W_S:
+ case LoongArch::FTINT_L_D:
+ case LoongArch::FTINT_L_S:
+ case LoongArch::FTINT_W_D:
+ case LoongArch::FTINT_W_S: {
+ // op: fj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::FCMP_CAF_D:
+ case LoongArch::FCMP_CAF_S:
+ case LoongArch::FCMP_CEQ_D:
+ case LoongArch::FCMP_CEQ_S:
+ case LoongArch::FCMP_CLE_D:
+ case LoongArch::FCMP_CLE_S:
+ case LoongArch::FCMP_CLT_D:
+ case LoongArch::FCMP_CLT_S:
+ case LoongArch::FCMP_CNE_D:
+ case LoongArch::FCMP_CNE_S:
+ case LoongArch::FCMP_COR_D:
+ case LoongArch::FCMP_COR_S:
+ case LoongArch::FCMP_CUEQ_D:
+ case LoongArch::FCMP_CUEQ_S:
+ case LoongArch::FCMP_CULE_D:
+ case LoongArch::FCMP_CULE_S:
+ case LoongArch::FCMP_CULT_D:
+ case LoongArch::FCMP_CULT_S:
+ case LoongArch::FCMP_CUNE_D:
+ case LoongArch::FCMP_CUNE_S:
+ case LoongArch::FCMP_CUN_D:
+ case LoongArch::FCMP_CUN_S:
+ case LoongArch::FCMP_SAF_D:
+ case LoongArch::FCMP_SAF_S:
+ case LoongArch::FCMP_SEQ_D:
+ case LoongArch::FCMP_SEQ_S:
+ case LoongArch::FCMP_SLE_D:
+ case LoongArch::FCMP_SLE_S:
+ case LoongArch::FCMP_SLT_D:
+ case LoongArch::FCMP_SLT_S:
+ case LoongArch::FCMP_SNE_D:
+ case LoongArch::FCMP_SNE_S:
+ case LoongArch::FCMP_SOR_D:
+ case LoongArch::FCMP_SOR_S:
+ case LoongArch::FCMP_SUEQ_D:
+ case LoongArch::FCMP_SUEQ_S:
+ case LoongArch::FCMP_SULE_D:
+ case LoongArch::FCMP_SULE_S:
+ case LoongArch::FCMP_SULT_D:
+ case LoongArch::FCMP_SULT_S:
+ case LoongArch::FCMP_SUNE_D:
+ case LoongArch::FCMP_SUNE_S:
+ case LoongArch::FCMP_SUN_D:
+ case LoongArch::FCMP_SUN_S: {
+ // op: fk
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: fj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: cd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(7);
+ Value |= op;
+ break;
+ }
+ case LoongArch::FADD_D:
+ case LoongArch::FADD_S:
+ case LoongArch::FCOPYSIGN_D:
+ case LoongArch::FCOPYSIGN_S:
+ case LoongArch::FDIV_D:
+ case LoongArch::FDIV_S:
+ case LoongArch::FMAXA_D:
+ case LoongArch::FMAXA_S:
+ case LoongArch::FMAX_D:
+ case LoongArch::FMAX_S:
+ case LoongArch::FMINA_D:
+ case LoongArch::FMINA_S:
+ case LoongArch::FMIN_D:
+ case LoongArch::FMIN_S:
+ case LoongArch::FMUL_D:
+ case LoongArch::FMUL_S:
+ case LoongArch::FSCALEB_D:
+ case LoongArch::FSCALEB_S:
+ case LoongArch::FSUB_D:
+ case LoongArch::FSUB_S: {
+ // op: fk
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: fj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::FLD_D:
+ case LoongArch::FLD_S:
+ case LoongArch::FST_D:
+ case LoongArch::FST_S: {
+ // op: imm12
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(4095);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::PRELD: {
+ // op: imm12
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(4095);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: imm5
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::CACOP: {
+ // op: imm12
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(4095);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: op
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::ADDI_D:
+ case LoongArch::ADDI_W:
+ case LoongArch::ANDI:
+ case LoongArch::LD_B:
+ case LoongArch::LD_BU:
+ case LoongArch::LD_D:
+ case LoongArch::LD_H:
+ case LoongArch::LD_HU:
+ case LoongArch::LD_W:
+ case LoongArch::LD_WU:
+ case LoongArch::LU52I_D:
+ case LoongArch::ORI:
+ case LoongArch::SLTI:
+ case LoongArch::SLTUI:
+ case LoongArch::ST_B:
+ case LoongArch::ST_D:
+ case LoongArch::ST_H:
+ case LoongArch::ST_W:
+ case LoongArch::XORI: {
+ // op: imm12
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(4095);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::LDPTR_D:
+ case LoongArch::LDPTR_W:
+ case LoongArch::LL_D:
+ case LoongArch::LL_W:
+ case LoongArch::STPTR_D:
+ case LoongArch::STPTR_W: {
+ // op: imm14
+ op = getImmOpValueAsr2(MI, 2, Fixups, STI);
+ op &= UINT64_C(16383);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::SC_D:
+ case LoongArch::SC_W: {
+ // op: imm14
+ op = getImmOpValueAsr2(MI, 3, Fixups, STI);
+ op &= UINT64_C(16383);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::BREAK:
+ case LoongArch::DBAR:
+ case LoongArch::DBCL:
+ case LoongArch::IBAR:
+ case LoongArch::IDLE:
+ case LoongArch::SYSCALL: {
+ // op: imm15
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(32767);
+ Value |= op;
+ break;
+ }
+ case LoongArch::BEQ:
+ case LoongArch::BGE:
+ case LoongArch::BGEU:
+ case LoongArch::BLT:
+ case LoongArch::BLTU:
+ case LoongArch::BNE: {
+ // op: imm16
+ op = getImmOpValueAsr2(MI, 2, Fixups, STI);
+ op &= UINT64_C(65535);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::JIRL: {
+ // op: imm16
+ op = getImmOpValueAsr2(MI, 2, Fixups, STI);
+ op &= UINT64_C(65535);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::ADDU16I_D: {
+ // op: imm16
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(65535);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::ALSL_D:
+ case LoongArch::ALSL_W:
+ case LoongArch::ALSL_WU: {
+ // op: imm2
+ op = getImmOpValueSub1(MI, 3, Fixups, STI);
+ op &= UINT64_C(3);
+ op <<= 15;
+ Value |= op;
+ // op: rk
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::BYTEPICK_W: {
+ // op: imm2
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ op &= UINT64_C(3);
+ op <<= 15;
+ Value |= op;
+ // op: rk
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::LU12I_W:
+ case LoongArch::PCADDI:
+ case LoongArch::PCADDU12I:
+ case LoongArch::PCADDU18I:
+ case LoongArch::PCALAU12I: {
+ // op: imm20
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(1048575);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::LU32I_D: {
+ // op: imm20
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(1048575);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::BCEQZ:
+ case LoongArch::BCNEZ: {
+ // op: imm21
+ op = getImmOpValueAsr2(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(65535)) << 10;
+ Value |= (op & UINT64_C(2031616)) >> 16;
+ // op: cj
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 5;
+ Value |= op;
+ break;
+ }
+ case LoongArch::BEQZ:
+ case LoongArch::BNEZ: {
+ // op: imm21
+ op = getImmOpValueAsr2(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(65535)) << 10;
+ Value |= (op & UINT64_C(2031616)) >> 16;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ break;
+ }
+ case LoongArch::B:
+ case LoongArch::BL: {
+ // op: imm26
+ op = getImmOpValueAsr2(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(65535)) << 10;
+ Value |= (op & UINT64_C(67043328)) >> 16;
+ break;
+ }
+ case LoongArch::BYTEPICK_D: {
+ // op: imm3
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 15;
+ Value |= op;
+ // op: rk
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::ROTRI_W:
+ case LoongArch::SLLI_W:
+ case LoongArch::SRAI_W:
+ case LoongArch::SRLI_W: {
+ // op: imm5
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::ROTRI_D:
+ case LoongArch::SLLI_D:
+ case LoongArch::SRAI_D:
+ case LoongArch::SRLI_D: {
+ // op: imm6
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(63);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::LDDIR: {
+ // op: imm8
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(255);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::BSTRPICK_D: {
+ // op: msbd
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(63);
+ op <<= 16;
+ Value |= op;
+ // op: lsbd
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ op &= UINT64_C(63);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::BSTRINS_D: {
+ // op: msbd
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ op &= UINT64_C(63);
+ op <<= 16;
+ Value |= op;
+ // op: lsbd
+ op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
+ op &= UINT64_C(63);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::BSTRPICK_W: {
+ // op: msbw
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 16;
+ Value |= op;
+ // op: lsbw
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::BSTRINS_W: {
+ // op: msbw
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 16;
+ Value |= op;
+ // op: lsbw
+ op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::BITREV_4B:
+ case LoongArch::BITREV_8B:
+ case LoongArch::BITREV_D:
+ case LoongArch::BITREV_W:
+ case LoongArch::CLO_D:
+ case LoongArch::CLO_W:
+ case LoongArch::CLZ_D:
+ case LoongArch::CLZ_W:
+ case LoongArch::CPUCFG:
+ case LoongArch::CTO_D:
+ case LoongArch::CTO_W:
+ case LoongArch::CTZ_D:
+ case LoongArch::CTZ_W:
+ case LoongArch::EXT_W_B:
+ case LoongArch::EXT_W_H:
+ case LoongArch::IOCSRRD_B:
+ case LoongArch::IOCSRRD_D:
+ case LoongArch::IOCSRRD_H:
+ case LoongArch::IOCSRRD_W:
+ case LoongArch::IOCSRWR_B:
+ case LoongArch::IOCSRWR_D:
+ case LoongArch::IOCSRWR_H:
+ case LoongArch::IOCSRWR_W:
+ case LoongArch::RDTIMEH_W:
+ case LoongArch::RDTIMEL_W:
+ case LoongArch::RDTIME_D:
+ case LoongArch::REVB_2H:
+ case LoongArch::REVB_2W:
+ case LoongArch::REVB_4H:
+ case LoongArch::REVB_D:
+ case LoongArch::REVH_2W:
+ case LoongArch::REVH_D: {
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::INVTLB: {
+ // op: rk
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: op
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::ASRTGT_D:
+ case LoongArch::ASRTLE_D: {
+ // op: rk
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ break;
+ }
+ case LoongArch::AMADD_D:
+ case LoongArch::AMADD_DB_D:
+ case LoongArch::AMADD_DB_W:
+ case LoongArch::AMADD_W:
+ case LoongArch::AMAND_D:
+ case LoongArch::AMAND_DB_D:
+ case LoongArch::AMAND_DB_W:
+ case LoongArch::AMAND_W:
+ case LoongArch::AMMAX_D:
+ case LoongArch::AMMAX_DB_D:
+ case LoongArch::AMMAX_DB_DU:
+ case LoongArch::AMMAX_DB_W:
+ case LoongArch::AMMAX_DB_WU:
+ case LoongArch::AMMAX_DU:
+ case LoongArch::AMMAX_W:
+ case LoongArch::AMMAX_WU:
+ case LoongArch::AMMIN_D:
+ case LoongArch::AMMIN_DB_D:
+ case LoongArch::AMMIN_DB_DU:
+ case LoongArch::AMMIN_DB_W:
+ case LoongArch::AMMIN_DB_WU:
+ case LoongArch::AMMIN_DU:
+ case LoongArch::AMMIN_W:
+ case LoongArch::AMMIN_WU:
+ case LoongArch::AMOR_D:
+ case LoongArch::AMOR_DB_D:
+ case LoongArch::AMOR_DB_W:
+ case LoongArch::AMOR_W:
+ case LoongArch::AMSWAP_D:
+ case LoongArch::AMSWAP_DB_D:
+ case LoongArch::AMSWAP_DB_W:
+ case LoongArch::AMSWAP_W:
+ case LoongArch::AMXOR_D:
+ case LoongArch::AMXOR_DB_D:
+ case LoongArch::AMXOR_DB_W:
+ case LoongArch::AMXOR_W: {
+ // op: rk
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::FLDGT_D:
+ case LoongArch::FLDGT_S:
+ case LoongArch::FLDLE_D:
+ case LoongArch::FLDLE_S:
+ case LoongArch::FLDX_D:
+ case LoongArch::FLDX_S:
+ case LoongArch::FSTGT_D:
+ case LoongArch::FSTGT_S:
+ case LoongArch::FSTLE_D:
+ case LoongArch::FSTLE_S:
+ case LoongArch::FSTX_D:
+ case LoongArch::FSTX_S: {
+ // op: rk
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::PRELDX: {
+ // op: rk
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: imm5
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::ADD_D:
+ case LoongArch::ADD_W:
+ case LoongArch::AND:
+ case LoongArch::ANDN:
+ case LoongArch::CRCC_W_B_W:
+ case LoongArch::CRCC_W_D_W:
+ case LoongArch::CRCC_W_H_W:
+ case LoongArch::CRCC_W_W_W:
+ case LoongArch::CRC_W_B_W:
+ case LoongArch::CRC_W_D_W:
+ case LoongArch::CRC_W_H_W:
+ case LoongArch::CRC_W_W_W:
+ case LoongArch::DIV_D:
+ case LoongArch::DIV_DU:
+ case LoongArch::DIV_W:
+ case LoongArch::DIV_WU:
+ case LoongArch::LDGT_B:
+ case LoongArch::LDGT_D:
+ case LoongArch::LDGT_H:
+ case LoongArch::LDGT_W:
+ case LoongArch::LDLE_B:
+ case LoongArch::LDLE_D:
+ case LoongArch::LDLE_H:
+ case LoongArch::LDLE_W:
+ case LoongArch::LDX_B:
+ case LoongArch::LDX_BU:
+ case LoongArch::LDX_D:
+ case LoongArch::LDX_H:
+ case LoongArch::LDX_HU:
+ case LoongArch::LDX_W:
+ case LoongArch::LDX_WU:
+ case LoongArch::MASKEQZ:
+ case LoongArch::MASKNEZ:
+ case LoongArch::MOD_D:
+ case LoongArch::MOD_DU:
+ case LoongArch::MOD_W:
+ case LoongArch::MOD_WU:
+ case LoongArch::MULH_D:
+ case LoongArch::MULH_DU:
+ case LoongArch::MULH_W:
+ case LoongArch::MULH_WU:
+ case LoongArch::MULW_D_W:
+ case LoongArch::MULW_D_WU:
+ case LoongArch::MUL_D:
+ case LoongArch::MUL_W:
+ case LoongArch::NOR:
+ case LoongArch::OR:
+ case LoongArch::ORN:
+ case LoongArch::ROTR_D:
+ case LoongArch::ROTR_W:
+ case LoongArch::SLL_D:
+ case LoongArch::SLL_W:
+ case LoongArch::SLT:
+ case LoongArch::SLTU:
+ case LoongArch::SRA_D:
+ case LoongArch::SRA_W:
+ case LoongArch::SRL_D:
+ case LoongArch::SRL_W:
+ case LoongArch::STGT_B:
+ case LoongArch::STGT_D:
+ case LoongArch::STGT_H:
+ case LoongArch::STGT_W:
+ case LoongArch::STLE_B:
+ case LoongArch::STLE_D:
+ case LoongArch::STLE_H:
+ case LoongArch::STLE_W:
+ case LoongArch::STX_B:
+ case LoongArch::STX_D:
+ case LoongArch::STX_H:
+ case LoongArch::STX_W:
+ case LoongArch::SUB_D:
+ case LoongArch::SUB_W:
+ case LoongArch::XOR: {
+ // op: rk
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::LDPTE: {
+ // op: seq
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(255);
+ op <<= 10;
+ Value |= op;
+ // op: rj
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ break;
+ }
+ case LoongArch::FMOV_D:
+ case LoongArch::FMOV_S:
+ case LoongArch::MOVCF2FR_S:
+ case LoongArch::MOVCF2GR:
+ case LoongArch::MOVFCSR2GR:
+ case LoongArch::MOVFR2CF_S:
+ case LoongArch::MOVFR2GR_D:
+ case LoongArch::MOVFR2GR_S:
+ case LoongArch::MOVFR2GR_S_64:
+ case LoongArch::MOVFRH2GR_S:
+ case LoongArch::MOVGR2CF:
+ case LoongArch::MOVGR2FCSR:
+ case LoongArch::MOVGR2FR_D:
+ case LoongArch::MOVGR2FR_W:
+ case LoongArch::MOVGR2FR_W_64: {
+ // op: src
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: dst
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ case LoongArch::MOVGR2FRH_W: {
+ // op: src
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 5;
+ Value |= op;
+ // op: dst
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ Value |= op;
+ break;
+ }
+ default:
+ std::string msg;
+ raw_string_ostream Msg(msg);
+ Msg << "Not supported instr: " << MI;
+ report_fatal_error(Msg.str().c_str());
+ }
+ return Value;
+}
+
diff --git a/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenMCPseudoLowering.inc b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenMCPseudoLowering.inc
new file mode 100644
index 0000000..e3956b8
--- /dev/null
+++ b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenMCPseudoLowering.inc
@@ -0,0 +1,166 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Pseudo-instruction MC lowering Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+bool LoongArchAsmPrinter::
+emitPseudoExpansionLowering(MCStreamer &OutStreamer,
+ const MachineInstr *MI) {
+ switch (MI->getOpcode()) {
+ default: return false;
+ case LoongArch::PseudoAtomicStoreD: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(LoongArch::AMSWAP_DB_D);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(LoongArch::R0));
+ // Operand: rk
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rj
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case LoongArch::PseudoAtomicStoreW: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(LoongArch::AMSWAP_DB_W);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(LoongArch::R0));
+ // Operand: rk
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rj
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case LoongArch::PseudoBR: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(LoongArch::B);
+ // Operand: imm26
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case LoongArch::PseudoBRIND: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(LoongArch::JIRL);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(LoongArch::R0));
+ // Operand: rj
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: imm16
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case LoongArch::PseudoB_TAIL: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(LoongArch::B);
+ // Operand: imm26
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case LoongArch::PseudoCALLIndirect: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(LoongArch::JIRL);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(LoongArch::R1));
+ // Operand: rj
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: imm16
+ TmpInst.addOperand(MCOperand::createImm(0));
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case LoongArch::PseudoJIRL_CALL: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(LoongArch::JIRL);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(LoongArch::R1));
+ // Operand: rj
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: imm16
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case LoongArch::PseudoJIRL_TAIL: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(LoongArch::JIRL);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(LoongArch::R0));
+ // Operand: rj
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: imm16
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case LoongArch::PseudoRET: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(LoongArch::JIRL);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(LoongArch::R0));
+ // Operand: rj
+ TmpInst.addOperand(MCOperand::createReg(LoongArch::R1));
+ // Operand: imm16
+ TmpInst.addOperand(MCOperand::createImm(0));
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case LoongArch::PseudoTAILIndirect: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(LoongArch::JIRL);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(LoongArch::R0));
+ // Operand: rj
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: imm16
+ TmpInst.addOperand(MCOperand::createImm(0));
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case LoongArch::PseudoUNIMP: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(LoongArch::AMSWAP_W);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(LoongArch::R0));
+ // Operand: rk
+ TmpInst.addOperand(MCOperand::createReg(LoongArch::R1));
+ // Operand: rj
+ TmpInst.addOperand(MCOperand::createReg(LoongArch::R0));
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ }
+ return true;
+}
+
diff --git a/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenRegisterInfo.inc b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenRegisterInfo.inc
new file mode 100644
index 0000000..eb0ee48
--- /dev/null
+++ b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenRegisterInfo.inc
@@ -0,0 +1,1676 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Target Register Enum Values *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+namespace llvm {
+
+class MCRegisterClass;
+extern const MCRegisterClass LoongArchMCRegisterClasses[];
+
+namespace LoongArch {
+enum {
+ NoRegister,
+ F0 = 1,
+ F1 = 2,
+ F2 = 3,
+ F3 = 4,
+ F4 = 5,
+ F5 = 6,
+ F6 = 7,
+ F7 = 8,
+ F8 = 9,
+ F9 = 10,
+ F10 = 11,
+ F11 = 12,
+ F12 = 13,
+ F13 = 14,
+ F14 = 15,
+ F15 = 16,
+ F16 = 17,
+ F17 = 18,
+ F18 = 19,
+ F19 = 20,
+ F20 = 21,
+ F21 = 22,
+ F22 = 23,
+ F23 = 24,
+ F24 = 25,
+ F25 = 26,
+ F26 = 27,
+ F27 = 28,
+ F28 = 29,
+ F29 = 30,
+ F30 = 31,
+ F31 = 32,
+ FCC0 = 33,
+ FCC1 = 34,
+ FCC2 = 35,
+ FCC3 = 36,
+ FCC4 = 37,
+ FCC5 = 38,
+ FCC6 = 39,
+ FCC7 = 40,
+ FCSR0 = 41,
+ FCSR1 = 42,
+ FCSR2 = 43,
+ FCSR3 = 44,
+ R0 = 45,
+ R1 = 46,
+ R2 = 47,
+ R3 = 48,
+ R4 = 49,
+ R5 = 50,
+ R6 = 51,
+ R7 = 52,
+ R8 = 53,
+ R9 = 54,
+ R10 = 55,
+ R11 = 56,
+ R12 = 57,
+ R13 = 58,
+ R14 = 59,
+ R15 = 60,
+ R16 = 61,
+ R17 = 62,
+ R18 = 63,
+ R19 = 64,
+ R20 = 65,
+ R21 = 66,
+ R22 = 67,
+ R23 = 68,
+ R24 = 69,
+ R25 = 70,
+ R26 = 71,
+ R27 = 72,
+ R28 = 73,
+ R29 = 74,
+ R30 = 75,
+ R31 = 76,
+ F0_64 = 77,
+ F1_64 = 78,
+ F2_64 = 79,
+ F3_64 = 80,
+ F4_64 = 81,
+ F5_64 = 82,
+ F6_64 = 83,
+ F7_64 = 84,
+ F8_64 = 85,
+ F9_64 = 86,
+ F10_64 = 87,
+ F11_64 = 88,
+ F12_64 = 89,
+ F13_64 = 90,
+ F14_64 = 91,
+ F15_64 = 92,
+ F16_64 = 93,
+ F17_64 = 94,
+ F18_64 = 95,
+ F19_64 = 96,
+ F20_64 = 97,
+ F21_64 = 98,
+ F22_64 = 99,
+ F23_64 = 100,
+ F24_64 = 101,
+ F25_64 = 102,
+ F26_64 = 103,
+ F27_64 = 104,
+ F28_64 = 105,
+ F29_64 = 106,
+ F30_64 = 107,
+ F31_64 = 108,
+ NUM_TARGET_REGS // 109
+};
+} // end namespace LoongArch
+
+// Register classes
+
+namespace LoongArch {
+enum {
+ FPR32RegClassID = 0,
+ GPRRegClassID = 1,
+ GPRTRegClassID = 2,
+ CFRRegClassID = 3,
+ FCSRRegClassID = 4,
+ FPR64RegClassID = 5,
+
+};
+} // end namespace LoongArch
+
+
+// Register alternate name indices
+
+namespace LoongArch {
+enum {
+ NoRegAltName, // 0
+ RegAliasName, // 1
+ NUM_TARGET_REG_ALT_NAMES = 2
+};
+} // end namespace LoongArch
+
+
+// Subregister indices
+
+namespace LoongArch {
+enum : uint16_t {
+ NoSubRegister,
+ sub_32, // 1
+ NUM_TARGET_SUBREGS
+};
+} // end namespace LoongArch
+
+// Register pressure sets enum.
+namespace LoongArch {
+enum RegisterPressureSets {
+ CFR = 0,
+ GPRT = 1,
+ FPR32 = 2,
+ GPR = 3,
+};
+} // end namespace LoongArch
+
+} // end namespace llvm
+
+#endif // GET_REGINFO_ENUM
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* MC Register Information *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+namespace llvm {
+
+extern const MCPhysReg LoongArchRegDiffLists[] = {
+ /* 0 */ 76, 0,
+ /* 2 */ 65459, 0,
+ /* 4 */ 65460, 0,
+ /* 6 */ 65535, 0,
+};
+
+extern const LaneBitmask LoongArchLaneMaskLists[] = {
+ /* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),
+ /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
+};
+
+extern const uint16_t LoongArchSubRegIdxLists[] = {
+ /* 0 */ 1, 0,
+};
+
+extern const MCRegisterInfo::SubRegCoveredBits LoongArchSubRegIdxRanges[] = {
+ { 65535, 65535 },
+ { 0, 32 }, // sub_32
+};
+
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Woverlength-strings"
+#endif
+extern const char LoongArchRegStrings[] = {
+ /* 0 */ "F10\0"
+ /* 4 */ "R10\0"
+ /* 8 */ "F20\0"
+ /* 12 */ "R20\0"
+ /* 16 */ "F30\0"
+ /* 20 */ "R30\0"
+ /* 24 */ "FCC0\0"
+ /* 29 */ "F0\0"
+ /* 32 */ "FCSR0\0"
+ /* 38 */ "F11\0"
+ /* 42 */ "R11\0"
+ /* 46 */ "F21\0"
+ /* 50 */ "R21\0"
+ /* 54 */ "F31\0"
+ /* 58 */ "R31\0"
+ /* 62 */ "FCC1\0"
+ /* 67 */ "F1\0"
+ /* 70 */ "FCSR1\0"
+ /* 76 */ "F12\0"
+ /* 80 */ "R12\0"
+ /* 84 */ "F22\0"
+ /* 88 */ "R22\0"
+ /* 92 */ "FCC2\0"
+ /* 97 */ "F2\0"
+ /* 100 */ "FCSR2\0"
+ /* 106 */ "F13\0"
+ /* 110 */ "R13\0"
+ /* 114 */ "F23\0"
+ /* 118 */ "R23\0"
+ /* 122 */ "FCC3\0"
+ /* 127 */ "F3\0"
+ /* 130 */ "FCSR3\0"
+ /* 136 */ "F14\0"
+ /* 140 */ "R14\0"
+ /* 144 */ "F24\0"
+ /* 148 */ "R24\0"
+ /* 152 */ "F10_64\0"
+ /* 159 */ "F20_64\0"
+ /* 166 */ "F30_64\0"
+ /* 173 */ "F0_64\0"
+ /* 179 */ "F11_64\0"
+ /* 186 */ "F21_64\0"
+ /* 193 */ "F31_64\0"
+ /* 200 */ "F1_64\0"
+ /* 206 */ "F12_64\0"
+ /* 213 */ "F22_64\0"
+ /* 220 */ "F2_64\0"
+ /* 226 */ "F13_64\0"
+ /* 233 */ "F23_64\0"
+ /* 240 */ "F3_64\0"
+ /* 246 */ "F14_64\0"
+ /* 253 */ "F24_64\0"
+ /* 260 */ "F4_64\0"
+ /* 266 */ "F15_64\0"
+ /* 273 */ "F25_64\0"
+ /* 280 */ "F5_64\0"
+ /* 286 */ "F16_64\0"
+ /* 293 */ "F26_64\0"
+ /* 300 */ "F6_64\0"
+ /* 306 */ "F17_64\0"
+ /* 313 */ "F27_64\0"
+ /* 320 */ "F7_64\0"
+ /* 326 */ "F18_64\0"
+ /* 333 */ "F28_64\0"
+ /* 340 */ "F8_64\0"
+ /* 346 */ "F19_64\0"
+ /* 353 */ "F29_64\0"
+ /* 360 */ "F9_64\0"
+ /* 366 */ "FCC4\0"
+ /* 371 */ "F4\0"
+ /* 374 */ "R4\0"
+ /* 377 */ "F15\0"
+ /* 381 */ "R15\0"
+ /* 385 */ "F25\0"
+ /* 389 */ "R25\0"
+ /* 393 */ "FCC5\0"
+ /* 398 */ "F5\0"
+ /* 401 */ "R5\0"
+ /* 404 */ "F16\0"
+ /* 408 */ "R16\0"
+ /* 412 */ "F26\0"
+ /* 416 */ "R26\0"
+ /* 420 */ "FCC6\0"
+ /* 425 */ "F6\0"
+ /* 428 */ "R6\0"
+ /* 431 */ "F17\0"
+ /* 435 */ "R17\0"
+ /* 439 */ "F27\0"
+ /* 443 */ "R27\0"
+ /* 447 */ "FCC7\0"
+ /* 452 */ "F7\0"
+ /* 455 */ "R7\0"
+ /* 458 */ "F18\0"
+ /* 462 */ "R18\0"
+ /* 466 */ "F28\0"
+ /* 470 */ "R28\0"
+ /* 474 */ "F8\0"
+ /* 477 */ "R8\0"
+ /* 480 */ "F19\0"
+ /* 484 */ "R19\0"
+ /* 488 */ "F29\0"
+ /* 492 */ "R29\0"
+ /* 496 */ "F9\0"
+ /* 499 */ "R9\0"
+};
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+extern const MCRegisterDesc LoongArchRegDesc[] = { // Descriptors
+ { 3, 0, 0, 0, 0, 0 },
+ { 29, 1, 0, 1, 97, 0 },
+ { 67, 1, 0, 1, 97, 0 },
+ { 97, 1, 0, 1, 97, 0 },
+ { 127, 1, 0, 1, 97, 0 },
+ { 371, 1, 0, 1, 97, 0 },
+ { 398, 1, 0, 1, 97, 0 },
+ { 425, 1, 0, 1, 97, 0 },
+ { 452, 1, 0, 1, 97, 0 },
+ { 474, 1, 0, 1, 97, 0 },
+ { 496, 1, 0, 1, 97, 0 },
+ { 0, 1, 0, 1, 97, 0 },
+ { 38, 1, 0, 1, 97, 0 },
+ { 76, 1, 0, 1, 97, 0 },
+ { 106, 1, 0, 1, 97, 0 },
+ { 136, 1, 0, 1, 97, 0 },
+ { 377, 1, 0, 1, 97, 0 },
+ { 404, 1, 0, 1, 97, 0 },
+ { 431, 1, 0, 1, 97, 0 },
+ { 458, 1, 0, 1, 97, 0 },
+ { 480, 1, 0, 1, 97, 0 },
+ { 8, 1, 0, 1, 97, 0 },
+ { 46, 1, 0, 1, 97, 0 },
+ { 84, 1, 0, 1, 97, 0 },
+ { 114, 1, 0, 1, 97, 0 },
+ { 144, 1, 0, 1, 97, 0 },
+ { 385, 1, 0, 1, 97, 0 },
+ { 412, 1, 0, 1, 97, 0 },
+ { 439, 1, 0, 1, 97, 0 },
+ { 466, 1, 0, 1, 97, 0 },
+ { 488, 1, 0, 1, 97, 0 },
+ { 16, 1, 0, 1, 97, 0 },
+ { 54, 1, 0, 1, 97, 0 },
+ { 24, 1, 1, 1, 97, 0 },
+ { 62, 1, 1, 1, 97, 0 },
+ { 92, 1, 1, 1, 97, 0 },
+ { 122, 1, 1, 1, 97, 0 },
+ { 366, 1, 1, 1, 97, 0 },
+ { 393, 1, 1, 1, 97, 0 },
+ { 420, 1, 1, 1, 97, 0 },
+ { 447, 1, 1, 1, 97, 0 },
+ { 32, 1, 1, 1, 97, 0 },
+ { 70, 1, 1, 1, 97, 0 },
+ { 100, 1, 1, 1, 97, 0 },
+ { 130, 1, 1, 1, 97, 0 },
+ { 35, 1, 1, 1, 97, 0 },
+ { 73, 1, 1, 1, 97, 0 },
+ { 103, 1, 1, 1, 97, 0 },
+ { 133, 1, 1, 1, 97, 0 },
+ { 374, 1, 1, 1, 97, 0 },
+ { 401, 1, 1, 1, 97, 0 },
+ { 428, 1, 1, 1, 97, 0 },
+ { 455, 1, 1, 1, 97, 0 },
+ { 477, 1, 1, 1, 97, 0 },
+ { 499, 1, 1, 1, 97, 0 },
+ { 4, 1, 1, 1, 97, 0 },
+ { 42, 1, 1, 1, 97, 0 },
+ { 80, 1, 1, 1, 97, 0 },
+ { 110, 1, 1, 1, 97, 0 },
+ { 140, 1, 1, 1, 97, 0 },
+ { 381, 1, 1, 1, 97, 0 },
+ { 408, 1, 1, 1, 97, 0 },
+ { 435, 1, 1, 1, 97, 0 },
+ { 462, 1, 1, 1, 97, 0 },
+ { 484, 1, 1, 1, 97, 0 },
+ { 12, 1, 1, 1, 97, 0 },
+ { 50, 1, 1, 1, 97, 0 },
+ { 88, 1, 1, 1, 97, 0 },
+ { 118, 1, 1, 1, 97, 0 },
+ { 148, 1, 1, 1, 97, 0 },
+ { 389, 1, 1, 1, 97, 0 },
+ { 416, 1, 1, 1, 97, 0 },
+ { 443, 1, 1, 1, 97, 0 },
+ { 470, 1, 1, 1, 97, 0 },
+ { 492, 1, 1, 1, 97, 0 },
+ { 20, 1, 1, 1, 97, 0 },
+ { 58, 1, 1, 1, 97, 0 },
+ { 173, 4, 1, 0, 33, 2 },
+ { 200, 4, 1, 0, 33, 2 },
+ { 220, 4, 1, 0, 33, 2 },
+ { 240, 4, 1, 0, 33, 2 },
+ { 260, 4, 1, 0, 33, 2 },
+ { 280, 4, 1, 0, 33, 2 },
+ { 300, 4, 1, 0, 33, 2 },
+ { 320, 4, 1, 0, 33, 2 },
+ { 340, 4, 1, 0, 33, 2 },
+ { 360, 4, 1, 0, 33, 2 },
+ { 152, 4, 1, 0, 33, 2 },
+ { 179, 4, 1, 0, 33, 2 },
+ { 206, 4, 1, 0, 33, 2 },
+ { 226, 4, 1, 0, 33, 2 },
+ { 246, 4, 1, 0, 33, 2 },
+ { 266, 4, 1, 0, 33, 2 },
+ { 286, 4, 1, 0, 33, 2 },
+ { 306, 4, 1, 0, 33, 2 },
+ { 326, 4, 1, 0, 33, 2 },
+ { 346, 4, 1, 0, 33, 2 },
+ { 159, 4, 1, 0, 33, 2 },
+ { 186, 4, 1, 0, 33, 2 },
+ { 213, 4, 1, 0, 33, 2 },
+ { 233, 4, 1, 0, 33, 2 },
+ { 253, 4, 1, 0, 33, 2 },
+ { 273, 4, 1, 0, 33, 2 },
+ { 293, 4, 1, 0, 33, 2 },
+ { 313, 4, 1, 0, 33, 2 },
+ { 333, 4, 1, 0, 33, 2 },
+ { 353, 4, 1, 0, 33, 2 },
+ { 166, 4, 1, 0, 33, 2 },
+ { 193, 4, 1, 0, 33, 2 },
+};
+
+extern const MCPhysReg LoongArchRegUnitRoots[][2] = {
+ { LoongArch::F0 },
+ { LoongArch::F1 },
+ { LoongArch::F2 },
+ { LoongArch::F3 },
+ { LoongArch::F4 },
+ { LoongArch::F5 },
+ { LoongArch::F6 },
+ { LoongArch::F7 },
+ { LoongArch::F8 },
+ { LoongArch::F9 },
+ { LoongArch::F10 },
+ { LoongArch::F11 },
+ { LoongArch::F12 },
+ { LoongArch::F13 },
+ { LoongArch::F14 },
+ { LoongArch::F15 },
+ { LoongArch::F16 },
+ { LoongArch::F17 },
+ { LoongArch::F18 },
+ { LoongArch::F19 },
+ { LoongArch::F20 },
+ { LoongArch::F21 },
+ { LoongArch::F22 },
+ { LoongArch::F23 },
+ { LoongArch::F24 },
+ { LoongArch::F25 },
+ { LoongArch::F26 },
+ { LoongArch::F27 },
+ { LoongArch::F28 },
+ { LoongArch::F29 },
+ { LoongArch::F30 },
+ { LoongArch::F31 },
+ { LoongArch::FCC0 },
+ { LoongArch::FCC1 },
+ { LoongArch::FCC2 },
+ { LoongArch::FCC3 },
+ { LoongArch::FCC4 },
+ { LoongArch::FCC5 },
+ { LoongArch::FCC6 },
+ { LoongArch::FCC7 },
+ { LoongArch::FCSR0 },
+ { LoongArch::FCSR1 },
+ { LoongArch::FCSR2 },
+ { LoongArch::FCSR3 },
+ { LoongArch::R0 },
+ { LoongArch::R1 },
+ { LoongArch::R2 },
+ { LoongArch::R3 },
+ { LoongArch::R4 },
+ { LoongArch::R5 },
+ { LoongArch::R6 },
+ { LoongArch::R7 },
+ { LoongArch::R8 },
+ { LoongArch::R9 },
+ { LoongArch::R10 },
+ { LoongArch::R11 },
+ { LoongArch::R12 },
+ { LoongArch::R13 },
+ { LoongArch::R14 },
+ { LoongArch::R15 },
+ { LoongArch::R16 },
+ { LoongArch::R17 },
+ { LoongArch::R18 },
+ { LoongArch::R19 },
+ { LoongArch::R20 },
+ { LoongArch::R21 },
+ { LoongArch::R22 },
+ { LoongArch::R23 },
+ { LoongArch::R24 },
+ { LoongArch::R25 },
+ { LoongArch::R26 },
+ { LoongArch::R27 },
+ { LoongArch::R28 },
+ { LoongArch::R29 },
+ { LoongArch::R30 },
+ { LoongArch::R31 },
+};
+
+namespace { // Register classes...
+ // FPR32 Register Class...
+ const MCPhysReg FPR32[] = {
+ LoongArch::F0, LoongArch::F1, LoongArch::F2, LoongArch::F3, LoongArch::F4, LoongArch::F5, LoongArch::F6, LoongArch::F7, LoongArch::F8, LoongArch::F9, LoongArch::F10, LoongArch::F11, LoongArch::F12, LoongArch::F13, LoongArch::F14, LoongArch::F15, LoongArch::F16, LoongArch::F17, LoongArch::F18, LoongArch::F19, LoongArch::F20, LoongArch::F21, LoongArch::F22, LoongArch::F23, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31,
+ };
+
+ // FPR32 Bit set.
+ const uint8_t FPR32Bits[] = {
+ 0xfe, 0xff, 0xff, 0xff, 0x01,
+ };
+
+ // GPR Register Class...
+ const MCPhysReg GPR[] = {
+ LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R0, LoongArch::R1, LoongArch::R2, LoongArch::R3, LoongArch::R21,
+ };
+
+ // GPR Bit set.
+ const uint8_t GPRBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
+ };
+
+ // GPRT Register Class...
+ const MCPhysReg GPRT[] = {
+ LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20,
+ };
+
+ // GPRT Bit set.
+ const uint8_t GPRTBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x03,
+ };
+
+ // CFR Register Class...
+ const MCPhysReg CFR[] = {
+ LoongArch::FCC0, LoongArch::FCC1, LoongArch::FCC2, LoongArch::FCC3, LoongArch::FCC4, LoongArch::FCC5, LoongArch::FCC6, LoongArch::FCC7,
+ };
+
+ // CFR Bit set.
+ const uint8_t CFRBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
+ };
+
+ // FCSR Register Class...
+ const MCPhysReg FCSR[] = {
+ LoongArch::FCSR0, LoongArch::FCSR1, LoongArch::FCSR2, LoongArch::FCSR3,
+ };
+
+ // FCSR Bit set.
+ const uint8_t FCSRBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
+ };
+
+ // FPR64 Register Class...
+ const MCPhysReg FPR64[] = {
+ LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64, LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64, LoongArch::F8_64, LoongArch::F9_64, LoongArch::F10_64, LoongArch::F11_64, LoongArch::F12_64, LoongArch::F13_64, LoongArch::F14_64, LoongArch::F15_64, LoongArch::F16_64, LoongArch::F17_64, LoongArch::F18_64, LoongArch::F19_64, LoongArch::F20_64, LoongArch::F21_64, LoongArch::F22_64, LoongArch::F23_64, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64,
+ };
+
+ // FPR64 Bit set.
+ const uint8_t FPR64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
+ };
+
+} // end anonymous namespace
+
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Woverlength-strings"
+#endif
+extern const char LoongArchRegClassStrings[] = {
+ /* 0 */ "FPR32\0"
+ /* 6 */ "FPR64\0"
+ /* 12 */ "CFR\0"
+ /* 16 */ "GPR\0"
+ /* 20 */ "FCSR\0"
+ /* 25 */ "GPRT\0"
+};
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+extern const MCRegisterClass LoongArchMCRegisterClasses[] = {
+ { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), LoongArch::FPR32RegClassID, 32, 1, true },
+ { GPR, GPRBits, 16, 32, sizeof(GPRBits), LoongArch::GPRRegClassID, 0, 1, true },
+ { GPRT, GPRTBits, 25, 17, sizeof(GPRTBits), LoongArch::GPRTRegClassID, 0, 1, true },
+ { CFR, CFRBits, 12, 8, sizeof(CFRBits), LoongArch::CFRRegClassID, 0, 1, true },
+ { FCSR, FCSRBits, 20, 4, sizeof(FCSRBits), LoongArch::FCSRRegClassID, 32, 1, false },
+ { FPR64, FPR64Bits, 6, 32, sizeof(FPR64Bits), LoongArch::FPR64RegClassID, 64, 1, true },
+};
+
+// LoongArch Dwarf<->LLVM register mappings.
+extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[] = {
+ { 0U, LoongArch::R0 },
+ { 1U, LoongArch::R1 },
+ { 2U, LoongArch::R2 },
+ { 3U, LoongArch::R3 },
+ { 4U, LoongArch::R4 },
+ { 5U, LoongArch::R5 },
+ { 6U, LoongArch::R6 },
+ { 7U, LoongArch::R7 },
+ { 8U, LoongArch::R8 },
+ { 9U, LoongArch::R9 },
+ { 10U, LoongArch::R10 },
+ { 11U, LoongArch::R11 },
+ { 12U, LoongArch::R12 },
+ { 13U, LoongArch::R13 },
+ { 14U, LoongArch::R14 },
+ { 15U, LoongArch::R15 },
+ { 16U, LoongArch::R16 },
+ { 17U, LoongArch::R17 },
+ { 18U, LoongArch::R18 },
+ { 19U, LoongArch::R19 },
+ { 20U, LoongArch::R20 },
+ { 21U, LoongArch::R21 },
+ { 22U, LoongArch::R22 },
+ { 23U, LoongArch::R23 },
+ { 24U, LoongArch::R24 },
+ { 25U, LoongArch::R25 },
+ { 26U, LoongArch::R26 },
+ { 27U, LoongArch::R27 },
+ { 28U, LoongArch::R28 },
+ { 29U, LoongArch::R29 },
+ { 30U, LoongArch::R30 },
+ { 31U, LoongArch::R31 },
+ { 32U, LoongArch::F0_64 },
+ { 33U, LoongArch::F1_64 },
+ { 34U, LoongArch::F2_64 },
+ { 35U, LoongArch::F3_64 },
+ { 36U, LoongArch::F4_64 },
+ { 37U, LoongArch::F5_64 },
+ { 38U, LoongArch::F6_64 },
+ { 39U, LoongArch::F7_64 },
+ { 40U, LoongArch::F8_64 },
+ { 41U, LoongArch::F9_64 },
+ { 42U, LoongArch::F10_64 },
+ { 43U, LoongArch::F11_64 },
+ { 44U, LoongArch::F12_64 },
+ { 45U, LoongArch::F13_64 },
+ { 46U, LoongArch::F14_64 },
+ { 47U, LoongArch::F15_64 },
+ { 48U, LoongArch::F16_64 },
+ { 49U, LoongArch::F17_64 },
+ { 50U, LoongArch::F18_64 },
+ { 51U, LoongArch::F19_64 },
+ { 52U, LoongArch::F20_64 },
+ { 53U, LoongArch::F21_64 },
+ { 54U, LoongArch::F22_64 },
+ { 55U, LoongArch::F23_64 },
+ { 56U, LoongArch::F24_64 },
+ { 57U, LoongArch::F25_64 },
+ { 58U, LoongArch::F26_64 },
+ { 59U, LoongArch::F27_64 },
+ { 60U, LoongArch::F28_64 },
+ { 61U, LoongArch::F29_64 },
+ { 62U, LoongArch::F30_64 },
+ { 63U, LoongArch::F31_64 },
+};
+extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize = std::size(LoongArchDwarfFlavour0Dwarf2L);
+
+extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[] = {
+ { 0U, LoongArch::R0 },
+ { 1U, LoongArch::R1 },
+ { 2U, LoongArch::R2 },
+ { 3U, LoongArch::R3 },
+ { 4U, LoongArch::R4 },
+ { 5U, LoongArch::R5 },
+ { 6U, LoongArch::R6 },
+ { 7U, LoongArch::R7 },
+ { 8U, LoongArch::R8 },
+ { 9U, LoongArch::R9 },
+ { 10U, LoongArch::R10 },
+ { 11U, LoongArch::R11 },
+ { 12U, LoongArch::R12 },
+ { 13U, LoongArch::R13 },
+ { 14U, LoongArch::R14 },
+ { 15U, LoongArch::R15 },
+ { 16U, LoongArch::R16 },
+ { 17U, LoongArch::R17 },
+ { 18U, LoongArch::R18 },
+ { 19U, LoongArch::R19 },
+ { 20U, LoongArch::R20 },
+ { 21U, LoongArch::R21 },
+ { 22U, LoongArch::R22 },
+ { 23U, LoongArch::R23 },
+ { 24U, LoongArch::R24 },
+ { 25U, LoongArch::R25 },
+ { 26U, LoongArch::R26 },
+ { 27U, LoongArch::R27 },
+ { 28U, LoongArch::R28 },
+ { 29U, LoongArch::R29 },
+ { 30U, LoongArch::R30 },
+ { 31U, LoongArch::R31 },
+ { 32U, LoongArch::F0_64 },
+ { 33U, LoongArch::F1_64 },
+ { 34U, LoongArch::F2_64 },
+ { 35U, LoongArch::F3_64 },
+ { 36U, LoongArch::F4_64 },
+ { 37U, LoongArch::F5_64 },
+ { 38U, LoongArch::F6_64 },
+ { 39U, LoongArch::F7_64 },
+ { 40U, LoongArch::F8_64 },
+ { 41U, LoongArch::F9_64 },
+ { 42U, LoongArch::F10_64 },
+ { 43U, LoongArch::F11_64 },
+ { 44U, LoongArch::F12_64 },
+ { 45U, LoongArch::F13_64 },
+ { 46U, LoongArch::F14_64 },
+ { 47U, LoongArch::F15_64 },
+ { 48U, LoongArch::F16_64 },
+ { 49U, LoongArch::F17_64 },
+ { 50U, LoongArch::F18_64 },
+ { 51U, LoongArch::F19_64 },
+ { 52U, LoongArch::F20_64 },
+ { 53U, LoongArch::F21_64 },
+ { 54U, LoongArch::F22_64 },
+ { 55U, LoongArch::F23_64 },
+ { 56U, LoongArch::F24_64 },
+ { 57U, LoongArch::F25_64 },
+ { 58U, LoongArch::F26_64 },
+ { 59U, LoongArch::F27_64 },
+ { 60U, LoongArch::F28_64 },
+ { 61U, LoongArch::F29_64 },
+ { 62U, LoongArch::F30_64 },
+ { 63U, LoongArch::F31_64 },
+};
+extern const unsigned LoongArchEHFlavour0Dwarf2LSize = std::size(LoongArchEHFlavour0Dwarf2L);
+
+extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[] = {
+ { LoongArch::F0, 32U },
+ { LoongArch::F1, 33U },
+ { LoongArch::F2, 34U },
+ { LoongArch::F3, 35U },
+ { LoongArch::F4, 36U },
+ { LoongArch::F5, 37U },
+ { LoongArch::F6, 38U },
+ { LoongArch::F7, 39U },
+ { LoongArch::F8, 40U },
+ { LoongArch::F9, 41U },
+ { LoongArch::F10, 42U },
+ { LoongArch::F11, 43U },
+ { LoongArch::F12, 44U },
+ { LoongArch::F13, 45U },
+ { LoongArch::F14, 46U },
+ { LoongArch::F15, 47U },
+ { LoongArch::F16, 48U },
+ { LoongArch::F17, 49U },
+ { LoongArch::F18, 50U },
+ { LoongArch::F19, 51U },
+ { LoongArch::F20, 52U },
+ { LoongArch::F21, 53U },
+ { LoongArch::F22, 54U },
+ { LoongArch::F23, 55U },
+ { LoongArch::F24, 56U },
+ { LoongArch::F25, 57U },
+ { LoongArch::F26, 58U },
+ { LoongArch::F27, 59U },
+ { LoongArch::F28, 60U },
+ { LoongArch::F29, 61U },
+ { LoongArch::F30, 62U },
+ { LoongArch::F31, 63U },
+ { LoongArch::R0, 0U },
+ { LoongArch::R1, 1U },
+ { LoongArch::R2, 2U },
+ { LoongArch::R3, 3U },
+ { LoongArch::R4, 4U },
+ { LoongArch::R5, 5U },
+ { LoongArch::R6, 6U },
+ { LoongArch::R7, 7U },
+ { LoongArch::R8, 8U },
+ { LoongArch::R9, 9U },
+ { LoongArch::R10, 10U },
+ { LoongArch::R11, 11U },
+ { LoongArch::R12, 12U },
+ { LoongArch::R13, 13U },
+ { LoongArch::R14, 14U },
+ { LoongArch::R15, 15U },
+ { LoongArch::R16, 16U },
+ { LoongArch::R17, 17U },
+ { LoongArch::R18, 18U },
+ { LoongArch::R19, 19U },
+ { LoongArch::R20, 20U },
+ { LoongArch::R21, 21U },
+ { LoongArch::R22, 22U },
+ { LoongArch::R23, 23U },
+ { LoongArch::R24, 24U },
+ { LoongArch::R25, 25U },
+ { LoongArch::R26, 26U },
+ { LoongArch::R27, 27U },
+ { LoongArch::R28, 28U },
+ { LoongArch::R29, 29U },
+ { LoongArch::R30, 30U },
+ { LoongArch::R31, 31U },
+ { LoongArch::F0_64, 32U },
+ { LoongArch::F1_64, 33U },
+ { LoongArch::F2_64, 34U },
+ { LoongArch::F3_64, 35U },
+ { LoongArch::F4_64, 36U },
+ { LoongArch::F5_64, 37U },
+ { LoongArch::F6_64, 38U },
+ { LoongArch::F7_64, 39U },
+ { LoongArch::F8_64, 40U },
+ { LoongArch::F9_64, 41U },
+ { LoongArch::F10_64, 42U },
+ { LoongArch::F11_64, 43U },
+ { LoongArch::F12_64, 44U },
+ { LoongArch::F13_64, 45U },
+ { LoongArch::F14_64, 46U },
+ { LoongArch::F15_64, 47U },
+ { LoongArch::F16_64, 48U },
+ { LoongArch::F17_64, 49U },
+ { LoongArch::F18_64, 50U },
+ { LoongArch::F19_64, 51U },
+ { LoongArch::F20_64, 52U },
+ { LoongArch::F21_64, 53U },
+ { LoongArch::F22_64, 54U },
+ { LoongArch::F23_64, 55U },
+ { LoongArch::F24_64, 56U },
+ { LoongArch::F25_64, 57U },
+ { LoongArch::F26_64, 58U },
+ { LoongArch::F27_64, 59U },
+ { LoongArch::F28_64, 60U },
+ { LoongArch::F29_64, 61U },
+ { LoongArch::F30_64, 62U },
+ { LoongArch::F31_64, 63U },
+};
+extern const unsigned LoongArchDwarfFlavour0L2DwarfSize = std::size(LoongArchDwarfFlavour0L2Dwarf);
+
+extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[] = {
+ { LoongArch::F0, 32U },
+ { LoongArch::F1, 33U },
+ { LoongArch::F2, 34U },
+ { LoongArch::F3, 35U },
+ { LoongArch::F4, 36U },
+ { LoongArch::F5, 37U },
+ { LoongArch::F6, 38U },
+ { LoongArch::F7, 39U },
+ { LoongArch::F8, 40U },
+ { LoongArch::F9, 41U },
+ { LoongArch::F10, 42U },
+ { LoongArch::F11, 43U },
+ { LoongArch::F12, 44U },
+ { LoongArch::F13, 45U },
+ { LoongArch::F14, 46U },
+ { LoongArch::F15, 47U },
+ { LoongArch::F16, 48U },
+ { LoongArch::F17, 49U },
+ { LoongArch::F18, 50U },
+ { LoongArch::F19, 51U },
+ { LoongArch::F20, 52U },
+ { LoongArch::F21, 53U },
+ { LoongArch::F22, 54U },
+ { LoongArch::F23, 55U },
+ { LoongArch::F24, 56U },
+ { LoongArch::F25, 57U },
+ { LoongArch::F26, 58U },
+ { LoongArch::F27, 59U },
+ { LoongArch::F28, 60U },
+ { LoongArch::F29, 61U },
+ { LoongArch::F30, 62U },
+ { LoongArch::F31, 63U },
+ { LoongArch::R0, 0U },
+ { LoongArch::R1, 1U },
+ { LoongArch::R2, 2U },
+ { LoongArch::R3, 3U },
+ { LoongArch::R4, 4U },
+ { LoongArch::R5, 5U },
+ { LoongArch::R6, 6U },
+ { LoongArch::R7, 7U },
+ { LoongArch::R8, 8U },
+ { LoongArch::R9, 9U },
+ { LoongArch::R10, 10U },
+ { LoongArch::R11, 11U },
+ { LoongArch::R12, 12U },
+ { LoongArch::R13, 13U },
+ { LoongArch::R14, 14U },
+ { LoongArch::R15, 15U },
+ { LoongArch::R16, 16U },
+ { LoongArch::R17, 17U },
+ { LoongArch::R18, 18U },
+ { LoongArch::R19, 19U },
+ { LoongArch::R20, 20U },
+ { LoongArch::R21, 21U },
+ { LoongArch::R22, 22U },
+ { LoongArch::R23, 23U },
+ { LoongArch::R24, 24U },
+ { LoongArch::R25, 25U },
+ { LoongArch::R26, 26U },
+ { LoongArch::R27, 27U },
+ { LoongArch::R28, 28U },
+ { LoongArch::R29, 29U },
+ { LoongArch::R30, 30U },
+ { LoongArch::R31, 31U },
+ { LoongArch::F0_64, 32U },
+ { LoongArch::F1_64, 33U },
+ { LoongArch::F2_64, 34U },
+ { LoongArch::F3_64, 35U },
+ { LoongArch::F4_64, 36U },
+ { LoongArch::F5_64, 37U },
+ { LoongArch::F6_64, 38U },
+ { LoongArch::F7_64, 39U },
+ { LoongArch::F8_64, 40U },
+ { LoongArch::F9_64, 41U },
+ { LoongArch::F10_64, 42U },
+ { LoongArch::F11_64, 43U },
+ { LoongArch::F12_64, 44U },
+ { LoongArch::F13_64, 45U },
+ { LoongArch::F14_64, 46U },
+ { LoongArch::F15_64, 47U },
+ { LoongArch::F16_64, 48U },
+ { LoongArch::F17_64, 49U },
+ { LoongArch::F18_64, 50U },
+ { LoongArch::F19_64, 51U },
+ { LoongArch::F20_64, 52U },
+ { LoongArch::F21_64, 53U },
+ { LoongArch::F22_64, 54U },
+ { LoongArch::F23_64, 55U },
+ { LoongArch::F24_64, 56U },
+ { LoongArch::F25_64, 57U },
+ { LoongArch::F26_64, 58U },
+ { LoongArch::F27_64, 59U },
+ { LoongArch::F28_64, 60U },
+ { LoongArch::F29_64, 61U },
+ { LoongArch::F30_64, 62U },
+ { LoongArch::F31_64, 63U },
+};
+extern const unsigned LoongArchEHFlavour0L2DwarfSize = std::size(LoongArchEHFlavour0L2Dwarf);
+
+extern const uint16_t LoongArchRegEncodingTable[] = {
+ 0,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 0,
+ 1,
+ 2,
+ 3,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+};
+static inline void InitLoongArchMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
+ RI->InitMCRegisterInfo(LoongArchRegDesc, 109, RA, PC, LoongArchMCRegisterClasses, 6, LoongArchRegUnitRoots, 76, LoongArchRegDiffLists, LoongArchLaneMaskLists, LoongArchRegStrings, LoongArchRegClassStrings, LoongArchSubRegIdxLists, 2,
+LoongArchSubRegIdxRanges, LoongArchRegEncodingTable);
+
+ switch (DwarfFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ RI->mapDwarfRegsToLLVMRegs(LoongArchDwarfFlavour0Dwarf2L, LoongArchDwarfFlavour0Dwarf2LSize, false);
+ break;
+ }
+ switch (EHFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ RI->mapDwarfRegsToLLVMRegs(LoongArchEHFlavour0Dwarf2L, LoongArchEHFlavour0Dwarf2LSize, true);
+ break;
+ }
+ switch (DwarfFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ RI->mapLLVMRegsToDwarfRegs(LoongArchDwarfFlavour0L2Dwarf, LoongArchDwarfFlavour0L2DwarfSize, false);
+ break;
+ }
+ switch (EHFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ RI->mapLLVMRegsToDwarfRegs(LoongArchEHFlavour0L2Dwarf, LoongArchEHFlavour0L2DwarfSize, true);
+ break;
+ }
+}
+
+} // end namespace llvm
+
+#endif // GET_REGINFO_MC_DESC
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Register Information Header Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_HEADER
+#undef GET_REGINFO_HEADER
+
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+
+namespace llvm {
+
+class LoongArchFrameLowering;
+
+struct LoongArchGenRegisterInfo : public TargetRegisterInfo {
+ explicit LoongArchGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
+ unsigned PC = 0, unsigned HwMode = 0);
+ unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
+ LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
+ LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
+ const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
+ const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
+ const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
+ unsigned getRegUnitWeight(unsigned RegUnit) const override;
+ unsigned getNumRegPressureSets() const override;
+ const char *getRegPressureSetName(unsigned Idx) const override;
+ unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
+ const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
+ const int *getRegUnitPressureSets(unsigned RegUnit) const override;
+ ArrayRef<const char *> getRegMaskNames() const override;
+ ArrayRef<const uint32_t *> getRegMasks() const override;
+ bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
+ bool isFixedRegister(const MachineFunction &, MCRegister) const override;
+ bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
+ bool isConstantPhysReg(MCRegister PhysReg) const override final;
+ /// Devirtualized TargetFrameLowering.
+ static const LoongArchFrameLowering *getFrameLowering(
+ const MachineFunction &MF);
+};
+
+namespace LoongArch { // Register classes
+ extern const TargetRegisterClass FPR32RegClass;
+ extern const TargetRegisterClass GPRRegClass;
+ extern const TargetRegisterClass GPRTRegClass;
+ extern const TargetRegisterClass CFRRegClass;
+ extern const TargetRegisterClass FCSRRegClass;
+ extern const TargetRegisterClass FPR64RegClass;
+} // end namespace LoongArch
+
+} // end namespace llvm
+
+#endif // GET_REGINFO_HEADER
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Target Register and Register Classes Information *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_TARGET_DESC
+#undef GET_REGINFO_TARGET_DESC
+
+namespace llvm {
+
+extern const MCRegisterClass LoongArchMCRegisterClasses[];
+
+static const MVT::SimpleValueType VTLists[] = {
+ /* 0 */ MVT::i32, MVT::Other,
+ /* 2 */ MVT::i64, MVT::Other,
+ /* 4 */ MVT::f32, MVT::Other,
+ /* 6 */ MVT::f64, MVT::Other,
+};
+
+static const char *SubRegIndexNameTable[] = { "sub_32", "" };
+
+
+static const LaneBitmask SubRegIndexLaneMaskTable[] = {
+ LaneBitmask::getAll(),
+ LaneBitmask(0x0000000000000001), // sub_32
+ };
+
+
+
+static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
+ // Mode = 0 (Default)
+ { 32, 32, 32, VTLists+4 }, // FPR32
+ { 32, 32, 32, VTLists+0 }, // GPR
+ { 32, 32, 32, VTLists+0 }, // GPRT
+ { 32, 32, 32, VTLists+0 }, // CFR
+ { 32, 32, 32, VTLists+0 }, // FCSR
+ { 64, 64, 64, VTLists+6 }, // FPR64
+ // Mode = 1 (LA64)
+ { 32, 32, 32, VTLists+4 }, // FPR32
+ { 64, 64, 64, VTLists+2 }, // GPR
+ { 64, 64, 64, VTLists+2 }, // GPRT
+ { 64, 64, 64, VTLists+2 }, // CFR
+ { 32, 32, 32, VTLists+0 }, // FCSR
+ { 64, 64, 64, VTLists+6 }, // FPR64
+};
+
+static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
+
+static const uint32_t FPR32SubClassMask[] = {
+ 0x00000001,
+ 0x00000020, // sub_32
+};
+
+static const uint32_t GPRSubClassMask[] = {
+ 0x00000006,
+};
+
+static const uint32_t GPRTSubClassMask[] = {
+ 0x00000004,
+};
+
+static const uint32_t CFRSubClassMask[] = {
+ 0x00000008,
+};
+
+static const uint32_t FCSRSubClassMask[] = {
+ 0x00000010,
+};
+
+static const uint32_t FPR64SubClassMask[] = {
+ 0x00000020,
+};
+
+static const uint16_t SuperRegIdxSeqs[] = {
+ /* 0 */ 1, 0,
+};
+
+static const TargetRegisterClass *const GPRTSuperclasses[] = {
+ &LoongArch::GPRRegClass,
+ nullptr
+};
+
+
+namespace LoongArch { // Register class instances
+ extern const TargetRegisterClass FPR32RegClass = {
+ &LoongArchMCRegisterClasses[FPR32RegClassID],
+ FPR32SubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x0000000000000001),
+ 0,
+ false,
+ 0x00, /* TSFlags */
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRRegClass = {
+ &LoongArchMCRegisterClasses[GPRRegClassID],
+ GPRSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x0000000000000001),
+ 0,
+ false,
+ 0x00, /* TSFlags */
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRTRegClass = {
+ &LoongArchMCRegisterClasses[GPRTRegClassID],
+ GPRTSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x0000000000000001),
+ 0,
+ false,
+ 0x00, /* TSFlags */
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPRTSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass CFRRegClass = {
+ &LoongArchMCRegisterClasses[CFRRegClassID],
+ CFRSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x0000000000000001),
+ 0,
+ false,
+ 0x00, /* TSFlags */
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass FCSRRegClass = {
+ &LoongArchMCRegisterClasses[FCSRRegClassID],
+ FCSRSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x0000000000000001),
+ 0,
+ false,
+ 0x00, /* TSFlags */
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass FPR64RegClass = {
+ &LoongArchMCRegisterClasses[FPR64RegClassID],
+ FPR64SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x0000000000000001),
+ 0,
+ false,
+ 0x00, /* TSFlags */
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+} // end namespace LoongArch
+
+namespace {
+ const TargetRegisterClass *const RegisterClasses[] = {
+ &LoongArch::FPR32RegClass,
+ &LoongArch::GPRRegClass,
+ &LoongArch::GPRTRegClass,
+ &LoongArch::CFRRegClass,
+ &LoongArch::FCSRRegClass,
+ &LoongArch::FPR64RegClass,
+ };
+} // end anonymous namespace
+
+static const uint8_t CostPerUseTable[] = {
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+
+
+static const bool InAllocatableClassTable[] = {
+false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
+
+
+static const TargetRegisterInfoDesc LoongArchRegInfoDesc = { // Extra Descriptors
+CostPerUseTable, 1, InAllocatableClassTable};
+
+unsigned LoongArchGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
+ static const uint8_t Rows[1][1] = {
+ { 0, },
+ };
+
+ --IdxA; assert(IdxA < 1); (void) IdxA;
+ --IdxB; assert(IdxB < 1);
+ return Rows[0][IdxB];
+}
+
+ struct MaskRolOp {
+ LaneBitmask Mask;
+ uint8_t RotateLeft;
+ };
+ static const MaskRolOp LaneMaskComposeSequences[] = {
+ { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 } // Sequence 0
+ };
+ static const uint8_t CompositeSequences[] = {
+ 0 // to sub_32
+ };
+
+LaneBitmask LoongArchGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
+ --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
+ LaneBitmask Result;
+ for (const MaskRolOp *Ops =
+ &LaneMaskComposeSequences[CompositeSequences[IdxA]];
+ Ops->Mask.any(); ++Ops) {
+ LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
+ if (unsigned S = Ops->RotateLeft)
+ Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
+ else
+ Result |= LaneBitmask(M);
+ }
+ return Result;
+}
+
+LaneBitmask LoongArchGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
+ LaneMask &= getSubRegIndexLaneMask(IdxA);
+ --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
+ LaneBitmask Result;
+ for (const MaskRolOp *Ops =
+ &LaneMaskComposeSequences[CompositeSequences[IdxA]];
+ Ops->Mask.any(); ++Ops) {
+ LaneBitmask::Type M = LaneMask.getAsInteger();
+ if (unsigned S = Ops->RotateLeft)
+ Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
+ else
+ Result |= LaneBitmask(M);
+ }
+ return Result;
+}
+
+const TargetRegisterClass *LoongArchGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
+ static const uint8_t Table[6][1] = {
+ { // FPR32
+ 0, // sub_32
+ },
+ { // GPR
+ 0, // sub_32
+ },
+ { // GPRT
+ 0, // sub_32
+ },
+ { // CFR
+ 0, // sub_32
+ },
+ { // FCSR
+ 0, // sub_32
+ },
+ { // FPR64
+ 6, // sub_32 -> FPR64
+ },
+ };
+ assert(RC && "Missing regclass");
+ if (!Idx) return RC;
+ --Idx;
+ assert(Idx < 1 && "Bad subreg");
+ unsigned TV = Table[RC->getID()][Idx];
+ return TV ? getRegClass(TV - 1) : nullptr;
+}
+
+const TargetRegisterClass *LoongArchGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
+ static const uint8_t Table[6][1] = {
+ { // FPR32
+ 0, // FPR32:sub_32
+ },
+ { // GPR
+ 0, // GPR:sub_32
+ },
+ { // GPRT
+ 0, // GPRT:sub_32
+ },
+ { // CFR
+ 0, // CFR:sub_32
+ },
+ { // FCSR
+ 0, // FCSR:sub_32
+ },
+ { // FPR64
+ 1, // FPR64:sub_32 -> FPR32
+ },
+ };
+ assert(RC && "Missing regclass");
+ if (!Idx) return RC;
+ --Idx;
+ assert(Idx < 1 && "Bad subreg");
+ unsigned TV = Table[RC->getID()][Idx];
+ return TV ? getRegClass(TV - 1) : nullptr;
+}
+
+/// Get the weight in units of pressure for this register class.
+const RegClassWeight &LoongArchGenRegisterInfo::
+getRegClassWeight(const TargetRegisterClass *RC) const {
+ static const RegClassWeight RCWeightTable[] = {
+ {1, 32}, // FPR32
+ {1, 32}, // GPR
+ {1, 17}, // GPRT
+ {1, 8}, // CFR
+ {0, 0}, // FCSR
+ {1, 32}, // FPR64
+ };
+ return RCWeightTable[RC->getID()];
+}
+
+/// Get the weight in units of pressure for this register unit.
+unsigned LoongArchGenRegisterInfo::
+getRegUnitWeight(unsigned RegUnit) const {
+ assert(RegUnit < 76 && "invalid register unit");
+ // All register units have unit weight.
+ return 1;
+}
+
+
+// Get the number of dimensions of register pressure.
+unsigned LoongArchGenRegisterInfo::getNumRegPressureSets() const {
+ return 4;
+}
+
+// Get the name of this register unit pressure set.
+const char *LoongArchGenRegisterInfo::
+getRegPressureSetName(unsigned Idx) const {
+ static const char *PressureNameTable[] = {
+ "CFR",
+ "GPRT",
+ "FPR32",
+ "GPR",
+ };
+ return PressureNameTable[Idx];
+}
+
+// Get the register unit pressure limit for this dimension.
+// This limit must be adjusted dynamically for reserved registers.
+unsigned LoongArchGenRegisterInfo::
+getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
+ static const uint8_t PressureLimitTable[] = {
+ 8, // 0: CFR
+ 17, // 1: GPRT
+ 32, // 2: FPR32
+ 32, // 3: GPR
+ };
+ return PressureLimitTable[Idx];
+}
+
+/// Table of pressure sets per register class or unit.
+static const int RCSetsTable[] = {
+ /* 0 */ 0, -1,
+ /* 2 */ 2, -1,
+ /* 4 */ 1, 3, -1,
+};
+
+/// Get the dimensions of register pressure impacted by this register class.
+/// Returns a -1 terminated array of pressure set IDs
+const int *LoongArchGenRegisterInfo::
+getRegClassPressureSets(const TargetRegisterClass *RC) const {
+ static const uint8_t RCSetStartTable[] = {
+ 2,5,4,0,1,2,};
+ return &RCSetsTable[RCSetStartTable[RC->getID()]];
+}
+
+/// Get the dimensions of register pressure impacted by this register unit.
+/// Returns a -1 terminated array of pressure set IDs
+const int *LoongArchGenRegisterInfo::
+getRegUnitPressureSets(unsigned RegUnit) const {
+ assert(RegUnit < 76 && "invalid register unit");
+ static const uint8_t RUSetStartTable[] = {
+ 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,1,1,1,1,5,5,5,5,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,};
+ return &RCSetsTable[RUSetStartTable[RegUnit]];
+}
+
+extern const MCRegisterDesc LoongArchRegDesc[];
+extern const MCPhysReg LoongArchRegDiffLists[];
+extern const LaneBitmask LoongArchLaneMaskLists[];
+extern const char LoongArchRegStrings[];
+extern const char LoongArchRegClassStrings[];
+extern const MCPhysReg LoongArchRegUnitRoots[][2];
+extern const uint16_t LoongArchSubRegIdxLists[];
+extern const MCRegisterInfo::SubRegCoveredBits LoongArchSubRegIdxRanges[];
+extern const uint16_t LoongArchRegEncodingTable[];
+// LoongArch Dwarf<->LLVM register mappings.
+extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[];
+extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize;
+
+extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[];
+extern const unsigned LoongArchEHFlavour0Dwarf2LSize;
+
+extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[];
+extern const unsigned LoongArchDwarfFlavour0L2DwarfSize;
+
+extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[];
+extern const unsigned LoongArchEHFlavour0L2DwarfSize;
+
+LoongArchGenRegisterInfo::
+LoongArchGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
+ unsigned PC, unsigned HwMode)
+ : TargetRegisterInfo(&LoongArchRegInfoDesc, RegisterClasses, RegisterClasses+6,
+ SubRegIndexNameTable, SubRegIndexLaneMaskTable,
+ LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, HwMode) {
+ InitMCRegisterInfo(LoongArchRegDesc, 109, RA, PC,
+ LoongArchMCRegisterClasses, 6,
+ LoongArchRegUnitRoots,
+ 76,
+ LoongArchRegDiffLists,
+ LoongArchLaneMaskLists,
+ LoongArchRegStrings,
+ LoongArchRegClassStrings,
+ LoongArchSubRegIdxLists,
+ 2,
+ LoongArchSubRegIdxRanges,
+ LoongArchRegEncodingTable);
+
+ switch (DwarfFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ mapDwarfRegsToLLVMRegs(LoongArchDwarfFlavour0Dwarf2L, LoongArchDwarfFlavour0Dwarf2LSize, false);
+ break;
+ }
+ switch (EHFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ mapDwarfRegsToLLVMRegs(LoongArchEHFlavour0Dwarf2L, LoongArchEHFlavour0Dwarf2LSize, true);
+ break;
+ }
+ switch (DwarfFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ mapLLVMRegsToDwarfRegs(LoongArchDwarfFlavour0L2Dwarf, LoongArchDwarfFlavour0L2DwarfSize, false);
+ break;
+ }
+ switch (EHFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ mapLLVMRegsToDwarfRegs(LoongArchEHFlavour0L2Dwarf, LoongArchEHFlavour0L2DwarfSize, true);
+ break;
+ }
+}
+
+static const MCPhysReg CSR_ILP32D_LP64D_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64, 0 };
+static const uint32_t CSR_ILP32D_LP64D_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00001fe0, };
+static const MCPhysReg CSR_ILP32F_LP64F_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31, 0 };
+static const uint32_t CSR_ILP32F_LP64F_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00000000, };
+static const MCPhysReg CSR_ILP32S_LP64S_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, 0 };
+static const uint32_t CSR_ILP32S_LP64S_RegMask[] = { 0x00000000, 0x00006000, 0x00001ff8, 0x00000000, };
+static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
+static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00002000, 0x00000000, 0x00000000, };
+
+
+ArrayRef<const uint32_t *> LoongArchGenRegisterInfo::getRegMasks() const {
+ static const uint32_t *const Masks[] = {
+ CSR_ILP32D_LP64D_RegMask,
+ CSR_ILP32F_LP64F_RegMask,
+ CSR_ILP32S_LP64S_RegMask,
+ CSR_NoRegs_RegMask,
+ };
+ return ArrayRef(Masks);
+}
+
+bool LoongArchGenRegisterInfo::
+isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
+ return
+ false;
+}
+
+bool LoongArchGenRegisterInfo::
+isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
+ return
+ false;
+}
+
+bool LoongArchGenRegisterInfo::
+isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
+ return
+ false;
+}
+
+bool LoongArchGenRegisterInfo::
+isConstantPhysReg(MCRegister PhysReg) const {
+ return
+ PhysReg == LoongArch::R0 ||
+ false;
+}
+
+ArrayRef<const char *> LoongArchGenRegisterInfo::getRegMaskNames() const {
+ static const char *Names[] = {
+ "CSR_ILP32D_LP64D",
+ "CSR_ILP32F_LP64F",
+ "CSR_ILP32S_LP64S",
+ "CSR_NoRegs",
+ };
+ return ArrayRef(Names);
+}
+
+const LoongArchFrameLowering *
+LoongArchGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
+ return static_cast<const LoongArchFrameLowering *>(
+ MF.getSubtarget().getFrameLowering());
+}
+
+} // end namespace llvm
+
+#endif // GET_REGINFO_TARGET_DESC
+
diff --git a/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenSubtargetInfo.inc b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenSubtargetInfo.inc
new file mode 100644
index 0000000..ba29052
--- /dev/null
+++ b/third_party/llvm-16.0/configs/common/lib/Target/LoongArch/LoongArchGenSubtargetInfo.inc
@@ -0,0 +1,261 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Subtarget Enumeration Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+namespace llvm {
+namespace LoongArch {
+enum {
+ Feature32Bit = 0,
+ Feature64Bit = 1,
+ FeatureBasicD = 2,
+ FeatureBasicF = 3,
+ FeatureExtLASX = 4,
+ FeatureExtLBT = 5,
+ FeatureExtLSX = 6,
+ FeatureExtLVZ = 7,
+ LaGlobalWithAbs = 8,
+ LaGlobalWithPcrel = 9,
+ LaLocalWithAbs = 10,
+ NumSubtargetFeatures = 11
+};
+} // end namespace LoongArch
+} // end namespace llvm
+
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+#ifdef GET_SUBTARGETINFO_MACRO
+GET_SUBTARGETINFO_MACRO(HasLA32, false, hasLA32)
+GET_SUBTARGETINFO_MACRO(HasLA64, false, hasLA64)
+GET_SUBTARGETINFO_MACRO(HasBasicD, false, hasBasicD)
+GET_SUBTARGETINFO_MACRO(HasBasicF, false, hasBasicF)
+GET_SUBTARGETINFO_MACRO(HasLaGlobalWithAbs, false, hasLaGlobalWithAbs)
+GET_SUBTARGETINFO_MACRO(HasLaGlobalWithPcrel, false, hasLaGlobalWithPcrel)
+GET_SUBTARGETINFO_MACRO(HasLaLocalWithAbs, false, hasLaLocalWithAbs)
+GET_SUBTARGETINFO_MACRO(HasExtLASX, false, hasExtLASX)
+GET_SUBTARGETINFO_MACRO(HasExtLBT, false, hasExtLBT)
+GET_SUBTARGETINFO_MACRO(HasExtLSX, false, hasExtLSX)
+GET_SUBTARGETINFO_MACRO(HasExtLVZ, false, hasExtLVZ)
+#undef GET_SUBTARGETINFO_MACRO
+#endif // GET_SUBTARGETINFO_MACRO
+
+
+#ifdef GET_SUBTARGETINFO_MC_DESC
+#undef GET_SUBTARGETINFO_MC_DESC
+
+namespace llvm {
+// Sorted (by key) array of values for CPU features.
+extern const llvm::SubtargetFeatureKV LoongArchFeatureKV[] = {
+ { "32bit", "LA32 Basic Integer and Privilege Instruction Set", LoongArch::Feature32Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "64bit", "LA64 Basic Integer and Privilege Instruction Set", LoongArch::Feature64Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "d", "'D' (Double-Precision Floating-Point)", LoongArch::FeatureBasicD, { { { 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "f", "'F' (Single-Precision Floating-Point)", LoongArch::FeatureBasicF, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "la-global-with-abs", "Expand la.global as la.abs", LoongArch::LaGlobalWithAbs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "la-global-with-pcrel", "Expand la.global as la.pcrel", LoongArch::LaGlobalWithPcrel, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "la-local-with-abs", "Expand la.local as la.abs", LoongArch::LaLocalWithAbs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "lasx", "'LASX' (Loongson Advanced SIMD Extension)", LoongArch::FeatureExtLASX, { { { 0x40ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "lbt", "'LBT' (Loongson Binary Translation Extension)", LoongArch::FeatureExtLBT, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "lsx", "'LSX' (Loongson SIMD Extension)", LoongArch::FeatureExtLSX, { { { 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "lvz", "'LVZ' (Loongson Virtualization Extension)", LoongArch::FeatureExtLVZ, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+};
+
+#ifdef DBGFIELD
+#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
+#endif
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
+#define DBGFIELD(x) x,
+#else
+#define DBGFIELD(x)
+#endif
+
+// ===============================================================
+// Data tables for the new per-operand machine model.
+
+// {ProcResourceIdx, Cycles}
+extern const llvm::MCWriteProcResEntry LoongArchWriteProcResTable[] = {
+ { 0, 0}, // Invalid
+}; // LoongArchWriteProcResTable
+
+// {Cycles, WriteResourceID}
+extern const llvm::MCWriteLatencyEntry LoongArchWriteLatencyTable[] = {
+ { 0, 0}, // Invalid
+}; // LoongArchWriteLatencyTable
+
+// {UseIdx, WriteResourceID, Cycles}
+extern const llvm::MCReadAdvanceEntry LoongArchReadAdvanceTable[] = {
+ {0, 0, 0}, // Invalid
+}; // LoongArchReadAdvanceTable
+
+#undef DBGFIELD
+
+static const llvm::MCSchedModel NoSchedModel = {
+ MCSchedModel::DefaultIssueWidth,
+ MCSchedModel::DefaultMicroOpBufferSize,
+ MCSchedModel::DefaultLoopMicroOpBufferSize,
+ MCSchedModel::DefaultLoadLatency,
+ MCSchedModel::DefaultHighLatency,
+ MCSchedModel::DefaultMispredictPenalty,
+ false, // PostRAScheduler
+ false, // CompleteModel
+ 0, // Processor ID
+ nullptr, nullptr, 0, 0, // No instruction-level machine model.
+ nullptr, // No Itinerary
+ nullptr // No extra processor descriptor
+};
+
+// Sorted (by key) array of values for CPU subtype.
+extern const llvm::SubtargetSubTypeKV LoongArchSubTypeKV[] = {
+ { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
+ { "generic-la32", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
+ { "generic-la64", { { { 0x2ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
+ { "la464", { { { 0xb2ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
+};
+
+namespace LoongArch_MC {
+unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
+ const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
+ // Don't know how to resolve this scheduling class.
+ return 0;
+}
+} // end namespace LoongArch_MC
+
+struct LoongArchGenMCSubtargetInfo : public MCSubtargetInfo {
+ LoongArchGenMCSubtargetInfo(const Triple &TT,
+ StringRef CPU, StringRef TuneCPU, StringRef FS,
+ ArrayRef<SubtargetFeatureKV> PF,
+ ArrayRef<SubtargetSubTypeKV> PD,
+ const MCWriteProcResEntry *WPR,
+ const MCWriteLatencyEntry *WL,
+ const MCReadAdvanceEntry *RA, const InstrStage *IS,
+ const unsigned *OC, const unsigned *FP) :
+ MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
+ WPR, WL, RA, IS, OC, FP) { }
+
+ unsigned resolveVariantSchedClass(unsigned SchedClass,
+ const MCInst *MI, const MCInstrInfo *MCII,
+ unsigned CPUID) const override {
+ return LoongArch_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
+ }
+ unsigned getHwMode() const override;
+};
+unsigned LoongArchGenMCSubtargetInfo::getHwMode() const {
+ if (checkFeatures("+64bit")) return 1;
+ return 0;
+}
+
+static inline MCSubtargetInfo *createLoongArchMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
+ return new LoongArchGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, LoongArchFeatureKV, LoongArchSubTypeKV,
+ LoongArchWriteProcResTable, LoongArchWriteLatencyTable, LoongArchReadAdvanceTable,
+ nullptr, nullptr, nullptr);
+}
+
+} // end namespace llvm
+
+#endif // GET_SUBTARGETINFO_MC_DESC
+
+
+#ifdef GET_SUBTARGETINFO_TARGET_DESC
+#undef GET_SUBTARGETINFO_TARGET_DESC
+
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+// ParseSubtargetFeatures - Parses features string setting specified
+// subtarget options.
+void llvm::LoongArchSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
+ LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
+ LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
+ LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
+ InitMCProcessorInfo(CPU, TuneCPU, FS);
+ const FeatureBitset &Bits = getFeatureBits();
+ if (Bits[LoongArch::Feature32Bit]) HasLA32 = true;
+ if (Bits[LoongArch::Feature64Bit]) HasLA64 = true;
+ if (Bits[LoongArch::FeatureBasicD]) HasBasicD = true;
+ if (Bits[LoongArch::FeatureBasicF]) HasBasicF = true;
+ if (Bits[LoongArch::FeatureExtLASX]) HasExtLASX = true;
+ if (Bits[LoongArch::FeatureExtLBT]) HasExtLBT = true;
+ if (Bits[LoongArch::FeatureExtLSX]) HasExtLSX = true;
+ if (Bits[LoongArch::FeatureExtLVZ]) HasExtLVZ = true;
+ if (Bits[LoongArch::LaGlobalWithAbs]) HasLaGlobalWithAbs = true;
+ if (Bits[LoongArch::LaGlobalWithPcrel]) HasLaGlobalWithPcrel = true;
+ if (Bits[LoongArch::LaLocalWithAbs]) HasLaLocalWithAbs = true;
+}
+#endif // GET_SUBTARGETINFO_TARGET_DESC
+
+
+#ifdef GET_SUBTARGETINFO_HEADER
+#undef GET_SUBTARGETINFO_HEADER
+
+namespace llvm {
+class DFAPacketizer;
+namespace LoongArch_MC {
+unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
+} // end namespace LoongArch_MC
+
+struct LoongArchGenSubtargetInfo : public TargetSubtargetInfo {
+ explicit LoongArchGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
+public:
+ unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
+ unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
+ DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
+ unsigned getHwMode() const override;
+};
+} // end namespace llvm
+
+#endif // GET_SUBTARGETINFO_HEADER
+
+
+#ifdef GET_SUBTARGETINFO_CTOR
+#undef GET_SUBTARGETINFO_CTOR
+
+#include "llvm/CodeGen/TargetSchedule.h"
+
+namespace llvm {
+extern const llvm::SubtargetFeatureKV LoongArchFeatureKV[];
+extern const llvm::SubtargetSubTypeKV LoongArchSubTypeKV[];
+extern const llvm::MCWriteProcResEntry LoongArchWriteProcResTable[];
+extern const llvm::MCWriteLatencyEntry LoongArchWriteLatencyTable[];
+extern const llvm::MCReadAdvanceEntry LoongArchReadAdvanceTable[];
+LoongArchGenSubtargetInfo::LoongArchGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
+ : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(LoongArchFeatureKV, 11), ArrayRef(LoongArchSubTypeKV, 4),
+ LoongArchWriteProcResTable, LoongArchWriteLatencyTable, LoongArchReadAdvanceTable,
+ nullptr, nullptr, nullptr) {}
+
+unsigned LoongArchGenSubtargetInfo
+::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
+ report_fatal_error("Expected a variant SchedClass");
+} // LoongArchGenSubtargetInfo::resolveSchedClass
+
+unsigned LoongArchGenSubtargetInfo
+::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
+ return LoongArch_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
+} // LoongArchGenSubtargetInfo::resolveVariantSchedClass
+
+unsigned LoongArchGenSubtargetInfo::getHwMode() const {
+ if (checkFeatures("+64bit")) return 1;
+ return 0;
+}
+} // end namespace llvm
+
+#endif // GET_SUBTARGETINFO_CTOR
+
+
+#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
+#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
+
+#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
+
+
+#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
+#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
+
+#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
+
diff --git a/third_party/llvm-16.0/configs/linux/include/llvm/Config/AsmParsers.def b/third_party/llvm-16.0/configs/linux/include/llvm/Config/AsmParsers.def
index 9893c66..2af3e28 100644
--- a/third_party/llvm-16.0/configs/linux/include/llvm/Config/AsmParsers.def
+++ b/third_party/llvm-16.0/configs/linux/include/llvm/Config/AsmParsers.def
@@ -33,6 +33,9 @@
#if defined(__i386__) || defined(__x86_64__)
LLVM_ASM_PARSER(X86)
#endif
+#if defined(__loongarch__)
+LLVM_ASM_PARSER(LoongArch)
+#endif
#if defined(__mips__)
LLVM_ASM_PARSER(Mips)
#endif
diff --git a/third_party/llvm-16.0/configs/linux/include/llvm/Config/AsmPrinters.def b/third_party/llvm-16.0/configs/linux/include/llvm/Config/AsmPrinters.def
index 523ee3b..2f675be 100644
--- a/third_party/llvm-16.0/configs/linux/include/llvm/Config/AsmPrinters.def
+++ b/third_party/llvm-16.0/configs/linux/include/llvm/Config/AsmPrinters.def
@@ -33,6 +33,9 @@
#if defined(__i386__) || defined(__x86_64__)
LLVM_ASM_PRINTER(X86)
#endif
+#if defined(__loongarch__)
+LLVM_ASM_PRINTER(LoongArch)
+#endif
#if defined(__mips__)
LLVM_ASM_PRINTER(Mips)
#endif
diff --git a/third_party/llvm-16.0/configs/linux/include/llvm/Config/Disassemblers.def b/third_party/llvm-16.0/configs/linux/include/llvm/Config/Disassemblers.def
index 4f61495..80e3a13 100644
--- a/third_party/llvm-16.0/configs/linux/include/llvm/Config/Disassemblers.def
+++ b/third_party/llvm-16.0/configs/linux/include/llvm/Config/Disassemblers.def
@@ -33,6 +33,9 @@
#if defined(__i386__) || defined(__x86_64__)
LLVM_DISASSEMBLER(X86)
#endif
+#if defined(__loongarch__)
+LLVM_DISASSEMBLER(LoongArch)
+#endif
#if defined(__mips__)
LLVM_DISASSEMBLER(Mips)
#endif
diff --git a/third_party/llvm-16.0/configs/linux/include/llvm/Config/Targets.def b/third_party/llvm-16.0/configs/linux/include/llvm/Config/Targets.def
index 0e68b41..d34b0ea 100644
--- a/third_party/llvm-16.0/configs/linux/include/llvm/Config/Targets.def
+++ b/third_party/llvm-16.0/configs/linux/include/llvm/Config/Targets.def
@@ -32,6 +32,9 @@
#if defined(__i386__) || defined(__x86_64__)
LLVM_TARGET(X86)
#endif
+#if defined(__loongarch__)
+LLVM_TARGET(LoongArch)
+#endif
#if defined(__mips__)
LLVM_TARGET(Mips)
#endif
diff --git a/third_party/llvm-16.0/configs/linux/include/llvm/Config/config.h b/third_party/llvm-16.0/configs/linux/include/llvm/Config/config.h
index 5e169c0..8788e3c 100644
--- a/third_party/llvm-16.0/configs/linux/include/llvm/Config/config.h
+++ b/third_party/llvm-16.0/configs/linux/include/llvm/Config/config.h
@@ -222,7 +222,7 @@
#define HAVE_UNISTD_H 1
/* Define to 1 if you have the <valgrind/valgrind.h> header file. */
-/* #undef HAVE_VALGRIND_VALGRIND_H */
+#define HAVE_VALGRIND_VALGRIND_H 1
/* Have host's _alloca */
/* #undef HAVE__ALLOCA */
diff --git a/third_party/llvm-16.0/configs/linux/include/llvm/Config/llvm-config.h b/third_party/llvm-16.0/configs/linux/include/llvm/Config/llvm-config.h
index ee2ca53..d9cce40 100644
--- a/third_party/llvm-16.0/configs/linux/include/llvm/Config/llvm-config.h
+++ b/third_party/llvm-16.0/configs/linux/include/llvm/Config/llvm-config.h
@@ -37,6 +37,8 @@
#define LLVM_DEFAULT_TARGET_TRIPLE "armv7-linux-gnueabihf"
#elif defined(__aarch64__)
#define LLVM_DEFAULT_TARGET_TRIPLE "aarch64-linux-gnu"
+#elif defined(__loongarch__)
+#define LLVM_DEFAULT_TARGET_TRIPLE "loongarch64-unknown-linux-gnu"
#elif defined(__mips__)
#define LLVM_DEFAULT_TARGET_TRIPLE "mipsel-linux-gnu"
#elif defined(__mips64)
@@ -64,6 +66,8 @@
#define LLVM_HOST_TRIPLE "armv7-linux-gnueabihf"
#elif defined(__aarch64__)
#define LLVM_HOST_TRIPLE "aarch64-linux-gnu"
+#elif defined(__loongarch__)
+#define LLVM_HOST_TRIPLE "loongarch64-unknown-linux-gnu"
#elif defined(__mips__)
#define LLVM_HOST_TRIPLE "mipsel-linux-gnu"
#elif defined(__mips64)
@@ -83,6 +87,8 @@
#define LLVM_NATIVE_ARCH ARM
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_ARCH X86
+#elif defined(__loongarch__)
+#define LLVM_NATIVE_ARCH LoongArch
#elif defined(__mips__)
#define LLVM_NATIVE_ARCH Mips
#elif defined(__powerpc64__)
@@ -100,6 +106,8 @@
#define LLVM_NATIVE_ASMPARSER LLVMInitializeARMAsmParser
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser
+#elif defined(__loongarch__)
+#define LLVM_NATIVE_ASMPARSER LLVMInitializeLoongArchAsmParser
#elif defined(__mips__)
#define LLVM_NATIVE_ASMPARSER LLVMInitializeMipsAsmParser
#elif defined(__powerpc64__)
@@ -117,6 +125,8 @@
#define LLVM_NATIVE_ASMPRINTER LLVMInitializeARMAsmPrinter
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter
+#elif defined(__loongarch__)
+#define LLVM_NATIVE_ASMPRINTER LLVMInitializeLoongArchAsmPrinter
#elif defined(__mips__)
#define LLVM_NATIVE_ASMPRINTER LLVMInitializeMipsAsmPrinter
#elif defined(__powerpc64__)
@@ -134,6 +144,8 @@
#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeARMDisassembler
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeX86Disassembler
+#elif defined(__loongarch__)
+#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeLoongArchDisassembler
#elif defined(__mips__)
#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeMipsDisassembler
#elif defined(__powerpc64__)
@@ -151,6 +163,8 @@
#define LLVM_NATIVE_TARGET LLVMInitializeARMTarget
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_TARGET LLVMInitializeX86Target
+#elif defined(__loongarch__)
+#define LLVM_NATIVE_TARGET LLVMInitializeLoongArchTarget
#elif defined(__mips__)
#define LLVM_NATIVE_TARGET LLVMInitializeMipsTarget
#elif defined(__powerpc64__)
@@ -168,6 +182,8 @@
#define LLVM_NATIVE_TARGETINFO LLVMInitializeARMTargetInfo
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_TARGETINFO LLVMInitializeX86TargetInfo
+#elif defined(__loongarch__)
+#define LLVM_NATIVE_TARGETINFO LLVMInitializeLoongArchTargetInfo
#elif defined(__mips__)
#define LLVM_NATIVE_TARGETINFO LLVMInitializeMipsTargetInfo
#elif defined(__powerpc64__)
@@ -185,6 +201,8 @@
#define LLVM_NATIVE_TARGETMC LLVMInitializeARMTargetMC
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_TARGETMC LLVMInitializeX86TargetMC
+#elif defined(__loongarch__)
+#define LLVM_NATIVE_TARGETMC LLVMInitializeLoongArchTargetMC
#elif defined(__mips__)
#define LLVM_NATIVE_TARGETMC LLVMInitializeMipsTargetMC
#elif defined(__powerpc64__)
diff --git a/third_party/llvm-16.0/configs/windows/include/llvm/Config/llvm-config.h b/third_party/llvm-16.0/configs/windows/include/llvm/Config/llvm-config.h
index 38123d4..2078fbc 100644
--- a/third_party/llvm-16.0/configs/windows/include/llvm/Config/llvm-config.h
+++ b/third_party/llvm-16.0/configs/windows/include/llvm/Config/llvm-config.h
@@ -22,6 +22,10 @@
#define __x86_64__ 1
#endif
+#if !defined(__aarch64__) && (defined(_M_ARM64) || defined (_M_ARM64EC))
+#define __aarch64__ 1
+#endif
+
#define LLVM_CONFIG_H
/* Define if LLVM_ENABLE_DUMP is enabled */
diff --git a/third_party/llvm-16.0/scripts/generate_build_files.py b/third_party/llvm-16.0/scripts/generate_build_files.py
index f6690a6..4d182e6 100755
--- a/third_party/llvm-16.0/scripts/generate_build_files.py
+++ b/third_party/llvm-16.0/scripts/generate_build_files.py
@@ -361,6 +361,7 @@
files_llvm_debug = [
"/lib/Analysis/RegionPrinter.cpp",
+ "/lib/MC/MCDisassembler/MCDisassembler.cpp",
]
files_to_add_back_for_llvm_arm = [
@@ -370,6 +371,11 @@
"/lib/Transforms/IPO/BarrierNoopPass.cpp",
]
+files_to_add_back_for_llvm_loongarch = [
+ "/lib/TargetParser/LoongArchTargetParser.cpp",
+ "/lib/Transforms/IPO/BarrierNoopPass.cpp",
+]
+
files_to_add_back_for_llvm_riscv = [
"/lib/TargetParser/RISCVTargetParser.cpp",
"/lib/Transforms/IPO/BarrierNoopPass.cpp",
@@ -384,6 +390,9 @@
files_ARM = keep_files_with_prefix(all_files, "/lib/Target/ARM/")
files_ARM.extend(files_to_add_back_for_llvm_arm)
files_ARM.sort()
+files_LoongArch = keep_files_with_prefix(all_files, "/lib/Target/LoongArch/")
+files_LoongArch.extend(files_to_add_back_for_llvm_loongarch)
+files_LoongArch.sort()
files_PowerPC = keep_files_with_prefix(all_files, "/lib/Target/PowerPC/")
files_RISCV = keep_files_with_prefix(all_files, "/lib/Target/RISCV/")
files_RISCV.extend(files_to_add_back_for_llvm_riscv)
@@ -398,6 +407,7 @@
'generated_file_comment' : "# " + generated_file_comment,
'files_llvm' : '\n'.join([" ${LLVM_DIR}" + s for s in files_llvm]),
'files_x86' : format_file_list_for_cmake(files_x86),
+ 'files_LoongArch' : format_file_list_for_cmake(files_LoongArch),
'files_Mips' : format_file_list_for_cmake(files_Mips),
'files_AArch64' : format_file_list_for_cmake(files_AArch64),
'files_ARM' : format_file_list_for_cmake(files_ARM),
@@ -446,7 +456,8 @@
def partition_paths(filepaths):
partitions = []
for path in filepaths:
- filename = get_filename(path)
+ # Convert to lower case to support case-insensitive filesystem
+ filename = get_filename(path).lower()
inserted = False
for partition in partitions:
if not filename in partition:
@@ -493,9 +504,11 @@
'files_x86' : format_file_list_for_build_gn(files_x86),
'files_AArch64' : format_file_list_for_build_gn(files_AArch64),
'files_ARM' : format_file_list_for_build_gn(files_ARM_build_gn),
+ 'files_LoongArch' : format_file_list_for_build_gn(files_LoongArch),
'files_Mips' : format_file_list_for_build_gn(files_Mips),
'files_PowerPC' : format_file_list_for_build_gn(files_PowerPC),
'files_RISCV' : format_file_list_for_build_gn(files_RISCV),
+ 'files_llvm_debug': format_file_list_for_build_gn(files_llvm_debug),
}
with open(BUILD_GN_TEMPLATE_PATH, 'r') as f:
build_gn_template = CustomTemplate(f.read())
diff --git a/third_party/llvm-16.0/scripts/template_BUILD.gn b/third_party/llvm-16.0/scripts/template_BUILD.gn
index 72c21f5..8d18e21 100644
--- a/third_party/llvm-16.0/scripts/template_BUILD.gn
+++ b/third_party/llvm-16.0/scripts/template_BUILD.gn
@@ -97,6 +97,7 @@
"llvm/include/",
"llvm/lib/Target/AArch64/",
"llvm/lib/Target/ARM/",
+ "llvm/lib/Target/LoongArch/",
"llvm/lib/Target/Mips/",
"llvm/lib/Target/PowerPC/",
"llvm/lib/Target/RISCV/",
@@ -106,6 +107,7 @@
"configs/common/lib/IR/",
"configs/common/lib/Target/AArch64/",
"configs/common/lib/Target/ARM/",
+ "configs/common/lib/Target/LoongArch/",
"configs/common/lib/Target/Mips/",
"configs/common/lib/Target/PowerPC/",
"configs/common/lib/Target/RISCV/",
@@ -156,10 +158,16 @@
%$%llvm_deps
]
+ if (is_debug) {
+ deps += [ ":swiftshader_llvm_debug" ]
+ }
+
if (current_cpu == "arm64") {
deps += [ ":swiftshader_llvm_aarch64" ]
} else if (current_cpu == "arm") {
deps += [ ":swiftshader_llvm_arm" ]
+ } else if (current_cpu == "loong64") {
+ deps += [ ":swiftshader_llvm_loongarch64" ]
} else if (current_cpu == "mipsel" || current_cpu == "mips64el") {
deps += [ ":swiftshader_llvm_mips" ]
} else if (current_cpu == "ppc64") {
@@ -186,6 +194,12 @@
# split out into their own source_set.
%$%llvm_source_sets
+swiftshader_llvm_source_set("swiftshader_llvm_debug") {
+ sources = [
+%$%files_llvm_debug
+ ]
+}
+
swiftshader_llvm_source_set("swiftshader_llvm_aarch64") {
sources = [
%$%files_AArch64
@@ -203,6 +217,12 @@
}
}
+swiftshader_llvm_source_set("swiftshader_llvm_loongarch64") {
+ sources = [
+%$%files_LoongArch
+ ]
+}
+
swiftshader_llvm_source_set("swiftshader_llvm_mips") {
sources = [
%$%files_Mips
diff --git a/third_party/llvm-16.0/scripts/template_CMakeLists.txt b/third_party/llvm-16.0/scripts/template_CMakeLists.txt
index cbe22d5..d60bf15 100644
--- a/third_party/llvm-16.0/scripts/template_CMakeLists.txt
+++ b/third_party/llvm-16.0/scripts/template_CMakeLists.txt
@@ -37,6 +37,10 @@
list(APPEND LLVM_LIST
%$%files_ARM
)
+elseif(ARCH STREQUAL "loongarch64")
+ list(APPEND LLVM_LIST
+%$%files_LoongArch
+ )
elseif(ARCH STREQUAL "ppc64le")
list(APPEND LLVM_LIST
%$%files_PowerPC
@@ -74,6 +78,7 @@
${LLVM_DIR}/include
${LLVM_DIR}/lib/Target/AArch64
${LLVM_DIR}/lib/Target/ARM
+ ${LLVM_DIR}/lib/Target/LoongArch
${LLVM_DIR}/lib/Target/Mips
${LLVM_DIR}/lib/Target/PowerPC
${LLVM_DIR}/lib/Target/RISCV
@@ -82,6 +87,7 @@
${LLVM_CONFIG_DIR}/common/lib/IR
${LLVM_CONFIG_DIR}/common/lib/Target/AArch64
${LLVM_CONFIG_DIR}/common/lib/Target/ARM
+ ${LLVM_CONFIG_DIR}/common/lib/Target/LoongArch
${LLVM_CONFIG_DIR}/common/lib/Target/Mips
${LLVM_CONFIG_DIR}/common/lib/Target/PowerPC
${LLVM_CONFIG_DIR}/common/lib/Target/RISCV
diff --git a/third_party/llvm-16.0/scripts/update.py b/third_party/llvm-16.0/scripts/update.py
index 113790c..7c3641a 100644
--- a/third_party/llvm-16.0/scripts/update.py
+++ b/third_party/llvm-16.0/scripts/update.py
@@ -44,6 +44,7 @@
('AArch64', ('__aarch64__',)),
('ARM', ('__arm__',)),
('X86', ('__i386__', '__x86_64__')),
+ ('LoongArch', ('__loongarch__',)),
('Mips', ('__mips__',)),
('PowerPC', ('__powerpc64__',)),
('RISCV', ('__riscv',)),
@@ -63,6 +64,7 @@
('__i386__', 'i686-pc-linux-gnu'),
('__arm__', 'armv7-linux-gnueabihf'),
('__aarch64__', 'aarch64-linux-gnu'),
+ ('__loongarch__', 'loongarch64-unknown-linux-gnu'),
('__mips__', 'mipsel-linux-gnu'),
('__mips64', 'mips64el-linux-gnuabi64'),
('__powerpc64__', 'powerpc64le-unknown-linux-gnu'),
