waipio-v2-mmrm-test.dtsi

&soc {
	msm_mmrm_test: qcom,mmrm-test {
		compatible = "qcom,msm-mmrm-test", "qcom,waipio-mmrm-test";
		status = "disable";

		/* Clock info */
		clock-names =
			"cam_cc_ife_0_clk_src",
			"cam_cc_ife_1_clk_src",
			"cam_cc_ife_2_clk_src",
			"cam_cc_csid_clk_src",
			"cam_cc_sfe_0_clk_src",
			"cam_cc_sfe_1_clk_src",
			"cam_cc_ipe_nps_clk_src",
			"cam_cc_bps_clk_src",
			"cam_cc_ife_lite_clk_src",
			"cam_cc_jpeg_clk_src",
			"cam_cc_camnoc_axi_clk_src",
			"cam_cc_ife_lite_csid_clk_src",
			"cam_cc_icp_clk_src",
			"cam_cc_cphy_rx_clk_src",
			"cam_cc_csi0phytimer_clk_src",
			"cam_cc_csi1phytimer_clk_src",
			"cam_cc_csi2phytimer_clk_src",
			"cam_cc_csi3phytimer_clk_src",
			"cam_cc_csi4phytimer_clk_src",
			"cam_cc_csi5phytimer_clk_src",
			"cam_cc_cci_0_clk_src",
			"cam_cc_cci_1_clk_src",
			"cam_cc_slow_ahb_clk_src",
			"cam_cc_fast_ahb_clk_src",
			"video_cc_mvs1_clk_src",
			"disp_cc_mdss_mdp_clk_src",
			"disp_cc_mdss_dptx0_link_clk_src",
			"video_cc_mvs0_clk_src";
		clocks =
			<&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
			<&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
			<&clock_camcc CAM_CC_IFE_2_CLK_SRC>,
			<&clock_camcc CAM_CC_CSID_CLK_SRC>,
			<&clock_camcc CAM_CC_SFE_0_CLK_SRC>,
			<&clock_camcc CAM_CC_SFE_1_CLK_SRC>,
			<&clock_camcc CAM_CC_IPE_NPS_CLK_SRC>,
			<&clock_camcc CAM_CC_BPS_CLK_SRC>,
			<&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
			<&clock_camcc CAM_CC_JPEG_CLK_SRC>,
			<&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
			<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
			<&clock_camcc CAM_CC_ICP_CLK_SRC>,
			<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
			<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
			<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
			<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
			<&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
			<&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
			<&clock_camcc CAM_CC_CCI_0_CLK_SRC>,
			<&clock_camcc CAM_CC_CCI_1_CLK_SRC>,
			<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
			<&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>,
			<&clock_videocc VIDEO_CC_MVS1_CLK_SRC>,
			<&clock_dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
			<&clock_dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
			<&clock_videocc VIDEO_CC_MVS0_CLK_SRC>;
		clock_rates =
			<0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
			<0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
			<0x1 CAM_CC_IFE_2_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
			<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
			<0x1 CAM_CC_SFE_0_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
			<0x1 CAM_CC_SFE_1_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
			<0x1 CAM_CC_IPE_NPS_CLK_SRC 364000000 500000000 600000000 700000000 700000000>,
			<0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
			<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
			<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
			<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000>,
			<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
			<0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000>,
			<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
			<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
			<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
			<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
			<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
			<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
			<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
			<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
			<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
			<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000>,
			<0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 300000000 400000000 400000000>,
			<0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 1500000000 1650000000 1650000000>,
			<0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 375000000 500000000 500000000>,
			<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000 270000 540000 810000 810000>,
			<0x4 VIDEO_CC_MVS0_CLK_SRC 720000000 1014000000 1098000000 1332000000 1332000000>;
	};
};