| commit | b63e22cff9601ab2249ce5b6371a5ca9e663ce09 | [log] [tgz] |
|---|---|---|
| author | Jean-Marc Valin <jmvalin@amazon.com> | Tue Dec 19 01:55:28 2023 -0500 |
| committer | Jean-Marc Valin <jmvalin@jmvalin.ca> | Thu Jan 25 02:19:35 2024 -0500 |
| tree | 00556354cf1db4d0e1501be77313dffbe0fa56c9 | |
| parent | 7b73c9bc7ff8e54bb6b72aad500bdab5d031aee0 [diff] |
Fix desync for CBR DRED The encoder wouldn't reserve enough bits for CELT, causing it to not have enough bits to code the switching redundancy flag when it should have.